Details Of Registers; Tselxcr0] (Control Register 0) - Toshiba TMPM4K Series Reference Manual

2.2.4. Details of Registers

The following chapters show the detail of registers. The sign in the functional column parenthesis of each table
expresses each function signal name.

2.2.4.1. [TSELxCR0] (Control Register 0)

Bit Bit Symbol
31 -
30:28 INSEL3[2:0]
27 -
26 UPDN3
25 OUTSEL3
24 EN3
23 -
22:20 INSEL2[2:0]
19 -
18 UPDN2
17 OUTSEL2
16 EN2
15 -
2018-09-18
After
Type
Reset
0 R Read as 0
Select the input trigger (DMA ch21)
000: T32A ch4 DMA request at match A1 register (T32A04DMAREQCMPA1)
001: T32A ch4 DMA request at match C1 register(T32A04DMAREQCMPC1)
010: T32A ch5 DMA request at match A1 register(T32A05DMAREQCMPA1)
000 R/W
011: T32A ch5 DMA request at match C1 register(T32A05DMAREQCMPC1)
100: Reserved
101: Reserved
110: Reserved
111: Reserved
0 R Read as 0
Edge detection
0 R/W
0: Rising edge detection
1: falling edge detection
Select the output trigger
0 R/W
0: The edge detection is disable
1: The edge detection is enable
Trigger output control
0 R/W
0: Disable
1: Enable
0 R Read as 0
Select the input trigger (DMA ch20)
000: T32A ch2 DMA request at match A1 register(T32A02DMAREQCMPA1)
001: T32A ch2 DMA request at match C1 register(T32A02DMAREQCMPC1)
010: T32A ch3 DMA request at match A1 register(T32A03DMAREQCMPA1)
000 R/W
011: T32A ch3 DMA request at match C1 register(T32A03DMAREQCMPC1)
100: A-PMD ch1 PWM interrupt (INTPWM1)
101: Reserved
110: Reserved
111: Reserved
0 R Read as 0
Edge detection
0 R/W
0: Rising edge detection
1: Falling edge detection
Select the output trigger
0 R/W
0: The edge detection is disable
1: The edge detection is enable
Trigger output control
0 R/W
0: Disable
1: Enable
Read as 0
0 R
Function
20 / 89
TMPM4K Group(1)
Product Inromation
Rev. 2.1