Infineon XDPP1100 Technical Reference Manual page 46

XDPP1100 technical reference manual
Digital power controller
Current sense (IS)
Figure 24 HBCT topology FET naming
Table 9 HBCT PWM state programming example
FET PWM Register programming
output
Q1 PWM1 Set bit field values corresponding PWM1 to 1 and other bit fields
to 0 in ceX_on_mask0
Q2 PWM2 Set bit field values corresponding PWM2 to 1 and other bit fields
to 0 in ceX_on_mask1
SR1 PWM3 Set bit field values corresponding PWM3 to 1 and other bit fields
to 0 in ceX_off_mask1
SR2 PWM4 Set bit field values corresponding PWM4 to 1 and other bit fields
to 0 in ceX_off_mask0
HBCD topology
d)
The HBCD topology adds an inductor to the secondary in order to double the maximum available current. The
simplified topology is shown in
inductor L2 on-time. The off-time for L1 is defined by SR1, and correspondingly the off-time for L2 is specified
by SR2. Table 10 describes the relevant programming for this topology.
Figure 25 HBCD FET naming
User Manual
Figure 25, where Q1 defines the on-time for inductor L1, and Q2 defines the
C
Q
1
1
N:1
V
IN
r
w1
Q
2 C
2
L
SR 1
1
C
OUT
r
w2
SR
2
L
2
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Register value
ceX_on_mask0 =
001h
ceX_on_mask1 =
002h
ceX_off_mask1 =
004h
ceX_off_mask0 =
008h
+
V
OUT
R
LOAD
-
V 1.0
2021-08-25