PCI Express GRL-PCIE-TX Quick Start User Manual

5.0 transmitter compliance test automation solution

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GRL-PCIE-TX PCI Express

5.0 Transmitter Compliance Test

Automation Solution

Quick Start/User Guide/Method of Implementation (MOI)

for PCIe Gen5 Physical Layer Transmitter Test Application

Published on 26 March 2022

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Page 1 GRL-PCIE-TX PCI Express 5.0 Transmitter Compliance Test ® Automation Solution Quick Start/User Guide/Method of Implementation (MOI) for PCIe Gen5 Physical Layer Transmitter Test Application Published on 26 March 2022...
Page 2 The PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Page 3: Table Of Contents
6 SAVING AND LOADING GRL-PCIE-TX TEST SESSIONS 7 APPENDIX A: METHOD OF IMPLEMENTATION (MOI) FOR MANUAL PCIE 5.0 TRANSMITTER MEASUREMENTS ................34 YSTEM OARD IGNAL UALITY ................... 37 IGNAL UALITY GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.3...
Page 4 ITTER (100 MH ..............44 YSTEM OARD LOCK ITTER 8 APPENDIX B: CONNECTING KEYSIGHT OSCILLOSCOPE TO PC 9 APPENDIX C: CONNECTING TEKTRONIX OSCILLOSCOPE TO PC GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.4...
Page 5: Introduction
This documentation covers the following major components for PCIe Tx testing. 1. GRL-P1 hardware controller setup. 2. GRL-PCIE-TX software configuration and test setup. Note: For manual test methodology, please refer to PCI-SIG SEG for approved vendor specific Method of Implementation (MOI’s) as technical reference. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0...
Page 6: Resource Requirements
Advanced Technology eXtended (ATX) Power For power supply to the DUT Supply GRL Switch (Optional) For multi-lane automated testing PCI-SIG Compliance Base Board (CBB) For add-in cards PCI-SIG Compliance Load Board (CLB) For hosts Computer (laptop or desktop) Windows 7+ OS For automation control of the DUT state Oscilloscope with scope software requirements as specified in vendor specific MOI’s.
Page 7: Software Requirements
Software Requirements 3. S ABLE OFTWARE EQUIREMENTS Software Description/Source GRL-PCIE-TX Granite River Labs PCI Express 5.0 Automated Transmitter Compliance Test ® Solution (hardware & software) – www.graniteriverlabs.com Further automation license for Custom DUT, RF Switch, or other bench automation – www.graniteriverlabs.com...
Page 8: Setting Up Grl-Pcie-Tx Automation Software
Click on GRL – Automated Test Solutions within the GRL folder to launch the GRL software framework. 1. S GRL F IGURE ELECT AND AUNCH RAMEWORK GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.8...
Page 9 • If you do not have an Activation Key, select “Close” to use a demo version of the software over a free 10-day trial period. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.9...
Page 10 GRL software is installed on the PC to control the Scope, type in the Scope IP address, for example “TCPIP0::192.168.0.110::inst0::INSTR”. Note to omit the Port number from the address. The “lightning” button should turn green if successfully connected to the instrument. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.10...
Page 11: Pre-Configure Grl-Pcie-Tx Software Before Testing
PCIe data lanes, data rates, and preset settings that are selected. a) Lane tab: Select the desired data lanes to be tested. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.11...
Page 12 Data Rate tab: Select the desired PCIe data rates for testing. 8. S IGURE ELECT ATES c) Preset tab: Select the pre-defined Tx presets as required for Tx equalization. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.12...
Page 13 9. S IGURE ELECT RESETS GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.13...
Page 14: Testing Using Grl-Pcie-Tx
PCIe Gen5. Optionally an arbitrary function generator can also be used as an alternative compliance toggle controller. The GRL-P1 controller can be connected to either a PCI-SIG compliance load board (CLB) test fixture for the system board DUT or compliance base board (CBB) test fixture for the add-in card DUT.
Page 15: Connect Equipment For System Board Dut Test
5. Connect the CLB Rx- Lane to the GRL-P1 Output 2. 6. Connect the power control adapter cable from the ATX power supply to the DUT. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.15...
Page 16: Connect Equipment For Add-In Card Dut Test
The following diagrams describe how to connect the equipment if using GRL-P1 with the PCIe Gen5 Compliance Base Board (CBB). Note the use of GRL-P1 in the setup is optional. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.16...
Page 17 8. Connect GRL-P1 to the Scope using a USB cable. 9. If using ISI, connect a 12.5 dB ISI in between the CBB Tx outputs and Scope channels (Figure 13 below). GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.17...
Page 18 13. C GRL-P1 ( ISI) IGURE ONCEPTUAL ETUP IAGRAM SING WITH GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.18...
Page 19: Connect Equipment For System Ref Clock Jitter Test
3. Connect Ref Clk- from the CLB to Channel 3 of the Scope. 1. Connect the power control adapter cable from the ATX power supply to the DUT. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.19...
Page 20: Set Up Test Requirements
• PCIE Gen5 (32Gb/s) ‒ Enter the SigTest Version for running Signal Quality (SQ) or Preset Tests and also make sure that the SigTest is already installed in the system. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.20...
Page 21 “Waveform Acquisition” group from the Select Tests page. See Section 4.2.5.1. If “Process Pre-captured waveforms” is selected, enter the directory of the saved waveform file in the Pre-Captured Waveform Path field. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.21...
Page 22: Select Compliance Tests
DUT, only those tests applicable for System Board will be shown. Other test parameters such as desired data rates and presets that were previously configured may also affect the test selection. 20. S IGURE ELECT ESTS GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.22...
Page 23 Under “Waveform Analysis”, select to perform the SigTest analysis, jitter and eye measurements, and preset test for the applicable PCIe Gen5 waveform. The software will automatically run the selected tests when initiated. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.23...
Page 24 23. S IGURE ELECT AVEFORM NALYSIS ESTS FOR YSTEM OARD 24. S IGURE ELECT AVEFORM NALYSIS ESTS FOR GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.24...
Page 25: Configure Test Parameters
Select to use the GRL-P1 hardware controller to provide compliance toggle signal to control the compliance state of the DUT. Select “None” if using manual compliance toggle. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.25...
Page 26 Select the SigTest to run Sequential or Parallel signal quality SigTest Run Mode testing to ensure waveform compliance. SigTest Max Thread Specify the maximum number of threads for each SigTest run. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.26...
Page 27: Run Automation Tests
Follow the step by step instructions to complete the entire testing. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.27...
Page 28: Interpreting Grl-Pcie-Tx Test Report
Select the Generate report button to generate the test report. 5.1.1 Test Session Information This portion displays the information previously entered on the Session Info page. 28. T IGURE ESSION NFORMATION XAMPLE GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.28...
Page 29: Test Summary Table
IGURE UMMARY ABLE XAMPLE 5.1.3 Test Results This portion displays the results of each test performed in detail along with supporting data points and screenshots. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.29...
Page 30 GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.30...
Page 31 GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.31...
Page 32: Delete Test Results
Delete Test Results Select the Delete button to delete individual test results or Delete All to delete all test results. 31. D IGURE ELETE ESULTS GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.32...
Page 33: Saving And Loading Grl-Pcie-Tx Test Sessions
The test configuration and session results are saved in a file with the ‘.ses’ extension, which is a compressed zip-style file, containing a variety of information. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.33...
Page 34: Appendix A: Method Of Implementation (Moi) For Manual Pcie
• Sampling Rate: ≥ 128 GS/s (2x interpolation allowed) 3. Refer to “Appendix B, Section B.11, Target Loss Values – Tx Signal Quality” in the PCI Express Architecture PHY Test Specification, Revision 5.0, Version 0.9 to determine the target loss and locate the S4P file to be embedded on the Scope.
Page 35 7. Measure both the Eye Height and Eye Width @1e-12 on SigTest Phoenix using the “PCIe\5_0\System\Optimize_CTLE” template file. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.35...
Page 36 8. Make sure that each DUT test lane achieves the following target Eye Height and Eye Width values for at least one Tx EQ Preset: • Eye Width ≥ 9.688 ps ±0.5 ps • Eye Height ≥ 17.5 mV ±1.5 mV GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.36...
Page 37: Add-In Card Tx Signal Quality Test
• Sampling Rate: ≥ 128 GS/s (2x interpolation allowed) 4. Refer to “Appendix B, Section B.11, Target Loss Values – Tx Signal Quality” in the PCI Express Architecture PHY Test Specification, Revision 5.0, Version 0.9 to determine the target loss and locate the S4P file to be embedded on the Scope.
Page 38 9. Make sure that each DUT test lane achieves the following target Eye Height and Eye Width values for at least one Tx EQ Preset: • Eye Width ≥ 10.625 ps ±0.5 ps • Eye Height ≥ 22 mV ±1.5 mV GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.38...
Page 39: System Board T X Preset
5. Save waveforms of all presets as “AIC_LaneX_Gen5_P0Y_d_.wtf”, where: • X = Lane number (0 to 15) • Y = Preset number (0 to 10) GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.39...
Page 40 6. To test the presets, load the saved preset files in SigTest Phoenix (by selecting PCIe → 5_0 → PresetTestAC → Template “No_CTLE” → Browse) and run the preset tests (by selecting Test). GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.40...
Page 41: And Udjdd) Test
5. To measure UPW-TJ, UPW-DJDD, UTJ, and UDJDD, load the saved waveform files in SigTest Phoenix (by selecting PCIe → 5_0 → Base → Browse → Load and Verify Data). GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.41...
Page 42: And Udjdd) Test
Phoenix (by selecting PCIe → 5_0 → Base → Browse → Load and Verify Data). 7. Measure UPW-TJ, UPW-DJDD, UTJ, and UDJDD @1e-12 on SigTest Phoenix using the “Templates\PCIe\5_0\Base\Optimize_CTLE” template file and select Test to start the measurements. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.42...
Page 43 8. The test is considered as Pass if the following target jitter parameter values are met: • UPW-TJ ≤ 6.25 ps • UPW-DJDD ≤ 2.5 ps • UTJ ≤ 6.25 ps • UDJDD ≤ 3.125 ps GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.43...
Page 44: Z ) Jitter Test
4. Using the Clock Jitter Tool, measure the HF RJ RMS (Max Phase Jitter) as shown in figure below. 5. The test is considered as Pass if the HF RJ RMS (Max Phase Jitter) is ≤ 200 fs. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.44...
Page 45 ‘Address’ field on the Equipment Setup page of the GRL PCIe Tx Test Application. If connected via LAN, type in the Scope IP address, for example “TCPIP0::192.168.0.110::inst0::INSTR”. Note to omit the Port number from the address. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.45...
Page 46 “Instrument Identify”: Select to use a supported programming language to send a query to identify the selected instrument. d) “Properties”: Select to display and view the selected instrument properties. GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.46...
Page 47 “GPIB8::1::INSTR”. If the GRL software is installed on the PC to control the Scope, type in the Scope IP address, for example “TCPIP0::192.168.0.110::inst0::INSTR”. Note to omit the Port number from the address. END_OF_DOCUMENT GRL-PCIE-TX Quick Start/User Guide/MOI Rev1.0 © PCI-SIG 2022 Version 1.0, Mar 2022. Updated 03.26.2022 Page.47...