Soc.shcfg1; Register 10-16 Soc.shcfg1 (Sample And Hold Configuration, 15H) - Qorvo PAC5556 User Manual

10.18.16

SOC.SHCFG1

Register 10-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)

BIT NAME
7:5 RFU
4 EMUXEN
3 ADCBUFEN
2 DAO54SH
1 DAO32SH
0 DAO10SH
ACCESS RESET
R 000b
RW 0b
RW 0b
RW 0b
RW 0b
RW 0b
-97-
Power Application Controller
DESCRIPTION
Reserved, write to 0x0.
EMUX Enable:
0b: Disabled. Writing this bit to 0b will reset the EMUX.
1b: Enabled
ADCBUF Circuit Enable:
0b: Disabled
1b: Enabled
Enable sample and hold circuit to synchronize the Differential
Amplifier 54 output to ADCIN:
0b: Disabled
1b: Enabled
Enable sample and hold circuit to synchronize the Differential
Amplifier 32 output to ADCIN:
0b: Disabled
1b: Enabled
Enable sample and hold circuit to synchronize the Differential
Amplifier 10 output to ADCIN:
0b: Disabled
1b: Enabled
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Copyright 2020 Qorvo, Inc.
Rev 2.2 – Nov 25, 2020