Page 1 AT32F415 Series Reference Manual ® ® -based 32-bit Cortex -M4 MCU, with 64 Kbyte ~ 256 Kbyte Internal Flash, sLib, USB-OTG, 11 Timers, 2 COMPs,1 ADC, 12 Communication Interfaces Function   ® ® Core: ARM 32-bit Cortex -M4 CPU Up to 11 Timers −...
Page 2: Table Of Contents
AT32F415 Series Reference Manual Contents System Architecture .................... 41 System Introduction ..................41 1.1.1 Bus Architecture ..................43 ® 1.1.2 ARM Cortex -M4 Processer ..............43 Address Map ....................44 1.2.1 Register Map ..................46 1.2.2 Bit Banding ..................... 47 1.2.3...
Page 3 AT32F415 Series Reference Manual Reset......................65 3.1.1 System Reset ..................65 3.1.2 Power Reset ................... 65 3.1.3 Backup Domain Reset ................66 Clocks ......................66 3.2.1 HSE Clock ....................68 3.2.2 HSI Clock ....................69 3.2.3 PLL ......................69 3.2.4 LSE Clock ....................
Page 4 AT32F415 Series Reference Manual EFC Introduction ..................... 94 Main Features ....................94 4.2.1 Flash Memory Architecture ..............94 Function Overview ................... 97 4.3.1 Read Operation ..................97 4.3.1.1 Instruction Fetch ................97 4.3.1.2 D-Code Interface ................98 4.3.1.3 Flash Access Controller ..............98 4.3.2...
Page 5 AT32F415 Series Reference Manual 4.4.9 Flash sLib Status Register 0 (FLASH_CDR0) .......... 114 4.4.10 Flash sLib Status Register 1 (FLASH_CDR1) .......... 115 4.4.11 Flash sLib Password Register (FSLI B_PSW ) ........... 117 4.4.12 Flash sLib Password Setting Status Register (FLASH_PSW _STS) .... 117 4.4.13...
Page 6 AT32F415 Series Reference Manual 6.3.7 Alternate Function (AF) ................. 132 IO Mapping Function Configuration ..............136 6.4.1 OSC32_IN/OSC32_OUT as GPIO Interface PC14/PC15 ......136 6.4.2 OSC_IN/OSC_OUT Pin as GPIO Interface PD0/PD1 ........ 136 6.4.3 CAN Alternate Function Remapping ............136 6.4.4...
Page 7 AT32F415 Series Reference Manual 6.5.19 AF Remap and Debug I/O Configuration Register 7 (AFIO_MAP7) .... 155 6.5.20 AF Remap and Debug I/O Configuration Register 8 (AFIO_MAP8 ) .... 157 Interrupts and Events ..................158 Nested Vectored Interrupt Controller ............... 158 7.1.1...
Page 8 AT32F415 Series Reference Manual 8.4.1 DMA Interrupt Status Register (DMA_ISTS) ..........179 8.4.2 DMA Interrupt Flag Clear Register (DMA_ICLR) ........180 DMA Channel x Configuration Register (DMA_CHCTRLx) (x = 1 … 7) ..180 8.4.3 DMA Channel x Number of Data Register (DMA_TCNTx) (x = 1 … 7) ..182 8.4.4...
Page 9 AT32F415 Series Reference Manual 9.1.4.3 Slave Mode Control Register (TMRx_SMC) ........219 9.1.4.4 DMA/Interrupt Enable Register (TMRx_DIE) ........221 9.1.4.5 Status Register (TMRx_STS) ............222 9.1.4.6 Event Generation Register (TMRx_EVEG) ........223 9.1.4.7 Capture/Compare Mode Register 1 (TMRx_CCM1) ......224 9.1.4.8...
Page 10 AT32F415 Series Reference Manual 9.2.3.11 Timer and External Trigger Synchronization (TMR9 Only) ....247 9.2.3.12 Timer Synchronization (TMR9 Only) ..........249 9.2.3.13 Debug Mode ................. 249 9.2.4 TMR9 Register Description ..............249 9.2.4.1 Control Register 1 (TMRx_CTRL1) ..........251 9.2.4.2 Slave Mode Control Register (TMRx_SMC) ........
Page 11 AT32F415 Series Reference Manual 9.3.3.2 Counter Mode ................273 9.3.3.3 Repetition Counter ................ 281 9.3.3.4 Clock Selection ................282 9.3.3.5 Capture/Compare Channel ............. 284 9.3.3.6 Input Capture Mode ..............286 9.3.3.7 PW M Input Mode................287 9.3.3.8 Forced Output Mode ..............288 9.3.3.9...
Page 12 AT32F415 Series Reference Manual 9.3.4.12 TMR1 Auto-reload Register (TMRx_AR).......... 322 9.3.4.13 TMR1 Repetition Counter Register (TMRx_RC) ....... 323 9.3.4.14 TMR1 Capture/Compare Register 1 (TMRx_CC1) ......323 9.3.4.15 TMR1 Capture/Compare Register 2 (TMRx_CC2) ......323 9.3.4.16 TMR1 Capture/Compare Register 3 (TMRx_CC3) ......324 9.3.4.17...
Page 13 AT32F415 Series Reference Manual 11 Real-time Clock (ERTC) ..................338 11.1 Introduction ....................338 11.2 ERTC Main Features ..................338 11.3 ERTC Function Overview ................339 11.3.1 Clock and Prescaler ................339 11.3.2 Real-time Clock and Calendar ..............340 11.3.3 Programmable Clock ................
Page 14 AT32F415 Series Reference Manual 11.6.11 ERTC Sub-second Register (ERTC_SBSR) ..........359 11.6.12 ERTC Shift Control Register (ERTC_SFCTR) .......... 359 11.6.13 ERTC Time Stamp Time Register (ERTC_TSTM) ........360 11.6.14 ERTC Time Stamp Date Register (ERTC_TSDT) ........360 11.6.15 ERTC Time Stamp Sub-second Register (ERTC_TSSBS) ......361 11.6.16 ERTC Calibration Register (ERTC_CCR) ..........
Page 15 AT32F415 Series Reference Manual 12.4.1 ADC Status Register (ADC_STS) ............377 12.4.2 ADC Control Register 1 (ADC_CTRL1) ........... 377 12.4.3 ADC Control Register 2 (ADC_CTRL2) ........... 380 12.4.4 ADC Sample Time Register 1 (ADC_SMPT1) .......... 383 12.4.5 ADC Sample Time Register 2 (ADC_SMPT2) .......... 383 ADC Injected Channel Data Offset Register x (ADC_JOFSx) (x = 1…4) ..
Page 16 AT32F415 Series Reference Manual 13.4.4 Own Address Register 2 (I C_OADDR2) ..........409 13.4.5 Data Register (I C_DT) ................409 13.4.6 Status Register 1 (I C_STS1) ..............409 13.4.7 Status Register 2 (I C_STS2) ..............412 13.4.8 Clock Control Register (I C_CLKCTRL) ..........
Page 17 AT32F415 Series Reference Manual 14.3.8 LIN (Local Interconnection Network) Mode ..........428 14.3.8.1 LIN Transmission ................428 14.3.8.2 LIN Reception ................428 14.3.9 USART Synchronous Mode ..............430 14.3.10 Single-wire Half-duplex Communication ..........432 14.3.11 Smartcard ..................... 433 14.3.12 IrDA SIR ENDEC Block ................435 14.3.13 Continuous Communication Using DMA ..........
Page 18 AT32F415 Series Reference Manual 15.3.1.1 Introduction .................. 451 15.3.1.2 Configure SPI in Slave Mode ............454 15.3.1.3 Configure SPI in Master Mode ............455 15.3.1.4 Configure SPI for Half -duplex Communication ......... 456 15.3.1.5 Data Transmission and Reception ..........456 15.3.1.6...
Page 19 AT32F415 Series Reference Manual 16.1 Introduction ....................490 16.2 Main Features ....................490 16.3 Function Overview ..................490 16.3.1 CAN Overall Function Descr iption ............490 16.3.2 Operating Mode ..................492 16.3.2.1 Initialization Mode ................. 492 16.3.2.2 Normal Mode ................493 16.3.2.3...
Page 20 AT32F415 Series Reference Manual 16.4.3 CAN Mailbox Register ................518 Tx Mailbox Identifier Register (CAN_TMIx) (x = 0…2) ...... 518 16.4.3.1 16.4.3.2 Mailbox Data Length and Time Stamp Register ( CAN_TDTx) (x = 0…2) ....................519 16.4.3.3 Tx Mailbox Data Low Register (CAN_TDLx) (x = 0...2) ..... 520 Tx Mailbox Data High Register (CAN _TDHx) (x = 0…2) ....
Page 21 AT32F415 Series Reference Manual 17.3.2.7 Stream Access, Stream W rite, and Stream Read (MultiMediaCard Only) ................... 542 17.3.2.8 Erase: Group Erase and Sector Erase ..........543 17.3.2.9 W ide Bus Selection or Deselection ..........543 17.3.2.10 Protection Management ..............543 17.3.2.11 Card Status Register ..............
Page 22 AT32F415 Series Reference Manual 17.4.9 SDIO Data Control Register (SDIO_DTCTRL) ......... 566 17.4.10 SDIO Data Counter Register (SDIO_DTCNTR) ........567 17.4.11 SDIO Status Register (SDIO_STS) ............567 17.4.12 SDIO Clear Interrupt Register (SDIO_INTCLR) ........568 17.4.13 SDIO Interrupt Mask Register (SDIO_INTEN) .......... 569 17.4.14 SDIO BUF Counter Register (SDIO_BUFCNTR) ........
Page 23 AT32F415 Series Reference Manual 19.5.2 Comparator Control/Status Register 2 (COMP_CTRLSTS2) ........584 19.5.3 Glitch Filter Enable Register (G_FILTER_EN) ........... 584 19.5.4 Interference Filter High Pulse (HIGH_PULSE) ........... 585 19.5.5 Interference Filter Low Pulse (LOW _PULSE) ..........585 20 HSI Auto Clock Calibration ................586 20.1 ACC Introduction ...................
Page 24 AT32F415 Series Reference Manual 21.6 USB Host Mode ..................... 599 21.6.1 USB Host States ..................600 21.6.2 Host Channel ..................601 21.6.3 Host Scheduler ..................602 21.7 SOF Trigger ....................604 21.7.1 Host SOFs ....................604 21.7.2 Device SOFs ................... 604 21.8 Power Supply Option ..................
Page 25 AT32F415 Series Reference Manual 21.14.14 OTG_FS Core ID Register (OTG_FS_GUID) .......... 635 21.14.15 OTG_FS Host Periodic TX FIFO Size Register (OTG_FS_HPTXFSIZ) ..635 21.14.16 OTG_FS Device IN Endpoint TX FIFO Size Register (OTG_FS_DIEPTXFn) (where n is FIFO number, n = 1...4) ..............636 21.14.17 Host Mode Registers ................
Page 26 AT32F415 Series Reference Manual 21.14.37 OTG_FS Device IN Endpoint FIFO Empty Interrupt Mask Register (OTG_FS_DIEPEMPMSK) .................. 651 21.14.38 OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) ......................652 21.14.39 OTG_FS Device Endpoint x Control Register (OTG_FS_DIEPCTLx)(where x is endpoint number, x = 1...3) ..................653 21.14.40 OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0)
Page 27 AT32F415 Series Reference Manual List of tables Table 1- 1 Register Boundary Address ......................46 Table 1- 2 256KB Flash Memory Module Organization ................. 48 Table 1- 3 128KB Flash Memory Module Organization ................. 49 Table 1- 4 64KB Flash Memory Module Organization ................... 51 Table 1- 5 Boot Mode ............................
Page 28 Table 6- 35 GPIO Register Map and Reset Values ..................141 Table 6- 36 AFIO Register Map and Reset Values ..................142 Table 7- 1 Vector Table of AT32F415 Series ....................158 Table 7- 2 External Interrupt/Event Controller Map and Reset Values ............164 Table 8- 1Programmable Data Transfer Width and Endian Behavior (When PINC = MINC = 1) ....
Page 29 AT32F415 Series Reference Manual Table 8- 5 Summary of Flexible DMA Request for Each Channel .............. 176 Table 8- 6 DMA Register Map and Reset Values ..................177 Table 9- 1 Counting Direction and Encoder Signals ..................207 Table 9- 2 TMRx–Register Table and Reset Values ..................216 Table 9- 3 TMRx internal trigger connection ....................
Page 30 AT32F415 Series Reference Manual Table 14- 5 Frame Format ........................... 428 Table 14- 6 USART Interrupt Request ......................439 (Note) Table 14- 7 USART Mode Configuration ....................440 Table 15- 1 SPI Interrupt Request ....................... 467 Table 15- 2 Audio-frequency Precision Using System Clock ..............476 Table 15- 3 I2S Interrupt Request .......................
Page 31 AT32F415 Series Reference Manual Table 17- 23 Application-specific Command ....................555 Table 17- 24 R1 Response .......................... 555 Table 17- 25 R2 Response .......................... 556 Table 17- 26 R3 Response .......................... 556 Table 17- 27 R4 Response .......................... 556 Table 17- 28 R4b Response ........................557 Table 17- 29 R5 Response ..........................
Page 32 AT32F415 Series Reference Manual List of figures Figure 1- 1 AT32F415 Series Microcontrollers System Architecture ..............42 ® Figure 1- 2 Internal Block Diagram of Cortex -M4 ..................44 Figure 1- 3 AT32F415 Address Configuration ....................45 Figure 2- 1 Block Diagram of Each Power Supply ..................56 Figure 2- 2 Power-on Reset/Power-down Reset Waveform .................
Page 33 AT32F415 Series Reference Manual Figure 9- 7 Counter Timing Diagram with Internal Clock Divided by N ............189 Figure 9- 8 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not Preloaded) ..189 Figure 9- 9 Counter Timing Diagram with Update Event When ARPEN = 1 (TMRx_AR is Preloaded) ... 190 Figure 9- 10 Counter Timing Diagram with Internal Clock Divided by 1 .............
Page 34 AT32F415 Series Reference Manual Figure 9- 40 Control Circuit in External Clock Mode 2 + Trigger Mode ............211 Figure 9- 41 Master/Slave Timer Example ....................211 Figure 9- 42 Timer 1 OC1REF Controls Timer 2 ..................212 Figure 9- 43 Control Timer 2 by Enabling Timer 1 ..................213 Figure 9- 44 Using Timer 1 Update to Trigger Timer 2 ................
Page 35 AT32F415 Series Reference Manual Figure 9- 72 Counter Timing Diagram with Prescaler Division Changing from 1 to 4 ......... 272 Figure 9- 73 Counter Timing Diagram with Internal Clock Divided by 1 ............. 273 Figure 9- 74 Counter Timing Diagram with Internal Clock Divided by 2 ............. 274 Figure 9- 75 Counter Timing Diagram with Internal Clock Divided by 4 .............
Page 36 AT32F415 Series Reference Manual Figure 9- 104 Complementary Output with Dead-time Insertion ..............292 Figure 9- 105 Dead-time Waveform Delay Which is Greater than Negative Pulse ........292 Figure 9- 106 Dead-time Waveform Delay Which is Greater than Positive Pulse ........293 Figure 9- 107 Outputs in Response to a Break ...................
Page 37 AT32F415 Series Reference Manual Figure 13- 7 Transfer Sequence Diagram for Master Receiver when N > 2 ..........396 Figure 13- 8 Transfer Sequence Diagram for Master Receiver when N = 2 ..........397 Figure 13- 9 Transfer Sequence Diagram for Master Receiver when N = 1 ..........398 Figure 13- 10 I2C Interrupt Mapping Diagram ....................
Page 38 AT32F415 Series Reference Manual Figure 15- 5 TE/RNE/BSY Behavior during Continuous Output in Master/Full-duplex Mode (BDMODE = 0 and RONLY = 0) ......................458 Figure 15- 6 TE/RNE/BSY Behavior during Continuous Transfer in Slave/Full-duplex Mode (BDMODE = 0 and RONLY = 0) ......................459 Figure 15- 7 TE/BSY Behavior during Continuous Transfer in Master Transmit-only Mode (BDMODE = 0 and RONLY = 0) ......................
Page 39 AT32F415 Series Reference Manual Figure 15- 32 I2S Clock Generator Architecture ..................475 Figure 16- 1 CAN Network Topology ......................491 Figure 16- 2 CAN Block Diagram ........................ 492 Figure 16- 3 bxCAN Operating Mode ......................493 Figure 16- 4 bxCAN in Silent Mode ......................494 Figure 16- 5 bxCAN in Loopback Mode ......................
Page 40 AT32F415 Series Reference Manual Figure 19- 2 Comparator Hysteresis ......................579 Figure 19- 3 Interference Filter Timing Sequence Diagram when H_PULSE_CNT = 1 and L_PULSE_CNT = 0 ..........................580 Figure 19- 4 Interference Filter Timing Sequence Diagram when H_PULSE_CNT = 2 and L_PULSE_CNT = 1 ..........................
Page 41: System Architecture
AT32F415 Series Reference Manual 1 System Architecture ® ® AT32F415 series microcontrollers consist of ARM Cortex -M4 processor core, bus architecture, ® peripherals, and memory. Cortex -M4 processer is a stage-of-the-art core, featuring many advanced ® ® functions. Compared with Cortex...
Page 42: Figure 1- 1 At32F415 Series Microcontrollers System Architecture
AT32F415 Series Reference Manual Figure 1- 1 AT32F415 Series Microcontrollers System Architecture HSE 4~25 MHz SWJTAG HSI 48 MHz Fmax 150 MHz SDIO Cortex-M4 (Fmax 150 MHz) FCLK HCLK PCLK1 NVIC PCLK2 DMA1 Flash Flash 7 channel controller POR/PDR DMA2...
Page 43: Bus Architecture
AT32F415 Series Reference Manual 1.1.1 Bus Architecture I-Code bus ● This bus connects the Instruction bus of the Cortex ® -M4 core to the Flash memory instruction interface. Prefetching is performed on this bus. D-Code bus ● This bus connects the D-Code bus (literal load and debug access) of the ®...
Page 44: Address Map
AT32F415 Series Reference Manual ® Figure 1- 2. Internal Block Diagram of Cortex Cortex-M4 Interrupts and Cortex-M4 Power control NVIC Core SW-DP or AHB-AP Bus Matrix TPIU SWJ-DP SW/JTAG ROM Table 1.2 Address Map Program memory, data memory, registers, and I/O ports are organized within the same linear 4-GB address space.
Page 45: Figure 1- 3 At32F415 Address Configuration
AT32F415 Series Reference Manual Figure 1- 3 AT32F415 Address Configuration 0xFFFF_FFFF Cortex-M4 Internal peripherals 0xE000_0000 0xDFFF_FFFF 0x5FFF_FFFF Reserved 0x4247_0000 0x4246_FFFF Peripheral bit binding mapping area 0x4200_0000 0x41FF_FFFF Reserved 0x4002_3800 0x4002_37FF Peripherals 0x4000_0000 Reserved 0x3FFF_FFFF Reserved 0x2210_0000 0x220F_FFFF SRAM bit binding...
Page 46: Register Map
AT32F415 Series Reference Manual 1.2.1 Register Map Please refer to the diagram of memory map listed in the corresponding data sheet of the user device. Table 1-1 lists all the peripheral boundary addresses in AT32F415. Table 1- 1 Register Boundary Address...
Page 47: Bit Banding
In the AT32F415 series, both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed.
Page 48: On-Chip Sram
1.2.4 On-chip Flash AT32F415 series provide up to 256 KB of on-chip Flash memory, supporting zero wait state single cycle 32-bit read operation. The Flash memory is divided into main memory block and information block. The main memory block is used for storing application code; it can be accessed by bytes (8-bit aligned), half-words (16-bit aligned), or full words (32-bit aligned).
Page 49: Table 1- 3 128Kb Flash Memory Module Organization
AT32F415 Series Reference Manual 0x4002 2010 – 0x4002 2013 FLASH_CTRL 0x4002 2014 – 0x4002 2017 FLASH_ADDR 0x4002 2018 – 0x4002 201B Reserved 0x4002 201C – 0x4002 201F FLASH_UOB 0x4002 2020 – 0x4002 2023 FLASH_WRPRT Reserved 0x4002 2024 - 0x4002 2073...
Page 50 AT32F415 Series Reference Manual FLASH_CRC_AR 0x4002 2084 - 0x4002 2087 FLASH_CRC_CTRL 0x4002 2088 - 0x4002 208B FLASH_CRC_OUTR 0x4002 208C - 0x4002 208F Reserved 0x4002 2090 - 0x4002 215F FSLIB_SET_PSW 0x4002 2160 - 0x4002 2163 FSLIB_SET_RANGE 0x4002 2164 - 0x4002 2167...
Page 51: Boot Configuration
AT32F415 Series Reference Manual Table 1- 4 64KB Flash Memory Module Organization Block Name Address Range Size (bytes) 0x0800 0000 – 0x0800 03FF Page0 0x0800 0400 – 0x0800 07FF Page1 0x0800 0800 – 0x0800 0BFF Page2 Main 0x0800 0C00 – 0x0800 0FFF...
Page 52 -M4 CPU always fetches the reset vector on the I-Code bus, which implies that boot space is available only in the code area (typically, Flash memory). AT32F415 series microcontrollers implement a special mechanism which enables booting from on- chip SRAM. When booting from on-chip SRAM, in the application initialization code, NVIC exception table and offset register must be used to relocate the vector table in SRAM.
Page 53: Device Characteristics Information
AT32F415 Series Reference Manual 1.4 Device Characteristics Information 1.4.1 Description of Register Abbreviations The following abbreviations are used in the register descriptions of this manual: Table 1- 6 List of for Register Abbreviations Software can read and write to these bits.
Page 54 AT32F415 Series Reference Manual Base address: 0x1FFF F7EC Reset value: 0xXXXX XXXX (Factory-programmed) UID[63:48] UID[47:32] Base address: 0x1FFF F7F0 Reset value: 0xXXXX XXXX (Factory-programmed) UID[95:80] UID[79:64] Note: UID[95:88] is the Series ID, which is 0x05 2020.06.28 Page 54 Version 1.02...
Page 55: Power Control (Pwr)
2 Power Control (PWR) 2.1 Introduction Power consumption is one of the most important issue in AT32F415 series devices. The operating voltage supply is 2.6 V ~ 3.6 V, and it can function normally within -40℃ ~ +85℃. To reduce power...
Page 56: Vdd/Vdda Power Domain
AT32F415 Series Reference Manual Figure 2- 1 Block Diagram of Each Power Supply VDDA domain REF- A/D converter (From 2.4 V up to V REF+ Temp. sensor reset block VDD domain 1.2 V domain I/O Ring CPU core Standby circuitry memories （Wakeup logic IWDG）...
Page 57: Figure 2- 2 Power-On Reset/Power-Down Reset Waveform
AT32F415 Series Reference Manual Figure 2- 2 Power-on Reset/Power-down Reset W aveform 180 mV hysteresis Temporization RESTTEMPO Reset AT32F415 provides a programmable voltage detector (PVD). Users can use this PVD to monitor VDD power supply by comparing it to the PVDS[2:0] bits in the power control register (PWR_CTRL), selecting the threshold for voltage monitor.
Page 58: Core Power Domain
AT32F415 Series Reference Manual 2.3.1.2 Core Power Domain Core power domain includes CPU core, memory, and embedded digital peripherals. This power domain is supplied by a voltage regulator. The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes.
Page 59: Sleep Mode
AT32F415 Series Reference Manual ON or in Any EXTI line low-power mode PDDS bit (configured in (depends on the Stop + SLEEPDEEP bit the EXTI power control + WFI or WFE registers) register (PWR_CTRL)) HSI and HSE All 1.2 V domain oscillators are clocks are OFF.
Page 60: Stop Mode
AT32F415 Series Reference Manual The wakeup time required by this mode is the shortest, since there is no time wasted in interrupt entry/exit. Please refer to Table 2-1 Table 2-2 for more details on how to exit Sleep mode. Table 2- 1 SLP-NOW Mode...
Page 61: Standby Mode
AT32F415 Series Reference Manual Table 2- 3 Stop Mode Stop mode Description Execute WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex ® -M4 system control register. – Clear PDDS bit in power control register (PWR_CTRL).
Page 62: Debug Mode
AT32F415 Series Reference Manual Table 2- 4 Standby Mode Standby Mode Description Execute WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex ® -M4 system control register Entry – Set PDDS bit in power control register (PWR_CTRL) –...
Page 63: Pwr Registers
AT32F415 Series Reference Manual 2.4 PWR Registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Offset Register PWR_CTRL 0x00 Reserved Reset Value 0 0 0 0 0 0 0 0 0 PWR_CTRL 0x04 Reserved Reserved Reset Value 0 0 0 2.4.1...
Page 64: Power Control/Status Register (Pwr_Ctrlsts)
AT32F415 Series Reference Manual PDDS: Power down deep-sleep Bit 1 0: Enter Stop mode when the CPU enters Deep-sleep. 1: Enter Standby mode when the CPU enters Deep-sleep. LPDS: Low power deep-sleep Bit 0 0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode in Stop mode 2.4.2...
Page 65: Reset And Clock Control (Rcc)
AT32F415 Series Reference Manual 3 Reset and Clock Control (RCC) 3.1 Reset AT32F415 provides three types of reset, including system reset, power-on reset, and backup domain reset. 3.1.1 System Reset Except for the reset flags in the RCC_CTRLSTS register of clock controller and the registers in the...
Page 66: Backup Domain Reset
AT32F415 Series Reference Manual Figure 3- 1 Reset Circuit DD V DDA External Reset System Filter reset NRST WWDG reset Pulse IWDG reset generator Power reset (Min 20 µs) Software reset Low-power management reset 3.1.3 Backup Domain Reset The backup domain has two specific resets that affect only the backup domain (See Figure 2-1).
Page 67: Figure 3- 2 Clock Tree
AT32F415 Series Reference Manual Figure 3- 2 Clock Tree HSI_FOR_USB HSI_DIV_EN USB_DP USB_DM 48 MHz USBOTGCLK USB OTG To USB OTG interface precaler HSI RC /1,1.5,2,2.5 I2S[1,2]CLK 48 MHz I2S[1,2] Peripheral clock enable HSISYSCTRL SDIOCLK Peripheral clock SDIO enable Max 150MHz...
Page 68: Hse Clock
AT32F415 Series Reference Manual of the APB domain to which the timers are connected. 2. Otherwise, they are set to double (×2) the frequency of the APB domain to which the timers are connected. ® ® FCLK acts as Cortex -M4’s free-running clock.
Page 69: Hsi Clock
AT32F415 Series Reference Manual Relevant hardware configuration is shown in Figure 3-3. Please refer to the electrical characteristics section of the data sheet for more details. The HSESTBL bit in the clock control register (RCC_CTRL) indicates if the high-speed external oscillator is stable.
Page 70: Lse Clock
AT32F415 Series Reference Manual PLL PLL clock calculation formula = PLL input clock x PLL PLL clock calculation formula / (PLL c x PLL postscaler factor) 500MHz <= PLL input clock x PLL multiplication factor /PLL multiplication factor <= 1000MHz 2MHz <= PLL input clock / PLL postscaler factor <= 16MHz...
Page 71: System Clock (Sysclk) Selection
AT32F415 Series Reference Manual 3. Measure the frequency of LSI clock with the TIMR5 capture/compare 4 event or interrupt. 4. Configure the 20-bit prescaler according to the measured and desired ERTC time base and IWDG timeout. 3.2.6 System Clock (SYSCLK) Selection After a system reset, the HSI oscillator is selected as system clock.
Page 72: Clock-Out Capability
AT32F415 Series Reference Manual 3.2.10 Clock-out Capability The microcontroller allows the clock to be output onto the external CLKOUT pin. The corresponding GPIO port register must be programmed as the corresponding function mode. The following 9 clock signals can be selected as CLKOUT clock: ●...
Page 73 AT32F415 Series Reference Manual Reset Value RCC_AH 014h Reserved Reset Value RCC_AP B2EN 018h Reset Value RCC_AP B1EN 01Ch Reset Value RCC_BD 020h Reserved Reserved Reserved Reset Value RCC_ 024h Reserved CTRLSTS RCC_AH BRSTR 028h Reserved Reserved Reset Value RCC_PLL...
Page 74: Clock Control Register (Rcc_Ctrl)
AT32F415 Series Reference Manual RCC_OT G_EXTC 044h Reserved Reset Value RCC_MIS 054h Reset Value 3.3.1 Clock Control Register (RCC_CTRL) Address offset: 0x00 Reset value: 0x000 XX83, where X is undefined Access: No wait state. Word, half-word, and byte access. Reserved...
Page 75 AT32F415 Series Reference Manual HSEEN: External high-speed clock enable Set and cleared by software. When entering Stop or Standby mode, this bit is cleared by hardware, and the 4 ~ 16 MHz Bit16 oscillator is disabled. When external 4 ~ 16 MHz oscillator is used as or selected to become system clock, this bit cannot be cleared.
Page 76: Clock Configuration Register (Rcc_Cfg)
AT32F415 Series Reference Manual 3.3.2 Clock Configuration Register (RCC_CFG) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 to 2 wait state. Word, half-word, and byte access. 1 or 2 wait states are inserted only when the access occurs during a clock source switch.
Page 77 AT32F415 Series Reference Manual PLLSRC: PLL entry clock source Set and cleared by software to select PLL input clock source. This bit can be written only Bit 16 when PLL is disabled. 0: HSI oscillator clock divided by 2 to be PLL input clock.
Page 78: Clock Interrupt Register (Rcc_Clkint)
AT32F415 Series Reference Manual 3.3.3 Clock Interrupt Register (RCC_CLKINT) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait state. Word, half-word, and byte access. PLLST HSES HSIS LSES LSIS Reserve CFDF Reserved TBLF BLFC BLFC BLFC PLLS HSES HSIS...
Page 79 AT32F415 Series Reference Manual HSISTBLIE: HSI ready interrupt enable Set and cleared by software to enable/disable internal 8 MHz RC oscillator ready interrupt Bit 10 0: HSI ready interrupt is disabled. 1: HSI ready interrupt is enabled. LSESTBLIE: LSE ready interrupt enable...
Page 80: Apb2 Peripheral Reset Register (Rcc_Apb2Rst)
AT32F415 Series Reference Manual 3.3.4 APB2 Peripheral Reset Register (RCC_APB2RST) Address offset: 0x0C Reset value: 0x0000 0000 Access: No wait state. Word, half-word, and byte access. TMR11 TMR10 TMR9 Reserved Reserved USAR SPI1 TMR1 ADC1 GPIOF GPIOD GPIOC GPIOB GPIOA AFIO Res.
Page 81: Apb1 Peripheral Reset Register (Rcc_Apb1Rst)
AT32F415 Series Reference Manual GPIOFRST: IO port F reset Set and cleared by software. Bit 7 0: No effect 1: Reset IO port F Bit 6 Reserved. Always set to 0. GPIODRST: IO port D reset Set and cleared by software.
Page 82 AT32F415 Series Reference Manual CANRST: CCAN reset Set and cleared by software. Bit 25 0: No effect 1: Reset CAN Bit 24:23 Reserved. Always read as 0. I2C2RST: I2C 2 reset Set and cleared by software. Bit 22 0: No effect...
Page 83 AT32F415 Series Reference Manual TMR4RST: Timer 4 reset Set and cleared by software. Bit 2 0: No effect 1: Reset TMR 4 timer TMR3RST: Timer 3 reset Set and cleared by software. Bit 1 0: No effect 1: Reset TMR 3 timer TMR2RST: Timer 2 reset Set and cleared by software.
Page 84: Ahb Peripheral Clock Enable Register (Rcc_Ahben)
AT32F415 Series Reference Manual 3.3.6 AHB Peripheral Clock Enable Register (RCC_AHBEN) Address offset: 0x14 Reset value: 0x0000 0014 Access: No wait state. Word, half-word, and byte access. Note: If peripheral clock is not enabled, the software will not be able to read the value of peripheral register, and the returned value is always 0x0.
Page 85 AT32F415 Series Reference Manual Reset value: 0x0000 0000 Access: Word, half-word, and byte access. Usually no waiting state, but if peripherals on APB2 bus are accessed, waiting states will be inserted until the end of APB2 peripheral access. Note: If peripheral clock is not enabled, the software will not be able to read the value of peripheral register, and the returned value is always 0x0.
Page 86: Apb1 Peripheral Clock Enable Register (Rcc_Apb1En)
AT32F415 Series Reference Manual GPIOFEN: I/O port F clock enable Set and cleared by software. Bit 7 0: IO port F clock is disabled. 1: IO port F clock is enabled. Bit 6 Reserved. Always read as 0. GPIODEN: I/O port D clock enable Set and cleared by software.
Page 87 AT32F415 Series Reference Manual CANEN: CAN clock enable Set and cleared by software. Bit 25 0: CAN clock is disabled. 1: CAN clock is enabled. Bit 24:26 Reserved. Always read as 0. I2C2EN: I2C 2 clock enable Set and cleared by software.
Page 88: Backup Domain Control Register (Rcc_Bdc)
AT32F415 Series Reference Manual TMR3EN: Timer 3 clock enable Set and cleared by software. Bit 1 0: Timer 3 clock is disabled. 1: Timer 3 clock is enabled. TMR2EN: Timer 2 clock enable Set and cleared by software. Bit 0 0: Timer 2 clock is disabled.
Page 89: Control/Status Register (Rcc_Ctrlsts)
AT32F415 Series Reference Manual LSESTBL: External low-speed oscillator ready Set and cleared by hardware to indicate if external 32 kHz oscillator is stable. After the Bit 1 LSEEN bit is cleared, this bit is cleared after 6 external low-speed oscillator clock cycles.
Page 90: Ahb Peripheral Reset Register (Rcc_Ahbrst)
AT32F415 Series Reference Manual RSTFC: Reset flag clear Set by software to clear the reset flags. Bit 24 0: No effect 1: Clear the reset flags. Bit 23:2 Reserved. Return 0 after being read. LSISTBL: Internal low-speed oscillator ready Set and cleared by hardware to indicate if the internal 40 kHz RC oscillator is stable. After the Bit 1 LSIEN bit is cleared, LSISTBL is cleared after 3 internal 40 kHz RC oscillator clock cycles.
Page 91: Additional Register (Rcc_Misc)
AT32F415 Series Reference Manual PLL_FREF: PLL Configuration Table Configured by software to determine which PLL reference clock table is used. 000: PLL uses 4M reference clock table. 001: PLL uses 6M reference clock table. 010: PLL uses 8M reference clock table.
Page 92: Otg_Fs Extension Control Register (Rcc_Otg_Extctrl)
AT32F415 Series Reference Manual 3.3.14 OTG_FS Extension Control Register (RCC_OTG_EXTCTRL) Address offset: 0x44 Reset value: 0x0000 0000 This register must be configured before enabling the OTG_FS peripherals. EP3_RMPEN USBDIV_RST Reserved Reserved EPS_RMPEN: Endpoint3 remap enable Set or cleared by software.
Page 93: Additional Register (Rcc_Misc2)
AT32F415 Series Reference Manual 3.3.15 Additional Register (RCC_MISC2) Address offset: 0x54 Reset value: 0x0000 000D Reserved HSI_ HSI_ AUTO_ Reserved SYS_ FOR_ Reserved STEP_ Reserved CTRL Bit 31:10 Reserved. Return 0 after being read. HSI_SYS_CTRL: HSI as system clock frequency select...
Page 94: Embedded Flash Controller (Efc)
AT32F415 Series Reference Manual 4 Embedded Flash Controller (EFC) 4.1 EFC Introduction Embedded Flash memory can be used for In-Circuit Programming (ICP) or In-Application Programming (IAP). In-Circuit Programming (ICP) is used to update all the contents in the Flash memory. It can download user application to the microcontroller through JTAG, SWD protocol, or boot loader.
Page 95: Table 4- 2 128 Kb Flash Memory Architecture
AT32F415 Series Reference Manual 0x4002 2000 – 0x4002 2003 FLASH_ACR 0x4002 2004 – 0x4002 2007 FLASH_FCKEY 0x4002 2008 – 0x4002 200B FLASH_OPTKEYR 0x4002 200C – 0x4002 200F FLASH_STS 0x4002 2010 – 0x4002 2013 FLASH_CTRL 0x4002 2014 – 0x4002 2017 FLASH_ADDR 0x4002 2018 –...
Page 96: Table 4- 3 64 Kb Flash Memory Architecture
AT32F415 Series Reference Manual FLASH_CDR1 0x4002 2078 - 0x4002 207B FSLIB_PSW 0x4002 207C - 0x4002 207F FSLIB_PSW_STS 0x4002 2080 - 0x4002 2083 FLASH_CRC_AR 0x4002 2084 - 0x4002 2087 FLASH_CRC_CTRL 0x4002 2088 - 0x4002 208B FLASH_CRC_OUTR 0x4002 208C - 0x4002 208F...
Page 97: Function Overview
Information block is divided into two parts: ● System memory is used for boot loader store d in the system memory bootstrapping mode. This area is reserved only for Artery, and the boot loader uses USART1; USART2 or OTG FS device mode (DFU) performs programming to the Flash memory;...
Page 98: D-Code Interface
AT32F415 Series Reference Manual 4.3.1.2 D-Code Interface D-Code interface includes simple AHB interface on CPU and logic circuit that requests access to the arbiter of Flash access controller. Access to D-code has higher priority than access to prefetch instruction. This interface uses access time regulator block of prefetch buffer.
Page 99: Flash Erase
AT32F415 Series Reference Manual Figure 4- 1 Process of the Programming Read the LOCK bit in FLASH_CR Execute Unlock LOCK bit = 1 Sequence Set the PRGM bit = 1 in FLASH_CR Write word (or half-word, or byte) to the designated address...
Page 100: Figure 4- 2 Process Of Flash Memory
AT32F415 Series Reference Manual  Set the PGERS bit in the FLASH_CTRLx register;  Select the page to be erased with the FLASH_ADDRx register;  Set the RSTR bit in the FLASH_CTRLx register;  Wait until the BSY bit becomes ‘0’;...
Page 101: Option Byte Programming
AT32F415 Series Reference Manual Figure 4- 3 Process of Flash Memory Mass Erase Read the LOCK bit in FLASH_CR Execute Unlock LOCK bit = 1 Process Set MER = 1 in FLASH_CR; Set STRT = 1 in FLASH_CR BSY bit = 1 in FLASH_SR...
Page 102: Protection
AT32F415 Series Reference Manual Process of erase The erase operation (OPTERASE) of option bytes is in the following order:  Check the BSY bit in the FLASH_STS register to confirm that there is no other programming operation in process; ...
Page 103: Table 4- 5 Read Protection Level Switch Description
AT32F415 Series Reference Manual Any value Opposite of non-RDP byte Protected Figure 4- 4 Read Protection Level Switch Status Diagram Option byte non-RDP bit change Level 1 (low-level protection) RDP is not 0x00A5. RDP is 0x00CC. (Default value) Erase option byte Erase option byte;...
Page 104: Option Byte Block Write Protection
AT32F415 Series Reference Manual  Reset (any reset) and reload option bytes (and new RDP code). Read protection will be disabled at this time. Note: Boot loader can also be used to disable the read protection (In this case, o ption bytes can be reloaded just by system reset).
Page 105: Special Functions
AT32F415 Series Reference Manual Data3: user data 3 Data2: user data2 Data1: user data1 (stored in the register FLASH_UOB[25:18]) Data0: user data0 (stored in the register FLASH_UOB[17:10]) WRPRTBMPx: Flash memory write protection option byte Every bit in the WRPRTBMPx option byte is used to protect the two memory pages (64K, 128L, 1Kbyte/page;...
Page 106: System Memory For Main Memory Extension Purpose
AT32F415 Series Reference Manual register to see if it is unlocked successfully . Afterwards, it is allowed to write values into the security library configuration register. Steps to enable main memory security library are as follows ● Check the BSY bit in the FLASH_STS register to ensure that there is no other ongoing programming operation;...
Page 107: Crc Calibration
AT32F415 Series Reference Manual 4.3.5.3 CRC Calibration Start selectable CRC calibration to security library code or HEX encryption user code by page. The calibration process is as follows: ● Check the BSY bit in the FLASH_STS register to ensure that there is no other ongoing programming operations;...
Page 108: Efc Registers
AT32F415 Series Reference Manual 4.4 EFC Registers Table 4- 9 Flash Memory Interface— Register Map and Reset Values Offset Register FLASH_ 0x00 Reserved Reset Value FLASH_ KEY[31：0] FCKEY 0x04 Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x FLASH_ OPTKEYR[31：0]...
Page 109: Flash Access Control Register (Flash_Acr)
AT32F415 Series Reference Manual Reset Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FSLIB FSLIB_PSW[31：0] _PSW 0x7C Reset Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...
Page 110: Fpec Key Register (Flash_Fckey)
AT32F415 Series Reference Manual Reserved. Must be kept at reset value ‘0’. Bit 31:6 PRFTBS: Prefetch buffer status This bit indicates the status of prefetch buffer. Bit 5 0: Prefetch buffer is OFF; 1: Prefetch buffer is ON. PRFTBE: Prefetch buffer enable Bit 4 0: Prefetch buffer is disabled;...
Page 111: Flash Status Register (Flash
AT32F415 Series Reference Manual OPTKEYR: Option bytes key Bit 31:0 These bits are used for option bytes key to unlock UOBWE. 4.4.4 Flash Status Register (FLASH_STS) Only used in Flash memory Bank 1. Address offset: 0x0C Reset value: 0x0000 0000...
Page 112: Flash Control Register (Flash_Ctrl)
AT32F415 Series Reference Manual 4.4.5 Flash Control Register (FLASH_CTRL) Only used in Main Flash memory Bank and user option byte Address offset: 0x10 Reset value: 0x0000 0080 RDPL Reserved _DIS Reserv Reserv Reserve Reserved DNIE Reserved. Must be kept at reset value ‘0’.
Page 113: Flash Address Register (Flash_Addr)
AT32F415 Series Reference Manual 4.4.6 Flash Address Register (FLASH_ADDR) Only used in Main Flash memory Bank. Address offset: 0x14 Reset value: 0x0000 0000 TA[31:16] TA[15:0] These bits are modified by hardware as the current/last address being used. In page erase operation, this register must be modified by software to select the pages to be erased.
Page 114: Write Protection Register (Flash_Wrprt)
AT32F415 Series Reference Manual 4.4.8 Write Protection Register (FLASH_WRPRT) Address offset: 0x20 Reset value: 0xFFFF FFFF WRPRTBMP [31:16] WRPRTBMP [15:0] WRPRTBMP: Write protection This register includes write protection option bytes loaded with OBL. Bit 31:0 0: Write protection is enabled.
Page 115: Flash Slib Status Register 1 (Flash_Cdr1)
AT32F415 Series Reference Manual SYS_MEM_SLIB_EN: main memory extension area for storing security library code enable When this bit is set, it indicates that the main memory extension area is used as security Bit 2 library code. 0: Store security library code function disabled...
Page 116 AT32F415 Series Reference Manual BLK_SLIB_ST_PG: Main memory security library start page 0: Page 0 1: Page 1 2: Page 2 Bit 10:0 … 63: Page 63 For 32 KB Flash memory, the valid pages are from page 0 to page 31;...
Page 117: Flash Slib Password Register (Fsli B_Psw )
AT32F415 Series Reference Manual 4.4.11 Flash sLib Password Register (FSLIB_PSW) Only used in Flash memory security library area Address offset: 0x7C Reset value: 0xFFFF FFFF FSLIB_PSW[31：16] FSLIB_PSW[15：0] FSLIB_PSW: Security library area password register Bit 31:0 Set the correct password to disable the security library function.
Page 118: Flash Crc Verify Start Position (Flash_Crc_Ar)
AT32F415 Series Reference Manual 4.4.13 Flash CRC Verify Start Position (FLASH_CRC_AR) Only used in Flash memory and main memory extension area. Address offset: 0x84 Reset value: 0x0000 0000 FCRC_AR31:16] FCRC_AR[15:0] Note: All bits are write-only, and will return 0 after being read.
Page 119: Flash Crc Verify Result Register (Flash_Crc_Outr)
AT32F415 Series Reference Manual 4.4.15 Flash CRC Verify Result Register (FLASH_CRC_OUTR) Only used in Flash memory and main memory extension area. Address offset: 0x8C Reset value: 0x0000 0000 FCRC_OUT[31：16] FCRC_OUT[15：0] Note: All these bits are read-only, and do not respond to write.
Page 120: Main Memory Extension Area Slib Setting Register
AT32F415 Series Reference Manual 4.4.18 Main memory Extension Area sLib Setting Register (SYS_MEM_SLIB_SET） Only used in security library area. Address offset: 0x168 Reset value: 0x0000 0000 Reserved SYS_MEM_SET_DATA_START_PAGE[23:16] SYS_MEM_AS_SLIB Note: These bits are write-only, and returns 0 when read. Reserved Bit 31:0 SYS_MEM_SET_DATA_START_PAGE: the start page of data sLib area.
Page 121: Flash Slib Key Register (Fslib_Keyr)
AT32F415 Series Reference Manual 4.4.20 Flash sLib key Register (FSLIB_KEYR) Only used in security library area. Address offset: 0x170 Reset value: 0x0000 0000 FSLIB_KEYR[31：16] FSLIB_KEYR[15：0] Note: All these bits are write-only and return 0 when it is read. FSLIB_KEYR: Security library key Bit 31~0 These bits are used for entering the unlock key of security library area.
Page 122: Crc Calculation Unit (Crc)
AT32F415 Series Reference Manual CRC Calculation Unit (CRC) 5.1 CRC Introduction The Periodic Redundancy Check (CRC) calculation unit is used to calculate a 32-bit CRC code based on a fixed generator polynomial. In other applications, CRC-based techniques are applied to verify the correctness and integrity of data transmission or data storage.
Page 123: Crc Function Overview
AT32F415 Series Reference Manual 5.3 CRC Function Overview CRC calculation unit includes one 32-bit data register: ● When being written, this register is used as input register, and can receive new data to be calculated with CRC. ● When being read, it returns the last CRC calculation result. Every write operation into the data register creates a combination of the last CRC calculation result and the new one (CRC calculation is done to the whole 32-bit word, instead of byte by byte).
Page 124: Crc Registers
AT32F415 Series Reference Manual 5.4 CRC Registers CRC calculation unit includes two data registers and one control register. Table 5-1 lists CRC register map and reset values. Table 5- 1 CRC Calculation Unit Register Map Offset Register 31~24 23~16 15~8...
Page 125: Control Register (Crc_Ctrl)
AT32F415 Series Reference Manual 5.4.3 Control Register (CRC_CTRL) Address offset: 0x08 Reset value: 0x0000 0000 Reserved Reserved 保留 REV_OUT REV_IN[1:0] RESET Bit 31:8 Reserved REV_OUT: Reverse output data This bit is used to control whether to reverse the output data.
Page 126: Crc Initial Value (Crc_Init)
AT32F415 Series Reference Manual 5.4.4 CRC Initial Value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31：16] CRC_INIT[15：0] CRC_INIT:CRC initial value This register is used to write the CRC intial value. Bit 31: 0 Note: The value in this register can be refreshed to the CRC_DR register by setting the RESET bit in the CRC_CTRL register.
Page 127: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
AT32F415 Series Reference Manual 6 General-purpose and Alternate-function I/Os (GPIOs and AFIOs) 6.1 Introduction GPIO interface includes 5 sets of general-purpose I/O ports. Each GPIO set provides 16 general-purpose I/O pins. Each GPIO port has relevant control and configuration registers to fulfill specific functions. External interrupts on the GPIO pins also have relevant control and configuration registers in external interrupt controller.
Page 128: Figure 6- 1 Basic Structure Of An I/O Port Bit
AT32F415 Series Reference Manual Figure 6-1 shows a basic structure of an I/O port bit. Figure 6- 1 Basic Structure of an I/O Port Bit Analog Input Pull-up To on-chip switch peripheral Alternate Function Input Input Switch Read V DD...
Page 129: External Interrupt/Wakeup Lines
AT32F415 Series Reference Manual Table 6- 1 Port Bit Assignment PxOPTDT Configuration Mode CONF1 CONF0 MDE1 MDE0 Register Push-Pull 0 or 1 General-purpose Output Open-Drain 0 or 1 Push-Pull Unused Alternate Function See table 6-2 Output Open-Drain Unused Analog Unused...
Page 130: Analog Input Configuration
AT32F415 Series Reference Manual clock cycle.  Read access to input data register can obtain I/O stat es. Figure 6-3 shows the input configuration of the I/O port bit. Figure 6- 3 Input Floating/Pull-up/Pull-down Configuration Pull-up switch Input ON Read...
Page 131: Output Configuration
AT32F415 Series Reference Manual Figure 6- 4 High Impedance Analog Input Configuration To on-chip Analog Input peripheral Input OFF Read V DD or (Note) DD_FT TTL Schmitt trigger Protection diode Input driver I/O pin Write Protection Output driver diode V SS...
Page 132: Gpio Locking Mechanism
AT32F415 Series Reference Manual Figure 6- 5 Output Configuration Input ON Read V DD or V DD_FT (Note) Protection Write diode Input driver I/O pin Protection Output driver V DD diode P-MOS V SS Output control Read/Write N-MOS V SS...
Page 133: Figure 6- 6 Alternate Function Configuration
AT32F415 Series Reference Manual  Weak pull-up and pull-down resistors are disabled.  If pins are configured as multiple -function output, please refer to the data sheet for the priority of each alternate function.  Data present on the I/O pin is sampled into the in put data register every APB2 clock cycle.
Page 134: Table 6- 3 Advanced Timers Tmr1/8/15
AT32F415 Series Reference Manual Table 6- 3 Advanced Timers TMR1/8/15 TMR1 Pin Configuration GPIO Configuration Input capture channel x Input floating TMR1_CHx Output compare channel x Alternate function push-pull TMR1_CHxN Complementary output channel x Alternate function push-pull TMR1_BKIN Break input...
Page 135: Table 6- 7 I2S
AT32F415 Series Reference Manual Table 6- 7 I S Pin Configuration GPIO Configuration Master Alternate function push-pull I2Sx_WS Slave Input floating Master Alternate function push-pull I2Sx_CK Slave Input floating Transmitter Alternate function push-pull I2Sx_SD Input floating/Input pull-up Receiver /Input pull-down...
Page 136: Io Mapping Function Configuration
AT32F415 Series Reference Manual Table 6- 13 Other I/O Functions Alternate Function GPIO Configuration RTC output Forced by hardware when configuring the TAMPER-RTC BRKP_CTRL and BRKP_RTCCAL r e g i s t e r s . Tamper event input CLKOUT...
Page 137: Adc Alternate Function Remapping
AT32F415 Series Reference Manual JTDI PA15 JTDO/TRACESWO JNTRST TRACECK TRACED0 TRACED1 TRACED2 TRACED3 To use more GPIOs during debugging, configuring the SWJTAG_CONF[2:0] bits in the AF remap and debug I/O configuration register (AFIO_MAP) can modify the above-mentioned remapping configuration. Table 6- 16 Debug Port Mapping...
Page 138: Timer Alternate Function Remapping
AT32F415 Series Reference Manual 6.4.6 Timer Alternate Function Remapping Remapping of other timers are listed in Table 6-18 ~ 19. Please refer to the AF remap and debug I/O configuration register (AFIO_MAP). Table 6- 19 TMR11 Alternate Function Remapping Alternate Function Mapping...
Page 139: Usart Alternate Function Remapping
AT32F415 Series Reference Manual Note: TMR2_CH1 and TMR2_ETR share the same pin, but they cannot be used at the same time (so use this mark here: TMR2_CH1_ETR ) Table 6- 25 TMR1 Alternate Function Remapping TMR1_REMAP[1:0] = 11 Alternate Function...
Page 140: C Alternate Function Remapping
AT32F415 Series Reference Manual 6.4.8 C Alternate Function Remapping Please refer to the AF remap and debug I/O configuration register (AFIO_MAP). Table 6- 29 I C1 Remapping Alternate Function I2C1_REMAP = 0 I2C1_REMAP = 1 I2C1_SCL I2C1_SDA Table 6- 30 I...
Page 141: Comp Alternate Function Remapping
AT32F415 Series Reference Manual SDIO_D1 SDIO_D2 PC10 SDIO_D3 PC11 SDIO_D4 SDIO_D5 SDIO_D6 SDIO_D7 SDIO_CK PC12 SDIO_CMD 6.4.11 COMP Alternate Function Remapping Table 6- 34 COMP Alternate Function Remapping Alternate Function COMP_GRMP[1:0]=00 COMP_GRMP[1:0]=01 COMP_GRMP[1:0]=10 COMP1_OUT PA11 COMP2_OUT PA12 6.5 GPIO and AFIO Registers Table 6-35 lists GPIO register map and reset values.
Page 142: Table 6- 36 Afio Register Map And Reset Values
AT32F415 Series Reference Manual Table 6- 36 AFIO Register Map and Reset Values Offset Register AFIO_EVCT 000h Reserved Reset Value 0 0 0 0 0 0 0 0 AFIO_MAP 004h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 143: Port Configuration Register Low (Gpiox_Ctrll) (X = A
AT32F415 Series Reference Manual AFIO_MAP6 02CH Reserved Reserved Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIO_MAP7 030H Reserved Reserved Reserved Reset Value 0 0 0 0 0...
Page 144: Port Configuration Register High (Gpiox_Ctrlh) (A
AT32F415 Series Reference Manual MDEy[1:0]: Portx Mode bit y (y = 0…7) Bit 29:28 Set by software to configure the corresponding I/O ports. Please refer to Table 7-1 for 25:24 port bit configuration. 21:20 17:16 00: Input mode (state after reset) 13:12 01: Output mode;...
Page 145: Port Input Data Register (Gpiox_Iptdt) (X = A
AT32F415 Series Reference Manual 6.5.3 Port Input Data Register (GPIOx_IPTDT) (x = A...E) Address offset: 0x08 Reset value: 0x0000XXXX Reserved IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD IPTD T[15] T[14] T[13] T[12]...
Page 146: Port Bit Reset Register (Iox_Bre) (X = A
AT32F415 Series Reference Manual BSTy: Portx Set bit y (y = 0…15) These bits are write-only and are accessed only by word (16 bits). Bit 15:0 0: No action to the corresponding OPTDTy bits. 1: Set the corresponding OPTDTy bit.
Page 147: Alternate Event Control Register (Afio_Evctrl)
AT32F415 Series Reference Manual LOCKy: Portx Lock bit y (y = 0…15) These bits can be read and written, but they can be written only when the LOCKK bit is 0. Bit 15:0 0: Port configuration is not locked. 1: Port configuration is locked.
Page 148 AT32F415 Series Reference Manual SWJTAG_CONF[2:0]: Serial wire JTAG configuration Only be written by software (reading these bits will return undefined values), and are used to configure SWJ and trace the I/O ports of alternate functions. SWJ ® (Serial Wire JTAG) supports JTAG or SWD access to the Cortex debug port.
Page 149: Alternate External Interrupt Configuration Register 1 (Afio_Extic1)
AT32F415 Series Reference Manual TMR1_REMAP[1:0]: TMR1 remapping Set and cleared by software. It controls the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR), and break input (BKIN) on the GPIO ports. 00: No remapping (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11,...
Page 150: Alternate External Interrupt Configuration Register 2 (Afio_Extic2)
AT32F415 Series Reference Manual EXTINTx[3:0]: EXTINTx configuration (x = 0…3) Can be read and written by software. Used to select the input source for EXTINTx external interrupt. Bit 15:0 0000: PA[x] pin 0100: PE[x] pin 0001: PB[x] pin 0101: PF[x] pin...
Page 151: Alternate External Interrupt Configuration Register 3 (Afio_Extic3)
AT32F415 Series Reference Manual 6.5.12 Alternate External Interrupt Configuration Register 3 (AFIO_EXTIC3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTINT11[3:0] EXTINT10[3:0] EXTINT9[3:0] EXTINT8[3:0] Bit 31:16 Reserved EXTINTx[3:0]: EXTINTx configuration (x = 8…11) Can be read and written by software. Used to select the input source for EXTINTx external interrupt.
Page 152: Af Remap And Debug I/O Configuration Register 3 (Afio_Map3)
AT32F415 Series Reference Manual Reser Reser Reser Reser Reser Reser Reser Reserved Reserved Bit 31:28 Reserved。 COMP_REMAP: COMP internal remap This bit can be set or cleared by software; it controls COMP internal mapping. When this field is set to ’00’, COMP1_OUT is connected to PA0, and COMP2_OUT is connected to PA2；...
Page 153: Af Remap And Debug I/O Configuration Register 4 (Afio_Map4)
AT32F415 Series Reference Manual Reserved for future extension, please all write ‘0’. Bit 23:20 Reserved for future extension, please all write ‘0’. Bit 19:16 Reserved for future extension, please all write ‘0’. Bit 15:12 TMR11_GRMP: TMR11 remapping Bit 11:8 Please refer to TMR11 alternate function remapping.
Page 154: Af Remap And Debug I/O Configuration Register 5 (Afio_Map5)
AT32F415 Series Reference Manual TMR1_GRMP: TMR1 remapping This field can be set or cleared by software; it controls TMR1 internal mapping. Bit 3:0 Please refer to timer alternate function remapping. 0000 ~ 1111: If this bit is not used, please all write ‘0’.
Page 155: Af Remap And Debug I/O Configuration Register 6 (Afio_Map6)
AT32F415 Series Reference Manual 6.5.18 AF Remap and Debug I/O Configuration Register 6 (AFIO_MAP6) Address offset: 0x2C Reset value: 0x00000000 UART4_GRMP USART3_GRMP Reserved USART1_GRMP Reserved SDIO1_GRMP Reserved CAN1_GRMP UART4_GRMP: mUART4 remapping This field can be set or cleared by software; it controls alternate function, UART4_RX and UART_TX remapping.
Page 156 AT32F415 Series Reference Manual GRMP GRMP Reserved for future extension, please all write ‘0’. Bit 31:21 PD01_GRMP: PortD0/PortD1 mapping on OSC_IN/OSC_OUT This bit can be set or cleared by software; it controls PD0 and PD1 GPIO functions mapping. When the main oscillator, HSE, is not used (the 8 MHz RC oscillator operates Bit 20 within the system), PD0 and PD1 can map to the OSC_IN and OSC_OUT pins.
Page 157: Af Remap And Debug I/O Configuration Register 8 (Afio_Map8 )
AT32F415 Series Reference Manual 6.5.20 AF Remap and Debug I/O Configuration Register 8 (AFIO_MAP8) Address offset: 0x34 Reset value: 0x00000000 TMR3_ TMR2_ TMR1_ TMR1_ CH1_ CH4_ CH1_ BK1_ Reserved COMP COMP COMP COMP [1:0] [1:0] [1:0] [1:0] Bit 31:8 Reserved TMR3_CH1_COMP[1:0]: TMR3 CH1 COMP output selection This bit can be set or cleared by software;...
Page 158: Interrupts And Events
The System Tick calibration value is fixed to 9000, which gives a reference time base of 1 ms when the System Tick clock is set to 9 MHz (max. of HCLK/8). 7.1.2 Interrupt and Exception Vectors Table 7-1 lists the vector table of AT32F415 series. Table 7- 1 Vector Table of AT32F415 Series Position Priority...
Page 159 AT32F415 Series Reference Manual Flash global interrupt Configurable FLASH 0x0000_0050 Reset and RCC interrupt Configurable 0x0000_0054 Configurable EXTINT0 EXTI Line0 interrupt 0x0000_0058 Configurable EXTINT1 EXTI Line1 interrupt 0x0000_005C Configurable EXTINT2 EXTI Line2 interrupt 0x0000_0060 Configurable EXTINT3 EXTI Line3 interrupt 0x0000_0064...
Page 160 AT32F415 Series Reference Manual Configurable USART3 USART3 global interrupt 0x0000_00DC Configurable EXTINT15_10 EXTI Line[15:10] interrupt 0x0000_00E0 Configurable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4 USB Wakeup through EXTI line interrupt Configurable Reserved 0x0000_00E8 TMR8 Break interrupt and TMR12 global...
Page 161: External Interrupt/Event Controller (Exti)
AT32F415 Series Reference Manual Configurable Reserved 0x0000_0168 DMA2 channel and DMA2 channel 7 global Configurable DMA2 channel 6_7 0x0000_016C interrupt 7.2 External Interrupt/Event Controller (EXTI) The external interrupt/event controller consists of 23 edge detectors which generate event/interrupt requests. Each input line can be independently configured to select input type (pulse or pending) and the corresponding trigger event (rising edge, falling edge, or both edges).
Page 162: Function Overview
AT32F415 Series Reference Manual 7.2.4 Function Overview To generate interrupts, the interrupt line should be configured and enabled first. This is done by programming the two trigger registers with the desired edge detection and enabling the interrupt request by writing ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated.
Page 163: Figure 7- 2 External Interrupt Gpio Mapping
AT32F415 Series Reference Manual Figure 7- 2 External Interrupt GPIO Mapping EXIT0[3:0] bit in AFIO_EXITC1 register EXIT0 EXIT1[3:0] bit in AFIO_EXITC1 register EXIT1 EXIT15[3:0] bit in AFIO_EXITC4 register PA15 PB15 EXIT15 PC15 To configure the external interrupt/event on GPIO lines with AFIO_EXTICRx, the AFIO clock should first be enabled.
Page 164: Exti Registers Description
AT32F415 Series Reference Manual 7.3 EXTI Registers Description These peripheral registers must be accessed by words (32-bit). Table 7-2 lists the EXTI register map and reset values. Table 7- 2 External Interrupt/Event Controller Map and Reset Values Offset Register EXTI_INTEN MR[22：0]...
Page 165: Event Mask Register (Exti_Evten)
AT32F415 Series Reference Manual 7.3.2 Event Mask Register (EXTI_EVTEN) Address offset: 0x04 Reset value: 0x0000 0000 Reserved MR22 MR21 MR20 MR19 MR18 MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10 Reserved. Must be kept at reset value ‘0’. Bit 31:23 MRx: Event Mask on line x 0: Event request from Line x is masked.
Page 166: Software Interrupt Event Register (Exti_Sw Ie)
AT32F415 Series Reference Manual TR15 TR14 TR13 TR12 TR11 TR10 Reserved. Must be kept at reset value ‘0’. Bit 31:23 TRx: Falling trigger event configuration bit of line x Bit 22:0 0: Falling trigger (event and interrupt) on input line x is disabled.
Page 167: Dma Controller (Dma)
AT32F415 Series Reference Manual PRx: Pending bit 0: No trigger request occurred. Bit 22:0 1: Selected trigger request occurred. This bit is set when the selected edge event occurs on the external interrupt line. This bit is cleared by writing ‘1’ or by changing the polarity of edge detection.
Page 168: Function Overview
AT32F415 Series Reference Manual Figure 8- 1 DMA Block Diagram ICode Flash Flash Interface controller DCode Cortex®-M4F Core System SARM DMA1 request Reset and clock Channel 1 SDIO1,2 DMA2 control (RCC) Channel2 Channel7 Bridge 2 Bridge 1 APB1 APB2 Arbiter...
Page 169: Arbiter
AT32F415 Series Reference Manual for the first transfer is the peripheral base address or memory unit programmed in the DMA_CPBAx or DMA_CMBAx register.  Execute a decrementing operation of the DMA_TCNTx register, which contains the number of unfinished transactions .
Page 170: Programmable Data Transfer Width, Alignment, And Endian
AT32F415 Series Reference Manual from/written to this address when there is peripheral data transfer request. Configure the amount of data to be transferred in the DMA_TCNTx register. After each data transfer, this value will be decremented. Configure channel priority using...
Page 171: Error Management
AT32F415 Series Reference Manual 0x0/B1B0 1: Read B1B0[15:0] at 0x0, then write B1B0[15:0] at 0x0 0x0/B1B0 0x2/B3B2 2: Read B3B2[15:0] at 0x2, then write B3B2[15:0] at 0x2 0x2/B3B2 0x4/B5B4 3: Read B5B4[15:0] at 0x4, then write B5B4[15:0] at 0x4 0x4/B5B4...
Page 172: Interrupts
AT32F415 Series Reference Manual 8.3.6 Interrupts An interrupt can be generated on a DMA half transfer, transfer complete, or transfer error form each DMA channel. For the purpose of flexibility, interrupts are enabled by configuring different bits in the registers.
Page 173: Figure 8- 2 Dma1 Request Mapping
AT32F415 Series Reference Manual Figure 8- 2 DMA1 Request Mapping Per ipheral req uest signal ADC1 Hardware request 1 Fixed software priority TMR2_CH3 Channel1 TMR4_CH1 High priority Software trigger (MEM2MEM bit) Channel1 EN bit SPI1/I2S1_RX Hardware request 2 USART3_TX TMR1_CH1...
Page 174: Table 8- 3 Summary Of Dma1 Requests For Each Channel
AT32F415 Series Reference Manual Table 8- 3 Summary of DMA1 Requests for Each Channel Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI1/I2S1_RX SPI1/I2S1_TX SPI2/I2S2_RX SPI2/I2S2_TX SPI/I USART USART3_TX USART3_RX USART1_TX...
Page 175: Flexible Dma Request Mapping
AT32F415 Series Reference Manual Figure 8- 3 DMA2 Request Mapping Peripheral request signals Fixed hardware priority Hardware request 1 TMR5_CH4 TMR5_TRIG Channel1 High priority Software trigger (MEM2MEM bit) Channel1 EN bit Hardware request 2 TMR5_CH3 TMR5_UP Channel2 Software trigger (MEM2MEM bit)
Page 176: Table 8- 5 Summary Of Flexible Dma Request For Each Channel
AT32F415 Series Reference Manual Table 8- 5 Summary of Flexible DMA Request for Each Channel CHx_SRC value DMA source CHx_SRC value DMA source CHx_SRC value DMA source No select reserved TIM4_CH1 ADC1 I2C1_RX TIM4_CH2 reserved I2C1_TX TIM4_CH3 reserved I2C2_RX TIM4_CH4...
Page 177: Dma Registers
AT32F415 Series Reference Manual 8.4 DMA Registers The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit). Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 with fixed mapping mode since it has only 5 channels.The DMA2 with flexible mapping mode supports up to 5 channels.
Page 178 AT32F415 Series Reference Manual 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ PA[31：0] 038h CPBA3 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ MA[31：0]...
Page 179: Dma Interrupt Status Register (Dma_Ists)
AT32F415 Series Reference Manual DMA_TCNT CNT[15：0] 084h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ PA[31：0] 088h CPBA7 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ MA[31：0]...
Page 180: Dma Interrupt Flag Clear Register (Dma_Iclr)
AT32F415 Series Reference Manual 8.4.2 DMA Interrupt Flag Clear Register (DMA_ICLR) Address offset: 0x04 Reset value: 0x0000 0000 CERR CHTI CTCI CERR CHTI CTCI CERR CHTI CTCI Reserved CERR CHTI CTCI CERR CHTI CTCI CERR CHTI CTCI CERR CHTI CTCI Bit 31:28 Reserved.
Page 181 AT32F415 Series Reference Manual CHPL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low Bit 13:12 01: Medium 10: High 11: Very high MWIDTH[1:0]: Memory size These bits are set and cleared by software. 00: 8 bits...
Page 182: Dma Channel X Number Of Data Register (Dma_Tcntx) (X = 1
AT32F415 Series Reference Manual 8.4.4 DMA Channel x Number of Data Register (DMA_TCNTx) (x = 1 … 7) Address offset: 0x0C + 20 x (channel number – 1) Reset value: 0x0000 0000 Reserved CNT[15:0] Bit 31:16 Reserved. Always read as 0.
Page 183: Dma Channel X Memory Address Register (Dma_Cmbax) (X = 1
AT32F415 Series Reference Manual 8.4.6 DMA Channel x Memory Address Register (DMA_CMBAx) (x = 1 … 7) Address offset: 0x14 + 20 x (channel number – 1) Reset value: 0x0000 0000 When the channel is enabled (CHEN = 1 in the DMA_CHCTRLx register), this register cannot be written.
Page 184: Dma Source Register0 (Dma_Src_Sel0)
AT32F415 Series Reference Manual 8.4.7 DMA Source Register0 (DMA_SRC_SEL0) Address offset: 0 x A0 Reset value: 0x0000 0000 CH4_SRC CH3_SRC CH2_SRC CH1_SRC CH4_SRC: CH4 source selection bit Bit 31:24 When DMA_FLEX_EN=1, the CH4_SRC is used to select CH4 source. Please refer to Section 8.3.8...
Page 185: Timer
AT32F415 Series Reference Manual Timer General-purpose Basic Timer (TMR2 to TMR5) 9.1.1 TMRx Introduction Basic timers consist of a 16-bit auto-reload counter driven by their own programmable prescalers. They can be used for various purposes, including measuring the pulse lengths of input sinals (input capture) or generating output waveforms (output compare and PWM).
Page 186: Tmrx Function Overview
AT32F415 Series Reference Manual Figure 9- 1 General-purpose Timer Block Diagram Internal clock（CK_INT) To other timers Trigger TMRxCLK from RCC ETRF To DAC/ADC Polarity selection, control ETRP TMRX_ETR edge detector, and Input filter TRGO prescaler ITR0 Slave mode ITR1 TRGI...
Page 187: Figure 9- 2 Counter Timing Diagram With Prescaler Division Changing From 1 To 2
AT32F415 Series Reference Manual achieved with the counter of a 16-bit register (TMRx_DIV). Its value can be changed on the fly since the TMRx_DIV control register is buffered. The new prescaler ratio takes effect at the next update event. Figure 9-2 and Figure 9-3 give examples of on-the-fly prescaler ratio change.
Page 188: Counting Mode
AT32F415 Series Reference Manual 9.1.3.2 Counting Mode Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (TMRx_AR register), and restarts from 0 and generates a counter overflow event. An update event can be generated at each counter overflow; setting the UEVG bit in the TMRx_EVEG register (by software or by using the slave mode controller) also generates the update events.
Page 189: Figure 9- 7 Counter Timing Diagram With Internal Clock Divided By N
AT32F415 Series Reference Manual Figure 9- 6 Counter Timing Diagram with Internal Clock Divided by 4 0035 0036 0000 0001 Figure 9- 7 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow...
Page 190: Figure 9- 9 Counter Timing Diagram With Update Event When Arpen = 1 (Tmrx_Ar Is Preloaded)
AT32F415 Series Reference Manual Figure 9- 9 Counter Timing Diagram with Update Event When ARPEN = 1 (TMRx_AR is Preloaded) CK_DIV CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Auto-reload shadow...
Page 191: Figure 9- 10 Counter Timing Diagram With Internal Clock Divided By 1
AT32F415 Series Reference Manual Figure 9- 10 Counter Timing Diagram with Internal Clock Divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow (cnt_overflow) Update event (UEV) Update interrupt flag (UEVIF) Figure 9- 11 Counter Timing Diagram with Internal Clock Divided by 2...
Page 192: Figure 9- 13 Counter Timing Diagram With Internal Clock Divided By N
AT32F415 Series Reference Manual Figure 9- 13 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UEVIF) Figure 9- 14 Counter Timing Diagram with Update Event When ARPEN = 0...
Page 193: Figure 9- 15 Counter Timing Diagram With Internal Clock Divided By 1, Tmrx_Ar = 0X6
AT32F415 Series Reference Manual generating both update and capture interrupts when the capture event occurs and the counter is cleared. When an update event occurs, all the registers are updated, and the update flag bit (the UEVIF bit in the TMRx_STS register) is set (according to the UEVRS bit).
Page 194: Figure 9- 17 Counter Timing Diagram With Internal Clock Divided By 4, Tmrx_Ar = 0X36
AT32F415 Series Reference Manual Figure 9- 17 Counter Timing Diagram with Internal Clock Divided by 4, TMRx_AR = 0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow Update event (UEV) Update interrupt flag (UEVIF)
Page 195: Clock Selection
AT32F415 Series Reference Manual Figure 9- 20 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Writing new values to the TMRx_AR register...
Page 196: Figure 9- 22 Ti2 External Clock Connection Example
AT32F415 Series Reference Manual Figure 9- 22 TI2 External Clock Connection Example TMRx_SMC TRGSEL[2:0] TI2F TI1F ITRx Encoder mode TI1_ED TRGI TI2F_Rising TI1FP1 External clock mode 1 TI2FP2 Edge Filter CK_DIV ETRF detector External clock TI2F_Falling ETRF mode 2 CK_INT...
Page 197: Capture/Compare Channel
AT32F415 Series Reference Manual Figure 9-24 shows the block diagram of the external trigger input. Figure 9- 24 Block Diagram of External Trigger Input TI2F TI1F Encoder mode ETRP TRGI Divider Filter ETR pin External clock CK_DIV mode 1 /1,/2,/4,/8...
Page 198: Figure 9- 26 Capture/Compare Channel (E.g. Channel 1 Input Stage)
AT32F415 Series Reference Manual Figure 9- 26 Capture/Compare Channel (e.g. Channel 1 Input Stage) TI1F_ED To the salve mode controller TI1F_Rising TI1F Edge Filter TI1FP1 detector downcounter f DTS TI1F_Falling TI2FP1 IC1PS Divider /1, /2, /4, /8 IC1DF[3:0] TMRx_CCE TMRx_CCM1...
Page 199: Input Capture Mode
AT32F415 Series Reference Manual The capture/compare block is made of one preload register and one shadow register. Write and read only access the preload register. In capture mode, captures are actually done in the shadow register, and then copied into the preload register.
Page 200: Pwm Input Mode
AT32F415 Series Reference Manual 9.1.3.6 PWM Input Mode This mode is a special case of input capture mode. The procedure is the same as input capture mode except for the following conditions:  Two ICx signals are mapped on the same TIx input.
Page 201: Forced Output Mode
AT32F415 Series Reference Manual 9.1.3.7 Forced Output Mode In output mode (CxSEL = 00 in the TMRx_CCMx register), output compare signal (OCxREF and the corresponding OCx) can be forced to be active or inactive level directly by software, independent of any comparison between the output compare register and the counter.
Page 202: Figure 9- 30 Output Compare Mode, Toggle On Oc1
AT32F415 Series Reference Manual Figure 9- 30 Output Compare Mode, Toggle on OC1 Write B201h in the CC1 register TMR1_CNT 0039 003A 003B B200 B201 TMR1_CC1 003A B201 OC1REF = OC1 Match detected on CC1 Interrupt generated if enabled 2020.06.28 Page 202 Version 1.02...
Page 203: Pwm Mode
AT32F415 Series Reference Manual 9.1.3.9 PWM Mode Pulse width modulation mode can generate a signal with its frequency determined by the TMRx_AR register and its duty cycle determined by TMRx_CCx register. Writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxMODE bit in the TMRx_CCMx register can independently configure each OCx output channel and generate single-channel PWM.
Page 204: Figure 9- 32 Center-Aligned Pwm Waveforms (Ap = 8)
AT32F415 Series Reference Manual Downcounting configuration Downcounting is active when the DIR bit in the TMRx_CTRL1 register is high. Please refer to Section 9.2.3.2. In PWM mode 1, the reference signal, OCxREF, is low once MRx_CNT > TMRx_CCx; else, it becomes high. If the compare value in TMRx_CCx is greater than the auto-reload value in TMRx_AR, then OCxREF is held at ‘1’.
Page 205: One-Pulse Mode
AT32F415 Series Reference Manual the counter is counting up, it will keep counting up. ― The direction is updated if 0 or the TMRx_AR value is written to the counter, but no update event UEV will be generated.  The safest way to use the center -aligned mode is to generate an update by software (setting the UEVG bit in the TMRx_EVEG register) before enabling the counter, and do not write the co unter while it is running.
Page 206: Clearing Ocxref Signal On An External Event
AT32F415 Series Reference Manual TMRx_CTRL1 register. Afterwards, write compare value in the TMRx_CC1 register, write auto-reload value in the TMRx_AR register, modify the UEVG bit to generate an update event, and wait for an external trigger event on TI2. In this example, C1P = ‘0’.
Page 207: Encoder Interface Mode
AT32F415 Series Reference Manual 9.1.3.12 Encoder Interface Mode To select the encoder interface mode, write SMSEL = 001 in the TMRx_SMC register if the counter is counting on TI2 edges only; write SMSEL = 010 if it is counting on TI1 edges only; write SMSEL = 011 if it is counting on both TI1 and TI2 edges.
Page 208: Timer Input Xor Function
AT32F415 Series Reference Manual Figure 9- 35 Example of Counter Operation in Encoder Interface Mode Figure 9-36 is an example of counter behavior when IC1FP1 polarity is inverted (the same configuration as the above example, except for C1P = ‘1’).
Page 209: Figure 9- 37 Control Circuit In Reset Mode
AT32F415 Series Reference Manual preloaded registers (TMRx_AR, TMRx_CCx) will be updated. In the following example, the up counter is cleared due to a rising edge on TI1 input:  Configure channel 1 to detect the rising edges on TI1. Configure the input filter duration (in this example, no filter is needed, so keep IC1DF = 0000).
Page 210: Figure 9- 38 Control Circuit In Gated Mode
AT32F415 Series Reference Manual Figure 9- 38 Control Circuit in Gated Mode CNT_EN Counter clock = CK_CNT = CK_DIV 30 31 32 33 35 36 37 38 Counter register TRGIF Write TRGIF = 0 Slave mode: Trigger mode The counter can be enabled according to the selected level of input.
Page 211: Timer Synchronization
AT32F415 Series Reference Manual rising edge of the ETR signal: 1. Configure the external trigger input circuit through the TMRx_SMC register: ─ ETDF = 0000: No filter ─ ETD = 00: Prescaler is disabled. ─ ETRGP = 0: Detect the rising edges on ETR and set ECLKEN = 1 to enable the external clock mode 2.
Page 212: Figure 9- 42 Timer 1 Oc1Ref Controls Timer 2
AT32F415 Series Reference Manual  Configure Timer 1 as master mode so that it can output a periodic trigger signal on each update event UEV. If MMSEL = ‘010’ in the TMR1_CTRL2 register, a rising edge is outputted on TRGO1 each time when an update event is generated.
Page 213: Figure 9- 43 Control Timer 2 By Enabling Timer 1
AT32F415 Series Reference Manual register:  Configure Timer 1 as master mode to send its output compare 1 reference signal (OC1REF) as trigger output (MMSEL = 100 in the TMR1_CTRL2 register).  Configure the Timer 1 OC1REF waveform (TMR1_CCM1 register).
Page 214: Figure 9- 44 Using Timer 1 Update To Trigger Timer 2
AT32F415 Series Reference Manual Figure 9- 44 Using Timer 1 Update to Trigger Timer 2 As in the above example, both counters can be initialized before starting counting. Figure 9-45 shows the behavior with the same configuration as the above example, but using trigger mode instead of gated mode (SMSEL = 110 in the TMR2_SMC register).
Page 215: Debug Mode
AT32F415 Series Reference Manual register)  Set CNTEN = 1 in the TMR1_CTRL2 register to start Timer 2.  Set CNTEN = 1 in the TMR1_CTRL1 register to start Timer 1. Starting two timers synchronously by an external trigger In this example, when Timer 1 TI1 input rises, enable Timer 1, and at the same time Timer 2 is enabled.
Page 216: Tmrx Registers
AT32F415 Series Reference Manual 9.1.4 TMRx Registers These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 9-2, all the TMRx registers are mapped to a 16-bit addressable space. Table 9- 2 TMRx– Register Table and Reset Values...
Page 217: Control Register 1 (Tmrx_Ctrl1)
AT32F415 Series Reference Manual TMRx_ CCM2 Input Reserved capture mode Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_ Reser Reser Reser 0x20 Reserved Reset Value CNT[31：16] CNT[15：0] TMRx_CNT 0x24...
Page 218 AT32F415 Series Reference Manual CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency and sampling frequency used by the digital filters (ETR, TIx). 00: t Bit 9:8 �� _�� 01: t = 2 x t ��...
Page 219: Control Register 2 (Tmrx_Ctrl2)
AT32F415 Series Reference Manual 9.1.4.2 Control Register 2 (TMRx_CTRL2) Address offset: 0x04 Reset value: 0x0000 TI1S Reserved MMSEL[2:0] Reserved Bit 15:8 Reserved. Always read as 0. TI1SEL: TI1 selection 0: TMRx_CH1 pin is connected to TI1 input. Bit 7 1: TMRx_CH1, TMRx_CH2, and TMRx_CH3 pins are connected to the TI1 input after XORed.
Page 220 AT32F415 Series Reference Manual ECLKEN: External clock enable This bit enables external clock mode 2. 0: External clock mode 2 is disabled 1: External clock mode 2 is enabled. The counter is clocked by any active edge on the ETRF signal.
Page 221: Dma/Interrupt Enable Register (Tmrx_Die)
AT32F415 Series Reference Manual SMSEL[2:0]: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is relevant to the selected external input polarity (Please refer to input control register and control register description.) 000: Slave mode is disabled - If CNTEN = 1, the prescaler is clocked directly by the internal clock.
Page 222: Status Register (Tmrx_Sts)
AT32F415 Series Reference Manual C2DE: Capture/Compare 2 DMA request enable Bit 10 0: Capture/Compare 2 DMA request is disabled. 1: Capture/Compare 2 DMA request is enabled. C1DE: Capture/Compare 1 DMA request enable Bit 9 0: Capture/Compare 1 DMA request is disabled.
Page 223: Event Generation Register (Tmrx_Eveg)
AT32F415 Series Reference Manual TRGIF: Trigger interrupt flag This flag is set by hardware on trigger event (When the slave mode controller is in all modes except for gated mode, active edge is detected on TRGI input, or any edge in Bit 6 the gated mode).
Page 224: Capture/Compare Mode Register 1 (Tmrx_Ccm1)
AT32F415 Series Reference Manual C3G: Capture/Compare 3 generation Bit 3 Please refer to C1G description. C2G: Capture/Compare 2 generation Bit 2 Please refer to C1G description. C1G: Capture/Compare 1 generation This bit is set by software to generate a capture/compare event. It is cleared automatically by hardware.
Page 225 AT32F415 Series Reference Manual OC1MODE[2:0]: Output compare 1 enable The bits define the behavior of the output reference signal OC1REF, and OC1REF determines OC1 value. OC1REF is active high, while active level of OC1 is determined by the C1P bit.
Page 226: Capture/Compare Mode Register 2 (Tmrx_Ccm2)
AT32F415 Series Reference Manual C2SEL[1:0]: Capture/Compare 2 selection The bits define the channel direction (input/output), and input pin selection: 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 227 AT32F415 Series Reference Manual C4SEL[1:0]: Capture/Compare 4 selection The bits define the channel direction (input/output), and input pin selection: 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3.
Page 228: Capture/Compare Enable Register (Tmrx_Cce)
AT32F415 Series Reference Manual C3SEL[1:0]: Capture/Compare 3 selection The bits define the channel direction (input/output), and input pin selection: 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4.
Page 229: Counter (Tmrx_Cnt)
AT32F415 Series Reference Manual Table 9- 4 Standard OCx Channel Output Control Bit CxEN Bit OCx Output State Output disabled (OCx = 0, OCx_EN = 0) OCx = OCxREF + Polarity, OCx_EN = 1 Note: The state of the external I/O pins connected to the standard O Cx channels is determined by the OCx channel state and the GPIO and AFIO registers.
Page 230: Auto-Reload Register (Tmrx_Ar)
AT32F415 Series Reference Manual 9.1.4.12 Auto-reload Register (TMRx_AR) Address offset: 0x2C Reset value: 0x0000 AR[31:16] AR[15:0] AR[31:16]: Auto-reload value Bit 31:16 When TMR2 or TMR5 enables plus mode (The PMEN bit in the TMR_CTRL1 register), AR is expanded to 32 bits.
Page 231: Capture/Compare Register 2 (Tmrx_Cc2)
AT32F415 Series Reference Manual 9.1.4.14 Capture/Compare Register 2 (TMRx_CC2) Address offset: 0x38 Reset value: 0x0000 CC2[31:16] CC2[15:0] CC2[31:16]: Capture/Compare 2 value Bit 31:16 When TMR2 or TMR5 enables plus mode (The PMEN bit in the TMR_CTRL1 register), CC2 is expanded to 32 bits.
Page 232: Capture/Compare Register 4 (Tmrx_Cc4)
AT32F415 Series Reference Manual 9.1.4.16 Capture/Compare Register 4 (TMRx_CC4) Address offset: 0x40 Reset value: 0x0000 CC4[31:16] CC4[15:0] CC4[31:16]: Capture/Compare 4 value Bit 31:16 When TMR2 or TMR5 enables plus mode (The PMEN bit in the TMR_CTRL1 register, CC4 is expanded to 32 bits.
Page 233: Dma Address In Burst Mode (Tmrx_Dmaba)
AT32F415 Series Reference Manual 9.1.4.18 DMA Address in Burst Mode (TMRx_DMABA) Address offset: 0x4C Reset value: 0x0000 DMABA[15:0] DMABA[15:0]: DMA register for burst accesses A read or write to the TMRx_DMABA register accesses the register located at the following address:...
Page 234: Tmr10 And Tmr11 Main Function
AT32F415 Series Reference Manual Figure 9- 47 General-purpose TMR9/12 Block Diagram Internal clock (CK_INT) TMRxCLK from RCC Trigger controller ITR0 ITR1 ITR2 Slave mode TRGI ITR3 controller TI1F_ED Reset, enable, TI1FP1 up counting TI2FP2 Auto-reload register Stop, clear CK_DIV CK_CNT...
Page 235: Figure 9- 48 Block Diagram Of General-Purpose Timers Tmr10/11
AT32F415 Series Reference Manual Figure 9- 48 Block Diagram of General-purpose Timers TMR10/11 Internal clock (CK_INT) Trigger TMRxCLK from RCC controller Enable couting Auto-reload register Stop, clear CK_DIV CK_CNT +/- CNT Counter prescaler CC1I CC1I TI1FP1 Input filter and IC1PS...
Page 236: Tmrx Function Overview
AT32F415 Series Reference Manual 9.2.3 TMRx Function Overview 9.2.3.1 Time-base Unit This programmable timer mainly consists of a 16-bit counter and relevant auto-reload registers. The counter can count up, down, or both up and down. The counter clock is obtained through a prescaler.
Page 237: Counter Mode
AT32F415 Series Reference Manual Figure 9- 50 Counter Timing Diagram with Prescaler Division Changing from 1 to 4 CK_DIV CNT_EN Timer clock = CK_CNT Counter register Update event (UEV) Prescaler control register Writing new values to the TMRx_DIV register Prescaler buffer Prescaler counter 9.2.3.2...
Page 238: Figure 9- 52 Counter Timing Diagram With Internal Clock Divided By 2
AT32F415 Series Reference Manual Figure 9- 52 Counter Timing Diagram with Internal Clock Divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0001 0034 0035 0036 0000 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UEVIF)
Page 239: Clock Selection
AT32F415 Series Reference Manual Figure 9- 55 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not Preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Writing new values to the TMRx_AR register...
Page 240: Figure 9- 57 Control Circuit In Normal Mode With Internal Clock Divided By 1
AT32F415 Series Reference Manual Internal clock source (CK_INT) For TMR10/TMR11 and TMR13/TMR14, internal clock source is the clock source by default. For TMR9 and TMR12, if the slave mode controller is disabled (SMSEL = 000 in the TMRx_SMC register), the CNTEN, DIR (in the TMRx_CTRL1 register), and UEVG bits (in the TMRx_EVEG register) are the actual control bits, and they can be changed only by software (except for the UEVG bit, which will be cleared automatically).
Page 241: Capture/Compare Channel
AT32F415 Series Reference Manual 6. Enable the counter by writing CNTEN = ‘1’ in the TMRx_CTRL1 register. When a rising edge occurs on TI2, the counter counts once, and the TRGIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter depends on the resynchronization circuit on TI2 input.
Page 242: Input Capture Mode
AT32F415 Series Reference Manual Figure 9- 61 Capture/Compare Channel 1 Main Circuit APB bus MCU peripheral interface high Read CC1H read_in_progress Write CC1H write_in_progress Capture/Compare preload register Read CC1L Write CC1L capture_transfer capture_transfer Input C1SEL mode C1SEL Input C1SEL mode...
Page 243: Pwm Input Mode (Only Tmr9)
AT32F415 Series Reference Manual TMRx_CC1 register must be linked to the TI1 input. The channel is configured as input as long as the C1SEL is not ‘00’. The TM1_CC1 register becomes read - only.  Program the desired input filter duration according to the input signal (if the input is TIx, the control bit of the input filter is the ICxDF bit in the TMRx_CCMx register).
Page 244: Forced Output Mode
AT32F415 Series Reference Manual Figure 9- 63 PWM Input Mode Timing TMRx_CNT 0004 0000 0001 0002 0003 0004 0000 TMRx_CC1 0004 0002 TMRx_CC2 IC2 capture IC1 capture IC1 capture period pulse width IC2 capture measurement measurement Reset counter Since only TI1FP1 and TI2FP2 are connected to the slave mode controller, the PWM input mode can be used only with the TMRx_CH1/TMRx_CH2 signals.
Page 245: Pwm Mode
AT32F415 Series Reference Manual 1. Select the counter clock (internal, external, and prescaler). 2. Write the corresponding data to the TMRx_AR and the TMRx_CCx registers. 3. Set the CxIE and/or CxDE bits if an interrupt and/or DMA request is to be generated.
Page 246: One-Pulse Mode
AT32F415 Series Reference Manual Figure 9- 65 Edge-aligned PWM Waveforms (AR = 8) Counter register OCXREF CCx = 4 CCxIF OCXREF CCx = 8 CCxIF OCXREF CCx > 8 ‘1’ CCxIF ‘0’ OCXREF CCx = 0 CCxIF 9.2.3.10 One-pulse Mode One-pulse mode (OPM) is quite different from the above-mentioned modes.
Page 247: Timer And External Trigger Synchronization (Tmr9 Only)
AT32F415 Series Reference Manual  Write SMSEL = ‘110’ in the TMRx_SMC register (trigger mode), and TI2FP2 is used to enable the counter. The OPM waveform is defined by the value written to the compare registers (the clock frequency and the counter prescaler should be taken into account).
Page 248: Figure 9- 67 Control Circuit In Reset Mode
AT32F415 Series Reference Manual auto-reload register TMRx_AR = 0x36. The delay between the rising edge on TI1 and the actual reset of the counter is determined by the resynchronization circuit on TI1 input. Figure 9- 67 Control Circuit in Reset Mode Slave mode: Gated mode The counter can be enabled according to the selected level of input.
Page 249: Timer Synchronization (Tmr9 Only)
AT32F415 Series Reference Manual Slave mode: Trigger mode The counter can be enabled according to the selected level of input. In the following example, the counter starts to count up at rising edge on TI2 input:  Configure channel 2 to detect the rising edge on TI2. Configure the input filter duration (in this example, no filter is needed, so keep IC1DF = 0000).
Page 250 AT32F415 Series Reference Manual 0x0000 0 0 0 0 0 0 0 TMRx_SMC 0x08 Reserved 0x0000 0 0 0 0 0 0 TMRx_DIE 0x0C Reserved 0x0000 0 0 0 TMRx_STS 0x10 Reserved 0x0000 0 0 0 TMRx_ EVEG 0x14 Reserved...
Page 251: Control Register 1 (Tmrx_Ctrl1)
AT32F415 Series Reference Manual 9.2.4.1 Control Register 1 (TMRx_CTRL1) Address offset: 0x00 Reset value: 0x0000 ARPE UEVR UEVD CNTE Reserved Reserved CLKDIV [1:0] Bit 15:10 Reserved. Always read as 0. CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency and sampling frequency used by the digital filters (ETR, TIx).
Page 252: Slave Mode Control Register (Tmrx_Smc)
AT32F415 Series Reference Manual 9.2.4.2 Slave Mode Control Register (TMRx_SMC) Address offset: 0x08 Reset value: 0x0000 Reserved TRGSEL[2:0] erve SMSEL[2:0] Bit 15:7 Reserved. Always read as 0. TRGSEL[2:0]: Trigger selection The bits select the trigger input used to synchronize the counter.
Page 253: Dma/Interrupt Enable Register (Tmrx_Die)
AT32F415 Series Reference Manual 9.2.4.3 DMA/Interrupt Enable Register (TMRx_DIE) Address offset: 0x0C Reset value: 0x0000 Reserved Reserved Bit 15:7 Reserved. Always read as 0. TRGIE: Trigger interrupt enable Bit 6 0: Trigger interrupt is disabled. 1: Trigger interrupt is enabled.
Page 254: Status Register (Tmrx_Sts)
AT32F415 Series Reference Manual 9.2.4.4 Status Register (TMRx_STS) Address offset: 0x10 Reset value: 0x0000 Reserved Reserved Reserved Bit 15:11 Reserved. Always read as 0. C2OF: Capture/Compare 2 overcapture flag Bit 10 Please refer to C1OF description. C1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured as input capture mode.
Page 255: Event Generation Register (Tmrx_Eveg)
AT32F415 Series Reference Manual 9.2.4.5 Event Generation Register (TMRx_EVEG) Address offset: 0x14 Reset value: 0x0000 Reserved Reserved Bit 15:7 Reserved. Always read as 0. TRGG: Trigger generation This bit is set by software to generate a trigger event. It is cleared automatically by hardware.
Page 256: Capture/Compare Mode Register 1 (Tmrx_Ccm1)
AT32F415 Series Reference Manual 9.2.4.6 Capture/Compare Mode Register 1 (TMRx_CCM1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by the corresponding CxSEL bits. All the other bits of this register have different functions in input and output modes.
Page 257 AT32F415 Series Reference Manual OC1PEN: Output compare 1 preload enable 0: Preload function of TMRx_CC1 is disabled. TMRx_CC1 can be written at any time, and the new value takes effect immediately. 1: Preload function of TMRx_CC1 is enabled. Read/Write operations only access the Bit 3 preload register.
Page 258 AT32F415 Series Reference Manual IC1DIV[1:0]: Input capture 1 prescaler The bits define CC1 input (IC1) prescaler ratio. Once C1EN = ‘0’ (in the TMRx_CCE register), the prescaler is reset. 00: No prescaler. Capture is done each time when an edge is detected on the capture Bit 3:2 input.
Page 259: Capture/Compare Enable Register (Tmrx_Cce)
AT32F415 Series Reference Manual 9.2.4.7 Capture/Compare Enable Register (TMRx_CCE) Address offset: 0x20 Reset value: 0x0000 Reserved erve erve Bit 15:8 Reserved. Always read as 0. C2NP: Capture/Compare 2 output polarity Bit 7 Please refer to C1NP description. Bit 6 Reserved. Always read as 0.
Page 260: Counter (Tmrx_Cnt)
AT32F415 Series Reference Manual 9.2.4.8 Counter (TMRx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] CNT[15:0]: Counter value Bit 15:0 9.2.4.9 Prescaler (TMRx_DIV) Address offset: 0x28 Reset value: 0x0000 DIV[15:0] DIV[15:0]: Prescaler value Bit 15:0 The counter clock frequency CK_CNT is fCK_DIV/(DIV[15:0]+1).
Page 261: Capture/Compare Register 1 (Tmrx_ Cc1)
AT32F415 Series Reference Manual 9.2.4.11 Capture/Compare Register 1 (TMRx_CC1) Address offset: 0x34 Reset value: 0x0000 CC1[15:0] CC1[15:0]: Capture/Compare 1 value If CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 262: Control Register 1 (Tmrx_Ctrl1)
AT32F415 Series Reference Manual TMRx_STS 0x10 Reserved Reserved Reset Value TMRx_ EVEG 0x14 Reserved Reset Value TMRx_ CCM1 Output Reserved compare mode Reset Value 0 0 0 0 0 0 0 0x18 TMRx_ CCM1 IC1DF[3：0] Input capture Reserved mode Reset Value...
Page 263: Dma/Interrupt Enable Register (Tmrx_Die)
AT32F415 Series Reference Manual ARPEN: Auto-reload preload enable Bit 7 0: TMRx_AR register is not buffered. 1: TMRx_AR register is buffered. Bit 6:3 Reserved. Always read as 0. UEVRS: Update request source This bit is set and cleared by software to select the UEV event sources.
Page 264 AT32F415 Series Reference Manual C1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured as input capture mode. It is cleared by writing ‘0’. Bit 9 0: No overcapture is detected. 1: When the counter value is captured to the TMRx_CC1 register, C1IF flag is already set.
Page 265: Event Generation Register (Tmrx_Eveg)
AT32F415 Series Reference Manual 9.2.5.4 Event Generation Register (TMRx_EVEG) Address offset: 0x14 Reset value: 0x0000 Reserved Bit 15:2 Reserved. Always read as 0. C1G: Capture/Compare 1 generation This bit is set by software to generate a capture/compare event. It is cleared automatically by hardware.
Page 266 AT32F415 Series Reference Manual OC1MODE[2:0]: Output compare 1 enable The bits define the behavior of the output reference signal, OC1REF, and OC1REF determines the OC1 value. OC1REF is active high, while the active level of OC1 is determined by the C1P bit.
Page 267: Capture/Compare Enable Register (Tmrx_Cce)
AT32F415 Series Reference Manual IC1DF[3:0]: Input capture 1 filter The bits define the frequency used to sample TI1 input and the length of digital filter. The digital filter is an event counter which records N consecutive events that are needed to...
Page 268: Counter (Tmrx_Cnt)
AT32F415 Series Reference Manual C1EN: Capture/Compare 1 output enable CC1 channel is configured as output: 0: OFF－ OC1 output is disabled. 1: ON－ OC1 is outputted on the corresponding output pin. Bit 0 CC1 channel is configured as input: This bit determines whether the counter value can be captured to TMRx_CC1 register.
Page 269: Capture/Compare Register 1 (Tmrx_Cc1)
AT32F415 Series Reference Manual 9.2.5.10 Capture/Compare Register 1 (TMRx_CC1) Address offset: 0x34 Reset value: 0x0000 CC1[15:0] CC1[15:0]: Capture/Compare 1 value If CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value).
Page 270: Advanced-Control Timer (Tmr1)
AT32F415 Series Reference Manual Advanced-control Timer (TMR1) 9.3.1 TMR1 Introduction The advanced-control timer (TMR1, TMR8, and TMR15) consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, embedded dead-time, and complementary PWM, and so on).
Page 271: Tmr1 Function Overview
AT32F415 Series Reference Manual Figure 9- 70 Block Diagram of Advanced-control Timer Internal clock（CK_INT) To other timers Trigger CK_TMR from RCC ETRF To DAC/ADC Polarity selection, ETRP controller TMRX_ETR edge detection, and Input filter TRGO prescaler ITR0 Slave mode TRGI...
Page 272: Figure 9- 71 Counter Timing Diagram With Prescaler Division Changing From 1 To 2
AT32F415 Series Reference Manual Please note that after the CNTEN bit in the TMRx_CTRL register is set, the counter starts counting after one clock cycle. Prescaler The prescaler can divide the counter clock frequency by any factor between 1 ~ 65536, and this is achieved with a 16-bit counter controlled by a 16-bit register (in the TMRx_DIV register).
Page 273: Counter Mode
AT32F415 Series Reference Manual 9.3.3.2 Counter Mode Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TMRx_AR counter), and restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting reaches the programmed count in the repetition counter register (TMRx_RC).
Page 274: Figure 9- 74 Counter Timing Diagram With Internal Clock Divided By 2
AT32F415 Series Reference Manual Figure 9- 74 Counter Timing Diagram with Internal Clock Divided by 2 CK_DIV CNT_EN Timer clock = CK_CNT Counter register 0002 0034 0035 0036 0001 0003 0004 Counter overflow Update event Update interrupt flag (UEVIF) Figure 9- 75 Counter Timing Diagram with Internal Clock Divided by 4...
Page 275: Figure 9- 77 Counter Timing Diagram With Update Event When Arpen = 0 (Tmrx_Ar Not Preloaded)
AT32F415 Series Reference Manual Figure 9- 77 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not Preloaded) CK_DIV CNTEN Timer clock = CK_CNT Counter register Counter overflow Update event Update interrupt flag (UEVIF) Auto-reload register Write new values to the TMRx_AR register...
Page 276: Figure 9- 79 Counter Timing Diagram With Internal Clock Divided By 1
AT32F415 Series Reference Manual event occurs until the UEVDIS bit is cleared. However, the counter still counts from the current auto- reload value, and the prescaler counter restarts from 0 (but the prescaler ratio does not change). In addition, if the UEVRS (update request selection) bit in the TMRx_CTRL1 register is set, setting the UEVG bit generates an update event UEV, but the UEVIF flag is not set (so no interrupt or DMA request is generated).
Page 277: Figure 9- 81 Counter Timing Diagram With Internal Clock Divided By 4
AT32F415 Series Reference Manual Figure 9- 81 Counter Timing Diagram with Internal Clock Divided by 4 0001 0000 0036 0035 Figure 9- 82 Counter Timing Diagram with Internal Clock Divided by N CK_DIV Timer clock CK_CNT Counter register Counter overflow...
Page 278: Figure 9- 84 Counter Timing Diagram With Internal Clock Divided By 1, Tmrx_Ar = 0X6
AT32F415 Series Reference Manual register) – 1, generates a counter overflow event, and counts from the auto-reload value down to 1 and generates a counter underflow event. Then, it restarts counting from 0. In this mode, the DIR direction bit in the TMRx_CTRL1 register cannot be written. It is updated by hardware and indicates the current counting direction.
Page 279: Figure 9- 6 Counter Timing Diagram With Internal Clock Divided By 4
AT32F415 Series Reference Manual Figure 9- 85 Counter Timing Diagram with Internal Clock Divided by 2 CK_DIV CNT_EN Timer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event Update interrupt flag (UEVIF) Figure 9- 86 Counter Timing Diagram with Internal Clock Divided by 4, TMRx_AR =...
Page 280: Figure 9- 88 Counter Timing Diagram With Update Event When Arpen = 1 (Counter Underflow)
AT32F415 Series Reference Manual Figure 9- 88 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter underflow) CK_DIV CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event Update interrupt flag (UEVIF) Auto-reload register Write new values to the TMRx_AR register...
Page 281: Repetition Counter
AT32F415 Series Reference Manual 9.3.3.3 Repetition Counter Section 9.3.3.1 describes how an update event (UEV) is generated on counter overflows/underflows. It is actually generated only when the repetition counter reaches ‘0’. This feature can be very useful when generating PWM signals.
Page 282: Clock Selection
AT32F415 Series Reference Manual 9.3.3.4 Clock Selection The counter clock can be provided by the following clock sources:  External clock mode 1: External input pin  External clock mode 2: External trigger input ETR  Internal trigger inputs (ITRx): Using one timer as the prescaler for another timer.
Page 283: Figure 9- 93 Control Circuit In External Clock Mode 1
AT32F415 Series Reference Manual 1. Configure channel 2 to detect the rising edges on the TI2 input by writing C2SEL = ‘01’ in the TMRx_CCM1 register. 2. Configure the input filter duration by writing the IC2DF[3:0] bits in the TMRx_CCM1 register (if no filter is needed, keep IC2DF = 0000).
Page 284: Capture/Compare Channel
AT32F415 Series Reference Manual 1. Since no filter is needed in this example, write ETDF[3:0] = 0000 in the TMRx_SMC register. 2. Set the prescaler by writing ETD[1:0] = 01 in the TMRx_SMC register. 3. Select the rising edge detection on ETR by writing ETRGP = 0 in the TMRx_SMC register.
Page 285: Figure 9- 61 Capture/Compare Channel 1 Main Circuit
AT32F415 Series Reference Manual The output stage generates an intermediate waveform OCxRef (active high) which serves as reference. The polarity of final output signal is determined by the end of the chain. Figure 9- 97 Capture/Compare Channel 1 Main Circuit...
Page 286: Input Capture Mode
AT32F415 Series Reference Manual Figure 9- 99 Capture/Compare Channel Output Stage (Channel 4) To master mode controller Output enable circuit CNT > CC4 TMR1_CCE Output OC4REF mode CNT = CC4 controller TMR1_CCE C4EN TMR1_BRKDT MOEN OSIMI OC4IS TMR1_CTRL2 OC2MODE[2:0] TMR1_CCM2 The capture/compare block is made of one preload register and one shadow register.
Page 287: Pwm Input Mode
AT32F415 Series Reference Manual When an input capture occurs:  The counter value is sent to the TMRx_CC1 register on active transition.  C1IF flag is set (interrupt flag). W hen at least two consecutive captures occur and the C1IF flag is not cleared, C1OF is also set.
Page 288: Forced Output Mode
AT32F415 Series Reference Manual Note: Since only TI1FP1 and TI2FP2 are connected to the slave mode controller, the PWM input mode can be used only with the TMRx_CH1/TMRx_CH2 signals. 9.3.3.8 Forced Output Mode In output mode (CxSEL = 00 in the TMRx_CCMx register), output compare signal (OCxREF and the corresponding OCx/OCxN) can be forced to be active or inactive level directly by software, independent of any comparison between the output compare register and the counter.
Page 289: Output Compare Mode
AT32F415 Series Reference Manual 9.3.3.9 Output Compare Mode This function is used to control an output waveform or to indicate that a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function proceeds as follows: ...
Page 290: Pwm Mode
AT32F415 Series Reference Manual 9.3.3.10 PWM Mode Pulse width modulation mode can generate a signal with its frequency determined by the TMRx_AR register and its duty cycle determined by TMRx_CCx register. Writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxMODE bit in the TMRx_CCMx register can independently configure each OCx output channel and generate single-channel PWM.
Page 291: Figure 9- 103 Center-Aligned Pwm Waveforms (Apr = 8)
AT32F415 Series Reference Manual other configurations have the same effect on the OCxREF/OCx signals). According to different CMSEL bit configurations, the compare flag is set when the counter counts up, counts down, or counts both up and down. The direction bit (DIR) in the TMRx_CTRL1 register is updated by hardware and must not be changed by software.
Page 292: Complementary Output And Dead-Time Insertion
AT32F415 Series Reference Manual 9.3.3.11 Complementary Output and Dead-time Insertion The advanced-control timers (TMR1, TMR8, and TMR15) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time. Users can adjust dead-time according to the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays resulted from power switches, etc.)
Page 293: Using The Break Function
AT32F415 Series Reference Manual Figure 9- 106 Dead-time Waveform Delay W hich is Greater than Positive Pulse OCxREF OCxN Delay The dead-time delay is the same for each channel, and is programmable with the DTGS bits in the TMRx_BRKDT register. Please refer to Section 9.3.4.18...
Page 294 AT32F415 Series Reference Manual enable output, else the enable output remains h igh.  When complementary outputs are used: ─ The outputs are first put at reset state, namely, inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.
Page 295: Clearing Ocxref Signal On An External Event
AT32F415 Series Reference Manual Figure 9- 107 Outputs in Response to a Break Break (MOEN) OCxREF (OCxN not implemented, CxP = 0, OCxIS = 1) (OCxN not implemented, CxP = 0, OCxIS = 0) (OCxN not implemented, CxP = 0, OCxIS = 1)
Page 296: 6-Step Pwm Output Generation
AT32F415 Series Reference Manual The external trigger polarity (ETRGP) and the external trigger filter (ETDF) can be configured according to users’ needs. Figure 10-108 shows how OCxREF signal behaves to respond to different OCxDIS values when the ETRF input becomes high. In this example, the timer TMRx is programmed in PWM mode.
Page 297: One-Pulse Mode
AT32F415 Series Reference Manual Figure 9- 109 6-step PWM Generation, Example of Using HALL (OSIMR = 1) Counter (CNT) (CCx) OCxREF Write HALL = 1 HALL event Write CxEN = 1 CxNEN = 0 OCxMODE = 100 CxEN = 1...
Page 298: Figure 9- 110 One-Pulse Mode Example
AT32F415 Series Reference Manual Figure 9- 110 One-pulse Mode Example OC1REF TMR1_AR Counter TMR1_CC1 DELAY PULSE For example, if users want to generate a positive pulse with a length of t on OC1 once a rising PULSE edge is detected on the TI2 input pin and after a delay t...
Page 299: Encoder Interface Mode
AT32F415 Series Reference Manual delay. In this case, OCxREF (and OCx) are forced to respond to the stimulus, instead of relying on the comparison result. The waveform outputted is the same as the one being compared and matched. OCxFEN acts only if the channel is configured as PWM1 or PWM2 mode.
Page 300: Timer Input Xor Function
AT32F415 Series Reference Manual  SMSEL = ‘011’ (TMRx_SMC register, all inputs are active on both rising and falling edges.)  CNTEN = ‘1’ (TMRx_CTRL1 register, counter enabled) Figure 9- 111 Example of Counter Operation in Encoder Interface Mode Figure 10-112 is an example of counter behavior when IC1FP1 polarity is inverted (the same configuration as the above example, except for C1P = ‘1’).
Page 301: Interfacing With Hall Sensors
AT32F415 Series Reference Manual 9.3.3.18 Interfacing with Hall Sensors When using the advanced-control timer (TMR1, TMR8, or TMR15) to generate PWM signal which drives the motor, another timer general-purpose timer TMRx (TMR2, TMR3, TMR4, orTMR5) can function as “interfacing timer” to connect Hall sensors. Please refer to Figure 10-113.
Page 302: Tmrx Timer And External Trigger Synchronization
AT32F415 Series Reference Manual Figure 9- 113 Example of HALL Sensor Interface Counter (CNT) (CC2) C7A3 C7A8 C794 C7A5 C7AB C796 TRGO = OC2REF HALL OCIN OC2N OC3N Write CxEN, CxNEN, and OCxMODE for the next step 9.3.3.19 TMRx Timer and External Trigger Synchronization The TMRx timer can be synchronized with an external trigger in several modes: reset mode, gated mode, and trigger mode.
Page 303: Figure 9- 114 Control Circuit In Reset Mode
AT32F415 Series Reference Manual  Configure the timer as reset mode by writing SMSEL = 100 in the TMRx_SMC register. Select TI1 as the input source by writing TRGSEL = 101 in the TMRx_SMC register.  Start the counter by writing CNTEN = 1 in the TMRx_CTRL1 register.
Page 304: Figure 9- 115 Control Circuit In Gated Mode
AT32F415 Series Reference Manual Figure 9- 115 Control Circuit in Gated Mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 35 36 37 38 TRGIF Write TRGIF = 0 Slave mode: Trigger mode The counter can be enabled according to the selected level of input.
Page 305: Timer Synchronization
AT32F415 Series Reference Manual In the following example, as soon as a rising edge of TI1 occurs, the counter counts up once at each rising edge of the ETR signal: 1. Configure the external trigger input circuit through the TMRx_SMC register: ─...
Page 306: Tmr1 Register Description
AT32F415 Series Reference Manual 9.3.4 TMR1 Register Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 9-11, TMR1, TMR8, and TMR15 registers are mapped to a 16-bit addressable space. Table 9- 11 TMR1, TMR8, and TMR15 –Register Table and Reset Values...
Page 307: Tmr1 Control Register 1 (Tmrx_Ctrl1)
AT32F415 Series Reference Manual Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_ CCM2 Input capture Reserved mode Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 308 AT32F415 Series Reference Manual CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency, dead-time, and sampling frequency used by the dead-time generator and digital filters (ETR, TIx). 00: �� = �� Bit 9:8 �� _�� 01: ��...
Page 309: Tmr1 Control Register 2 (Tmrx_Ctrl2)
AT32F415 Series Reference Manual 9.3.4.2 TMR1 Control Register 2 (TMRx_CTRL2) Address offset: 0x04 Reset value: 0x0000 TI1S erve MMSEL[2:0] erve Bit 15 Reserved. Always read as 0. OC4IS: Output idle state 4 (OC4 output). Please refer to the OC1IS bit.
Page 310: Tmr1 Slave Mode Control Register (Tmrx_Smc)
AT32F415 Series Reference Manual CUSEL: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CPC = 1), they are updated only by setting the HALL bit. Bit 2 1: When capture/compare control bits are preloaded (CPC = 1), they are updated by setting the HALL bit or a rising edge on TRGI.
Page 311: Tmr1 Dma/Interrupt Enable Register (Tmrx_Die)
AT32F415 Series Reference Manual MSMODE: Master/Slave mode 0: No effect Bit 7 1: The event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful when synchronizing several timers on a single external event.
Page 312: Tmr1 Status Register (Tmrx_Sts)
AT32F415 Series Reference Manual HALLDE: HALL DMA request enable Bit 13 0: HALL DMA request is disabled. 1: HALL DMA request is enabled. C4DE: Capture/Compare 4 DMA request enable Bit 12 0: Capture/Compare 4 DMA request is disabled. 1: Capture/Compare 4 DMA request is enabled.
Page 313 AT32F415 Series Reference Manual C4OF: Capture/Compare 4 overcapture flag Bit 12 Please refer to C1OF description. C3OF: Capture/Compare 3 overcapture flag Bit 11 Please refer to C1OF description. C2OF: Capture/Compare 2 overcapture flag Bit 10 Please refer to C1OF description.
Page 314 AT32F415 Series Reference Manual UEVIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update event occurs. 1: Update interrupt is pending. This bit is set by hardware when the registers are updated: −...
Page 315: Tmr1 Event Generation Register (Tmrx_Eveg)
AT32F415 Series Reference Manual 9.3.4.6 TMR1 Event Generation Register (TMRx_EVEG) Address offset: 0x14 Reset value: 0x0000 HALL Reserved Bit 15:8 Reserved. Always read as 0. BRKG: Break generation This bit is set by software to generate a break event. It is cleared automatically by hardware.
Page 316 AT32F415 Series Reference Manual channel is defined by the corresponding CxSEL bits. All the other bits of this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is in output mode, while ICxx describes its function when the channel is in input mode. Attention must be given to the fact that the same bit can have different definitions for the input stage and for the output stage.
Page 317 AT32F415 Series Reference Manual OC1PEN: Output compare 1 preload enable 0: Preload function of TMRx_CC1 is disabled. TMRx_CC1 can be written at any time, and the new value takes effect immediately. 1: Preload function of TMRx_CC1 is enabled. Read/Write operations only access the preload register.
Page 318: Tmr1 Capture/Compare Mode Register 2 (Tmrx_Ccm2)
AT32F415 Series Reference Manual ETDF[3:0]: External trigger filter The bits define the frequency used to sample ETRP signal and the length of ETRP digital filter. In fact, the digital filter is an event counter which records N consecutive events that...
Page 319: Tmr1 Capture/Compare Enable Register (Tmrx_Cce)
AT32F415 Series Reference Manual OC3DIS: Output compare 3 clear enable Bit 7 Bit 6:4 OC3MODE[2:0]: Output compare 3 mode Bit 3 OC3PEN: Output compare 3 preload enable Bit 2 OC3FEN: Output compare 3 fast enable C3SEL[1:0]: Capture/Compare 3 selection The bits define the channel direction (input/output), and input pin selection: 00: CC3 channel is configured as output.
Page 320 AT32F415 Series Reference Manual Bit 15:14 Reserved. Always read as 0. C4P: Capture/Compare 4 output polarity Bit 13 Please refer to C1P description. C4EN: Capture/Compare 4 output enable Bit 12 Please refer to C1OE description. C3NP: Capture/Compare 3 complementary output polarity Bit 11 Please refer to C1NP description.
Page 321: Table 9- 13 Complementary Output Channel Ocx And Ocxn Control Bits With Break Function
AT32F415 Series Reference Manual C1P: Capture/Compare 1 output polarity CC1 channel is configured as output: 0: OC1N is active high. 1: OC1N is active low. CC1 channel is configured as input: The CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity signal as trigger or capture signal.
Page 322: Tmr1 Counter (Tmrx_Cnt)
AT32F415 Series Reference Manual Output disabled (not driven by the timer) Asynchronously: OCx = CxP, OCx_EN = 0,CxN = CxNP, OCxN_EN = 0; If the clock is present: After a dead-time, OCx = OC1IS, OCxN = OCxNIS, assuming that OC1IS and OCxNIS do not correspond to OCx and OCxN active level.
Page 323: Tmr1 Repetition Counter Register (Tmrx_Rc)
AT32F415 Series Reference Manual AR[15:0]: Auto-reload value AR contains the value to be loaded to the actual auto-reload register. When auto-reload Bit 15:0 value is null, the counter does not work. Please refer to Section 9.3.3.1 for more details on AR update and behavior.
Page 324: Tmr1 Capture/Compare Register 3 (Tmrx_Cc3)
AT32F415 Series Reference Manual CC2[15:0]: Capture/Compare channel 2 value If CC2 channel is configured as output: CC2 is the value to be loaded in the actual capture/compare 2 register (preload value). The written value is loaded immediately to the active register if the preload feature is not selected in the TMRx_CCM2 register (the OC2PEN bit).
Page 325: Tmr1 Break And Dead-Time Register (Tmrx_Brkdt)
AT32F415 Series Reference Manual 9.3.4.18 TMR1 Break and Dead-time Register (TMRx_BRKDT) Address offset: 0x44 Reset value: 0x0000 DTGS[7:0] LOCKC[1:0] Note: The AOEN, BRKP, BRKEN, OSIMI, OSIMR, and DTGS[7:0] bits can be write- locked according to LOCK configuration. It is necessary to configure all of them during the first write access to the TMRx_BRKDT register.
Page 326: Tmr1 Dma Control Register (Tmrx_Dmac)
AT32F415 Series Reference Manual OSIMI: Off-state selection for Idle mode This bit is used when MOEN = 0 on channels configured as outputs. Please refer to OC/OCN enable description for more details (Section 9.3.4.9). 0: When the timer is inactive, OC/OCN outputs are disabled (OC/OCN enable output Bit 10 signal = 0).
Page 327: Tmr1 Dma Address In Burst Mode (Tmrx_Dmaba)
AT32F415 Series Reference Manual DBLEN[4:0]: DMA burst length The bits define the number of DMA transfers in burst mode (the timer recognizes a burst transfer when a read or a write access is done to the TMRx_DMABA register). Namely, defining the number of transfer, and the transfer can be half-word (two-byte) or byte:...
Page 328: Watchdog
AT32F415 Series Reference Manual 10 Watchdog 10.1 Window Watchdog (WWDG) 10.1.1 WWDG Introduction AT32F415 devices have two embedded watchdogs which provide a higher safety level, timing accuracy, and flexibilities. Both watchdog peripherals (independent watchdog and window watchdog) can detect and resolve malfunctions caused by software failures. When the counter reaches a given timeout value, they can trigger an interrupt (window watchdog only) or system reset.
Page 329 AT32F415 Series Reference Manual an MCU reset. The write operation can be done only when the counter value is less than the window register value. The value stored in the WWDG_CTRL register must fall between 0xFF and 0xC0:  Enable the watchdog.
Page 330: How To Program Watchdog Timeout
AT32F415 Series Reference Manual 10.1.4 How to Program Watchdog Timeout Figure 10-2 provides the formula to calculate the window watchdog timeout. Warning: When writing to the WWDG_CTRL register, always set the CNTR6 bit as ‘1’ to avoid an immediate reset.
Page 331: Register Description
AT32F415 Series Reference Manual 10.1.6 Register Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Table 10- 1 WW DG Register Map and Reset Values Offset Register WWDG_CT CNTR[6:0] 0x00 Reserved Reset Value 0 1 1 1 1 1 1 1...
Page 332: Status Register (Wwdg_Sts)
AT32F415 Series Reference Manual Reserved EWIEN PSC[1:0] WCNTR[6:0] Bit 31:8 Reserved. EWIEN: Early wakeup interrupt Bit 9 If this bit is set, an interrupt will be generated when the counter value reaches 40h. The interrupt can only be cleared by hardware after reset.
Page 333: Independent Watchdog (Iwdg)
AT32F415 Series Reference Manual 10.2 Independent Watchdog (IWDG) 10.2.1 Introduction The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. IWDG best suits the occasions which require the watchdog to run completely independent of the main application, and have lower timing accuracy requirements.
Page 334: Iwdg Register Description
AT32F415 Series Reference Manual Note: The watchdog is implemented in VDD power domain, which means that it can work normally in Stop mode and Standby mode. ( N o t e ) Table 10- 2 W atchdog Timeout Period (40 kHz Input Clock (LSI)) Min.
Page 335: Key Register (Iwdg_Key)
AT32F415 Series Reference Manual 10.2.4.1 Key Register (IWDG_KEY) Address offset: 0x00 Reset value: 0x0000 0000 (Reset by Standby mode) Reserved KEY[15:0] Bit 31:16 Reserved. Always read as 0. KEY[15:0]: Key value (Write-only, the value being read is 0x0000.) These bits must be written 0xAAAA by software at regular intervals; otherwise, a watchdog reset will be generated when the counter turns 0.
Page 336: Reload Register (Iwdg_Rld)
AT32F415 Series Reference Manual 10.2.4.3 Reload Register (IWDG_RLD) Address offset: 0x08 Reset value: 0x0000 0FFF (Reset by Standby mode) Reserved Reserved RLD[11:0] Bit 31:12 Reserved. Always read as 0. RLD[11:0]: Watchdog counter reload value These bits are write-protected, please refer to Section 10.2.3.2.
Page 337: Status Register (Iwdg_Sts)
AT32F415 Series Reference Manual 10.2.4.4 Status Register (IWDG_STS) Address offset: 0x0C Reset value: 0x0000 0000 (Not reset by Standby mode) Reserved Reserved RLDF PSCF Bit 31:2 Reserved. RLDF: Watchdog counter reload value update This bit is set by hardware to indicate that the reload value update is in process.
Page 338: Real-Time Clock (Ertc)
AT32F415 Series Reference Manual 11 Real-time Clock (ERTC) 11.1 Introduction Real-time clock (ERTC) is an independent BCD timer/counter. ERTC provides one calendar clock, two programmable clock interrupt, and a periodic programmable wakeup flag with interrupt function. ERTC also contains automatic wakeup unit for low-power mode management.
Page 339: Ertc Function Overview
AT32F415 Series Reference Manual This output can map to device ERTC_AF1 function.  ERTC_ALARM (alarm clock A, alarm clock B, or wakeup); this output can be selected by setting the ERTC_CTRL register, OSEL[1:0]. This output can map to device ERTC_AF1 function.
Page 340: Real-Time Clock And Calendar
AT32F415 Series Reference Manual higher value to maximally lower power consumption. To obtain internal clock (ck_spre) with frequency of 1 Hz by using LSE with frequency of 32.768 kHz, the asynchronous prescaler ratio should be set to 128, and the synchronous prescaler ratio should be set to 256.
Page 341: Periodic Auto-Wakeup
AT32F415 Series Reference Manual connect to the ERTC_ALARM output. ERTC_ALARM polarity can be configured by the OPOL bit in the ERTC_CTRL register. Note: If second field is selected (the MASK1 bit in the ERTC_ALA or ERTC_ALB is reset), then the synchronous prescaler ratio set in the ERTC_PSC register must be 3 at least, to ensure that the alarm clock correctly operates.
Page 342 AT32F415 Series Reference Manual prescaler configuration, please follow the steps below: 1. Set the INITM bit in the ERTC_STS register to enter initialization mode. In this mode, calendar counter will stop working, and its value can be updated. 2. Poll the INITF bit in the ERTC_STS register. Enter initialization stage mode when the INITF bit is set.
Page 343: Read The Calendar
AT32F415 Series Reference Manual 11.3.6 Read the Calendar When the BYPSHDW control bit in the ERTC_CTRL register is cleared. To correctly read the ERTC calendar register (ERTC_SBSR, ERTC_TIME, and ERTC_DATE), APB1 clock frequency (fPCLK1) must be equal to or higher than the 7 times of the fERTCCLK ERTC clock frequency, which can ensure the safety of synchronous mechanism.
Page 344: Reset Ertc
AT32F415 Series Reference Manual 11.3.7 Reset ERTC Some bits of the calendar shadow register (ERTC_SBSR, ERTC_TIME, and ERTC_DATE) and ERTC status register (ERTC_STS) are reset to their default values through all available system reset sources. On the contrary, the following registers are reset to their default values through power-on...
Page 345: Ertc Coarse Digital Calibration
AT32F415 Series Reference Manual ERTC uses 32.768-kHz oscillator generated 256-Hz clock (ck_apre) to detect whether reference clock source exists. Every time when the calendar is updated, Every time when the calendar is updated (every 1 second), a detection is performed during the time window. When the first reference clock edge is detected, the window is equal to 7 ck_apre cycles.
Page 346: Ertc Fine Digital Calibration
AT32F415 Series Reference Manual For example, when DCAL is 1, only the first two minutes can be modified. This means that, if every ck_apre cycle means 128 ERTCCLK cycles (calculated by PRDIV_A + 1 = 128), then for every first 2xDCAL minutes of the 64-minute cycle, 256 ERTCCLK cycle will be decreased or 128 ERTCCLK cycles will be added within a second in every minute.
Page 347: Time Stamp Function
AT32F415 Series Reference Manual Under this circumstance, if ERTCCLK is right 32768.00 Hz, then when CALM[7:0] is 0x100 (the middle value of CALM range), the configuration is correct. Verify ERTC calibration By measuring the accurate frequency of ERTC CLK, CALM and CALAD values can be correctly calculated to realize ERTC resolution.
Page 348: Tamper Detection
AT32F415 Series Reference Manual write 0 to the TSF bit unless the TSF bit is already read as ‘1’. Besides, tamper events cause time stamp to be recorded. For TMTS control bit description, please refer to Section 23.6.17. If time stamp event uses the same pin with the tamper event configured to filter mode (TMFLT is not set to 0), the time stamp mode of tamper detection event should be selected by setting the TMTS bit in the ERTC_TPAF register.
Page 349: Calibration Clock Output
AT32F415 Series Reference Manual consecutive samples occur on the level specified by the TAMPxTRG bit (TM1TRG/TAMP2TRG). Unless tamper input is disabled by setting the TMPUDIS bit, the input will be precharged by I/O internal pull-up resistor before tamper input status is sampled. How long the time of precharge lasts depends on the TMPRCH bit, which allows to increase the capacitance on the tamper input.
Page 350: Ertc Interrupt
AT32F415 Series Reference Manual 11.5 ERTC Interrupt All ERTC interrupts are connected to the EXTI controller. To enable ERTC alarm clock interrupt, the sequence below should be followed: 1. Set the EXTI line 17 configuration to interrupt mode, then enable the interrupt, and select rising edge effective.
Page 351: Ertc Register
AT32F415 Series Reference Manual 11.6 ERTC Register 11.6.1 ERTC Time Register (ERTC_TIME) ERTC_TIME is the calendar time shadow register; write access to this register can only be done in initialization mode. Please refer to Section 11.3.5. Offset: 0x00 Power-on reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHDW = 0;...
Page 352: Ertc Date Register (Ertc_Date)
AT32F415 Series Reference Manual 11.6.2 ERTC Date Register (ERTC_DATE) ERTC_DATE is the calendar date shadow register; write access to this register can only be done in initialization mode. Please refer to Section 11.3.5. Offset: 0x04 Power-on reset value: 0x0000 2101 System reset: 0x0000 2101 when BYPSHDW = 0;...
Page 353 AT32F415 Series Reference Manual This bit configures the ERTC_ALARM output polarity. 0: When ALAF/ALBF/WATF is set (depends on OSEL[1:0]), the pin is high level. 1: When ALAF/ALBF/WATF is set (depends on OSEL[1:0]), the pin is low level. Bit 19 CALSEL: Calibration Output Selection When CALOE = 1, this bit selects the output signal on ERTC_CAL.
Page 354: Ertc Initialization And Status Register (Ertc_Sts)
AT32F415 Series Reference Manual Bit 2:0 WACKSEL[2:0]: Wakeup clock select 000: Select ERTC/16 clock 001: Select ERTC/8 clock 010: Select ERTC/4 clock 011: Select ERTC/2 clock 10x: Select ck_spre clock (usually 1 Hz ) 11x: Select ck_spre clock (usually 1 Hz) and increase the WAREV counter value by 216 (Please refer to the following notes.)
Page 355: Ertc Prescaler Register (Ertc_Psc)
AT32F415 Series Reference Manual Bit 8 ALAF: alarm clock A flag When time/date register (ERTC_TIME and ERTC_DATE) matches the alarm clock A register (ERTC_ALA), this flag will be set by hardware. It is cleared by software. Bit 7 INITM: Initialization mode 0: Free-running mode 1: Initialization mode;...
Page 356: Ertc Wakeup Timer Register (Ertc_Watr)
AT32F415 Series Reference Manual Asynchronous prescaler ratio equation is as follows: ck_apre frequency = ERTCCLK frequency/(PRDIV_A+1) Note: PRDIV_A [6:0] = 000000 is a forbidden value. Bit 15 Reserved; must be kept as reset value. Bit 14:0 PRDIV_S[14:0]: Synchronous prescaler ratio...
Page 357: Ertc Alarm Clock A Register (Ertc_Ala)
AT32F415 Series Reference Manual 00010: + 8 ppm (Rounded) 11111: + 126 ppm (Rounded) DCALS = 1 (Negative calibration) 00000: - 0 ppm 00001: - 2 ppm (Rounded) 00010: - 4 ppm (Rounded) 11111: - 63 ppm (Rounded) For more detailed values, please refer to Section 17.3.10, “When ERTCCLK = 32.768 kHz and PRDIV_A+1 = 128.
Page 358: Ertc Alarm Clock B Register (Ertc_Alb)
AT32F415 Series Reference Manual 11.6.9 ERTC Alarm Clock B Register (ERTC_ALB) Offset: 0x20 Power-on reset value: 0x0000 0000 System reset: Not affected MASK4 WKSEL DT[1:0] DU[3:0] MASK3 AMPM HT[1:0] HU[3:0] MASK2 MT[2:0] MU[3:0] MSK1 ST[2:0] SU[3:0] Bit 31 MASK4: alarm clock A DATE mask 0: If date matches day, alarm clock A is set.
Page 359: Ertc Sub-Second Register (Ertc_Sbsr)
AT32F415 Series Reference Manual 11.6.11 ERTC Sub-second Register (ERTC_SBSR) Offset: 0x28 Power-on reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHDW =0; no affected when BYPSHDW = 1. SBS[15:0] Bit 31:16 Reserved Bit 15:0 SBS: Sub-second value SBS[15:0] is the value of synchronous prescaler counter.
Page 360: Ertc Time Stamp Time Register (Ertc_Tstm)
AT32F415 Series Reference Manual 11.6.13 ERTC Time Stamp Time Register (ERTC_TSTM) Offset: 0x30AM Power-on reset value: 0x0000 0000 System reset: Not affected AMPM HT[1:0] HU[3:0] MT[2:0] MU[3:0] ST[2:0] SU[3:0] Bit 31:23 Reserved; must be kept as reset value. Bit 22...
Page 361: Ertc Time Stamp Sub-Second Register (Ertc_Tssbs)
AT32F415 Series Reference Manual 11.6.15 ERTC Time Stamp Sub-second Register (ERTC_TSSBS) Offset: 0x38 Power-on reset value: 0x0000 0000 System reset: Not affected SBS[15:0] Bit 31:16 Reserved Bit 15:0 SBS: Sub-second value When time stamp event occurs, SBS[15:0] is the value of the synchronous prescaler counter.
Page 362: Ertc Tamper And Alternate Function Configuration Register (Ertc_Tpaf)
AT32F415 Series Reference Manual 11.6.17 ERTC Tamper and Alternate Function Configuration Register (ERTC_TPAF) Address offset: 0x40 Power-on reset value: 0x0000 0000 System reset: Not affected ALAOUTTY TMPUDI TMPRCH[1: TMFLT[1: TMFREQ[2:0] TMIE TM1TR Bit 31:19 Reserved Bit 18 ALAOUTTYPE: ERTC_ALARM output type 0: ERTC_ALARM is open-drain output.
Page 363: Ertc Alarm Clock A Sub-Second Register (Ertc_Alasbs)
AT32F415 Series Reference Manual If TMFLT = 00: 0: TAMPER1 rising edge will trigger tamper detection event. 1: TAMPER1 falling edge will trigger tamper detection event. Note: If TMFLT = 0, then the TM1E bit must be reset when changing TM1TRG, to avoid accidentally setting the TPF bit.
Page 364: Ertc Backup Register (Ertc_Bkpxdt)
AT32F415 Series Reference Manual Mask the highest effective bit starting from this bit 0: Do not compare sub-second in alarm clock A. When second unit increases, configure the alarm clock (assuming that other fields all match.) 1: Compare in alarm clock B, SBS[14:1] are “don’t care”, only SBS [0] is compared.
Page 365: Analog-To-Digital Converter (Adc)
AT32F415 Series Reference Manual 12 Analog-to-Digital Converter (ADC) 12.1 ADC Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has 23 channels to measure the 21 external and 2 internal signal sources. The analog signal of each channel can be converted by the ADC in single, continuous, scan, or discontinuous mode.
Page 366: Table 12- 1 Adc Pins
AT32F415 Series Reference Manual Interrupt enable bits End of conversion Flag bits ADC interrupt to NVIC ECIEN End of injected conversion JECIEN AWDIEN Analog watchdog Analog watchdog Compare result event High threshold (12 bits) Low threshold (12 bits) Injected data register （4*16 bits）...
Page 367: Adc Switch
AT32F415 Series Reference Manual 12.3.1 ADC Switch Setting the ADON bit in the ADC_CTRL2 register can activate the ADC. When setting the ADON bit for the first time, it will wake up the ADC from power-down mode. Conversion starts when ADON bit is set for the second time after ADC power-on delay time ( STAB Clearing the ADON bit can stop conversion and put the ADC in power-down mode.
Page 368: Continuous Conversion Mode
AT32F415 Series Reference Manual 12.3.5 Continuous Conversion Mode In continuous conversion mode, the ADC starts another conversion as soon as it finishes the previous one. This mode is started either by external trigger or by setting the ADON bit in the ADC_CTRL2 register.
Page 369: Scan Mode
AT32F415 Series Reference Manual Figure 12- 3 Analog W atchdog Guarded Area Table 12- 2 Analog W atchdog Channel Selection ADC_CTRL1 Register Control Bits Channels to be guarded by analog watchdog AWDSGE bit AWDEN bit JAWDEN bit None Any value...
Page 370: Discontinuous Mode
AT32F415 Series Reference Manual shows the timing diagram. Note: When using triggered injection, the interval between trigger events must be longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is, two conversions with a 1.5 clock-period sampling time), the minimum interval between triggers must be 29 ADC clock cycles.
Page 371: Calibration
AT32F415 Series Reference Manual First trigger: The converted sequence are 0, 1, and 2. An EC event is generated. Second trigger: The converted sequence are 3, 6, and 7. An EC event is generated. Third trigger: The converted sequence are 9 and 10. An EC event is generated.
Page 372: Data Alignment
AT32F415 Series Reference Manual Figure 12- 5 Calibration Timing Diagram Calibration flag cleared by Calibration ongoing hardware Normal ADC conversion conversion 12.3.12 Data Alignment The DALIGN bit in the ADC_CTRL2 register selects the alignment of data stored after conversion. Data can be left-aligned or right-aligned, as shown in...
Page 373: Table 12- 3 Adc1 And Adc2 Used In External Trigger For Regular Channels
AT32F415 Series Reference Manual Note: When an external trigger signal is selected for ADC regular or injected conversion, only its rising edge can start the conversion. Table 12- 3 ADC1 and ADC2 Used in External Trigger for Regular Channels Source...
Page 374: Dma Request
AT32F415 Series Reference Manual 12.3.15 DMA Request Since the converted values of regular channels are stored in the only one data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data which is already stored in the ADC_RDOR register.
Page 375: Adc Interrupts
AT32F415 Series Reference Manual Avg_Slope = Average slope for curve between temperature and V (given in mV/° C or SENSE μV/° C) Please refer to the section of electrical characteristics in the data sheet for the actual values of and Avg_Slope.
Page 376 AT32F415 Series Reference Manual Offset Register ADC_SMPT1 00Ch Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPT2 010h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFS1 JOFST1[11：0]...
Page 377: Adc Status Register (Adc_Sts)
AT32F415 Series Reference Manual 12.4.1 ADC Status Register (ADC_STS) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved RSTR JSTR rc w0 rc w0 rc w0 rc w0 rc w0 Bit 31:15 Reserved. Must be kept as 0. RSTR: Regular channel Start flag...
Page 378 AT32F415 Series Reference Manual AWDEN: Analog watchdog enable on regular channels This bit is set and cleared by software. Bit 23 0: Analog watchdog is disabled on regular channel. 1: Analog watchdog is enabled on regular channel. JAWDEN: Analog watchdog enable on injected channels This bit is set and cleared by software.
Page 379 AT32F415 Series Reference Manual ECIEN: Interrupt enable for EC This bit is set and cleared by software to enable or disable interrupt generation after conversion. Bit 5 0: EC interrupt is disabled. 1: EC interrupt is enabled. An interrupt is generated when the EC bit is set by hardware.
Page 380: Adc Control Register 2 (Adc_Ctrl2)
AT32F415 Series Reference Manual 12.4.3 ADC Control Register 2 (ADC_CTRL2) Address offset: 0x08 Reset value: 0x0000 0000 EXSE JEXSE JSWS EXTT EXSE Reserved Reserved L[3] L[3] L[2:0] DALI JEXT TRIG JEXSEL[2:0] Reserved Reserved RST CAL ADON Bit 31:24 Reserved. Must be kept as 0.
Page 381 AT32F415 Series Reference Manual EXSEL[3:0]: External event select for regular group These bits select the external event that starts regular channel group conversion. Trigger configurations for ADC1 and ADC2 are as follows: 0000: Timer 1 CC1 event 0001: Timer 1 CC2 event...
Page 382 AT32F415 Series Reference Manual JEXSEL[3:0] : External event select for injected group These bits select the external event that starts injected channel group conversion. Trigger configurations for ADC1 and ADC2 are as follows: 0000: Timer 1 TRGO event 0001: Timer 1 CC4 event...
Page 383: Adc Sample Time Register 1 (Adc_Smpt1)
AT32F415 Series Reference Manual CON: Continuous conversion This bit is set and cleared by software. If this bit is set, conversion will be Bit 1 continuously performed until this bit is cleared. 0: Single conversion mode 1: Continuous conversion mode ADON: A/D converter ON/OFF This bit is set and cleared by software.
Page 384: Adc Injected Channel Data Offset Register X (Adc_Jofsx) (X = 1
AT32F415 Series Reference Manual SMPx[2:0]: Channel x Sample time selection These bits select the sample time for each channel individually. During sample cycles, channel selection bits must remain unchanged. 000: 1.5 cycles 100: 41.5 cycles Bit 29:0 001: 7.5 cycles 101: 55.5 cycles...
Page 385: Adc Watchdog Low Threshold Register (Adc_Wltr)
AT32F415 Series Reference Manual 12.4.8 ADC Watchdog Low Threshold Register (ADC_WLTR) Address offset: 0x28 Reset value: 0x0000 0000 Reserved Reserved AWLT[11:0] Bit 31:12 Reserved. Must be kept as 0. AWLT[11:0]: Analog watchdog low threshold Bit 11:0 These bits define the low threshold for analog watchdog.
Page 386: Adc Regular Sequence Register 3 (Adc_Rsq3)
AT32F415 Series Reference Manual SQ10[0] SQ9[4:0] SQ8[4:0] SQ7[4:0] Bit 31:30 Reserved. Must be kept as 0. SQ12[4:0]: 12th conversion in regular sequence Bit 29:25 These bits are set by software to define the channel number (0 ~ 17) of the 12th conversion in the sequence.
Page 387: Adc Injected Sequence Register (Adc_Jsq)
AT32F415 Series Reference Manual 12.4.12 ADC Injected Sequence Register (ADC_JSQ) Address offset: 0x38 Reset value: 0x0000 0000 Reserved JLEN[3:0] JSQ4[4:0] JSQ4[0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bit 31:22 Reserved. Must be kept as 0. JLEN[1:0]: Injected sequence length These bits are set by software to define the total number of conversions in the injected channel conversion sequence.
Page 388: Adc Regular Data Register (Adc_Rdor)
AT32F415 Series Reference Manual 12.4.14 ADC Regular Data Register (ADC_RDOR) Address offset: 0x4C Reset value: 0x0000 0000 Reserved D[15:0] Bit 31:16 Reserved. D[15:0]: Regular data These bits are read only. They contain the conversion result of the regular Bit 15:0 channels.
Page 389: C Interface
AT32F415 Series Reference Manual 13 I C Interface 13.1 I C Introduction C (inter-integrated circuit) bus interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability and controls all I C bus-specific sequencing, protocol, arbitration, and timing.
Page 390: C Function Overview
AT32F415 Series Reference Manual 13.3 I C Function Overview C module receives and transmits data, and converts data from serial to parallel format, and vice versa. Interrupts can be enabled or disabled. The interface is connected to the I C bus through a data pin (SDA) and a clock pin (SCL).
Page 391: C Slave Mode
AT32F415 Series Reference Manual Figure 13- 2 Block Diagram of I C Function Data register Data control Data shift register Comparator PEC calculation Own address register Dual address register PEC register Clock control Clock control register (CLKCTRL) Control registers (CTRL1＆CTRL2)
Page 392: Figure 13- 3 Transfer Sequence Diagram Of Slave Transmitter
AT32F415 Series Reference Manual Header matched (10-bit mode only): If the ACKEN bit is set, the I C interface generates an acknowledge pulse and waits for the 8-bit slave address. Address matched: The I C interface generates the following sequence: ●...
Page 393: C Master Mode
AT32F415 Series Reference Manual Figure 13- 4 Transfer Sequence Diagram of Slave Receiver 7-bit slave receiver Address Data 1 Data 2 Data N …… 10-bit slave receiver Header Address Data 1 Data N …… Description：S = Start (Start condition), Sr = Repeated start condition, P = Stop (Stop condition), A = Acknowledge, NA = Non acknowledge, Evx = Event (Interrupt generated when EVTITEN = 1) EV1: ADDRF = 1, read STS1 and then STS2 to clear the event.
Page 394 AT32F415 Series Reference Manual set. Then, the master waits for a read to the STS1 register, followed by writing the slave address into the DT register (Please refer to EV5 in Figure 13-5 Figure 13-6). Slave address transmission The slave address is sent to the SDA line via the internal shift register.
Page 395: Figure 13- 5 Transfer Sequence Diagram Of Master Transmitter
AT32F415 Series Reference Manual (the MSF bit is cleared). Note: Stop condition should be programmed during EV8_2 event when either the TDE bit or the BTFF bit is set. Figure 13- 5 Transfer Sequence Diagram of Master Transmitter 7-bit master transmitter...
Page 396: Figure 13- 6 Transfer Sequence Diagram Of Master Receiver
AT32F415 Series Reference Manual Figure 13- 6 Transfer Sequence Diagram of Master Receiver 7-bit master receiver Address Data 1 Data 2 Data N ⑴ …… EV6 EV6_1 EV7_1 10-bit master receiver Header Address Address Data 1 Data 2 Data N ⑴...
Page 397: Figure 13- 8 Transfer Sequence Diagram For Master Receiver When N = 2
AT32F415 Series Reference Manual ● Read data N-2, and the bus starts receiving data N ● Data N received, and respond to NACK ● Set the STARTGEN/STOPGEN bit ● RDNE = 1 ● Read data N Case 3: I C interrupt is not set as the highest priority, and the total number of bytes received is 2 or 1, N = 2 or N = 1 ●...
Page 398: Error Condition
AT32F415 Series Reference Manual Figure 13- 9 Transfer Sequence Diagram for Master Receiver when N = 1 7-bit master receiver Address Data 1 EV6_3 10-bit master receiver Header Address header Data 1 EV6_3 Description：S = Start (Start condition), Sr = Repeated start condition, P = Stop (Stop condition), A = Acknowledge, NA = Non acknowledge, Evx = Event (Interrupt generated when EVTITEN = 1) EV5：STARTF = 1, read STS1 and then write the address to the DT register to clear the event.
Page 399: Sda/Scl Line Control
AT32F415 Series Reference Manual transmit the last received byte. In slave mode, an underrun error occurs if clock stretching is disabled, the I C interface is transmitting data, but before the clock of the next byte arrives, new data is not yet written into the DT register (TDE = 1).
Page 400 AT32F415 Series Reference Manual 35 ms clock low timeout No clock timeout Fixed logic levels -dependent logic levels Different address types (reserved, dynamic, etc.) 7-bit, 10-bit, and general call slave address types Different bus protocols (quick command, process call, etc.)
Page 401: Dma Request
AT32F415 Series Reference Manual For more details on SMBus Alert mode, please refer to SMBus specification version 2.0. standard http://smbus.org/specs/ Timeout error In the timing specifications, there are several differences between I C and SMBus. SMBus defines a clock low timeout, TIMEOUT of 35 ms. SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device.
Page 402: Packet Error Checking (Pec)
AT32F415 Series Reference Manual sends an End of Transfer signal, EOT/EOT_1, to the I C interface. A DMA interrupt will be generated if enabled. Note: Do not set the BUFITEN bit in the I2C_CTRL2 register if DMA is used for transmission.
Page 403: C Interrupt Request
AT32F415 Series Reference Manual 13.3.9 I C Interrupt Request Table 13-2 lists all the I C interrupt request. Table 13- 2 I C Interrupt Request Interrupt Event Event Flag Enable Control Bit Start bit sent (Master) STARTF Address sent (Master) or Address matched (Slave)
Page 404: C Debug Mode
AT32F415 Series Reference Manual Figure 13- 10 I C Interrupt Mapping Diagram EVTITEN STARTF ADDRF ADD10F STOPF it_event BTFF Event interrupt BUFITEN RDNE ERRITEN BUSERR ARLOST ACKFAIL it_error OVRUN Error interrupt PECERR TIMOUT SMBALERTF 13.3.10 I C Debug Mode ®...
Page 405: Control Register
AT32F415 Series Reference Manual Reset Value 0 0 0 0 0 0 0 0 0 0 0 I2C_CTRL2 CLKFREQ[7：0] 004h Reserved Reserve Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_OADDR ADDR[7：1] 008h...
Page 406 AT32F415 Series Reference Manual SWRESET: Software reset When set, I C is under reset state. Before resetting this bit, ensure that I C pins are released, and the bus is free. Bit 15 0: I C peripheral is not at reset state.
Page 407: Control Register
AT32F415 Series Reference Manual NOCLKSTRETCH: Clock stretching disable (Slave mode) This bit is used to disable clock stretching in slave mode when ADDRF or BTFF flag is Bit 7 set, until it is reset by software. 0: Clock stretching is enabled.
Page 408: C_Oaddr1)
AT32F415 Series Reference Manual DMAEN: DMA requests enable Bit 11 0: DMA request is disabled. 1: DMA request is enabled when TDE = 1 or RDNE = 1. BUFITEN: Buffer interrupt enable 0: No interrupt is generated when TDE = 1 or RDNE = 1.
Page 409: C_Oaddr2)
AT32F415 Series Reference Manual ADDR0: Interface address Bit 0 Not attended in 7-bit addressing mode. The 0 bit of the address in 10-bit addressing mode. 13.4.4 Own Address Register 2 (I C_OADDR2) Address offset: 0x0C Reset value: 0x0000 Reserved ADDR2[7:1] DUALEN Reserved.
Page 410 AT32F415 Series Reference Manual SMBALERTF: SMBus alert In SMBus host mode: 0: No SMBus alert 1: SMBALERTF event occurs on the pin. Bit 15 In SMBus slave mode: 0: No SMBAlert response address header. 1: SMBAlert response address header to SMBAlert LOW received.
Page 411 AT32F415 Series Reference Manual TDE: Data register empty (Transmitters) 0: Data register is not empty. 1: Data register is empty. – Set when the data register is empty in transmission. This bit is not set at address transmission phase. –...
Page 412: Status Register 2 (I C_Sts2)
AT32F415 Series Reference Manual ADDRF: Address sent (Master mode)/matched (Slave mode) This bit is cleared by read access to the STS2 register after software reads the STS1 register. Address matched (Slave mode) 0: Address is mismatched or not received. 1: Received address is matched.
Page 413: Clock Control Register
AT32F415 Series Reference Manual TRF: Transmitter/receiver 0: Data is received. 1: Data is transmitted. At the end of the whole address transmission phase, this bit is Bit 2 set depending on the R/W bit of the address byte. It is cleared by hardware after detection of Stop condition (STOPF = 1), repeated Start condition, bus arbitration lost (ARLOST = 1), or when PEN = 0.
Page 414: Tmrise Register (I C_Tmrise)
AT32F415 Series Reference Manual CLKCTRL[11:0] : Clock control register in Fast/Standard mode (Master mode) The divider ratio sets the SCL clock in master mode. In slave mode, it does not need to be configured, or is the same as the one in master mode according to the equation.
Page 415: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32F415 Series Reference Manual 14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 14.1 USART Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means to realize full-duplex data exchange with external devices which require industry standard NRZ asynchronous serial data format. With a fractional baud rate generator, the USART offers a very wide range of baud rates.
Page 416: Usart Function Overview
AT32F415 Series Reference Manual ─ Noise error ─ Framing error ─ Parity error ● 10 interrupt sources with flags ─ CTSF changes ─ LIN break detection ─ Transmit data register empty ─ Transmission completed ─ Receive data register full ─ Idle line detected ─...
Page 417: Usart Feature Description
AT32F415 Series Reference Manual The following pins are required in hardware flow control mode: ● CTS: Cleared after reception. If it is low level, the next data transmission will occur after the current transmission ends. If it is high level, the next data transmission will be stopped by the end of current data transmission.
Page 418: Transmitter
AT32F415 Series Reference Manual Figure 14- 2 W ord Length Programming 9-bit word length (The LEN bit is set), 1 stop bit Next data frame Possible Data frame Next parity bit Start start Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8...
Page 419: Configurable Stop Bit
AT32F415 Series Reference Manual 2. After the TEN bit is enabled, the USART will automatically send an idle frame. 14.3.2.2 Configurable Stop Bit The number of stop bits transmitted by each character can be programmed by the bits 13 and 12 in the control register 2 (USART_CTRL2).
Page 420: Single Byte Communication
AT32F415 Series Reference Manual 7. Write the data to be sent in the USART_DT register (which clears the TDE bit). Repeat this step to each data to be transmitted in single buffer cases. 8. After writing the last data into the USART_DT register, wait until TRAC = 1. This indicates the end of the last frame transmission.
Page 421: Idle Character
AT32F415 Series Reference Manual completed (during the stop bit of the break frame). The USART inserts a logic ‘1’ at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Note: If the software resets the SBRK bit before the break frame transmission, the break frame will not be transmitted.
Page 422: Character Reception
AT32F415 Series Reference Manual 14.3.3.2 Character Reception During a USART transmission, the least significant bits of data are shifted in first from the Rx pin. In this mode, the USART_DT register includes a buffer between the internal APB bus and the receive shift register.
Page 423: Table 14- 1 Sampled Data From Noise Detection
AT32F415 Series Reference Manual ● The ORERR bit is reset by reading the USART_STS and then the USART_DT registers in order. Note: When the ORERR bit is set, it indicates that at least 1 data is lost. There are two possibilities: ●...
Page 424: Framing Error
AT32F415 Series Reference Manual 14.3.3.6 Framing Error A framing error is detected when: The stop bit is not recognized on reception at the expected time because of data desynchronization or excessive noise. When a framing error is detected: ● The FERR bit is set by hardware.
Page 425: How To Derive Usartdiv From Usart_ Baudr Register Values
AT32F415 Series Reference Manual 14.3.4.1 How to Derive USARTDIV from USART_ BAUDR Register Values Example 1: If DIV_Integer = 27, DIV_Decimal = 12 (USART_BAUDR = 0x1BC), then DIV_Integer (USARTDIV) = 27 DIV_Decimal (USARTDIV) = 12/16 = 0.75 Therefore, USARTDIV = 27.75 Example 2: To program USARTDIV = 25.62, it leads to:...
Page 426: Usart Receiver's Tolerance To Clock Deviation
AT32F415 Series Reference Manual 14.3.5 USART Receiver’s Tolerance to Clock Deviation The USART asynchronous receiver can work normally only if the whole clock system deviation is within the range of the USART receiver tolerance. The factors that contribute to the deviation include: ●...
Page 427: Idle Line Detection (Wumode = 0)
AT32F415 Series Reference Manual 14.3.6.1 Idle Line Detection (WUMODE = 0) The USART enters mute mode when the RECMUTE bit is written to 1. It wakes up when an idle frame is detected. Then, the RECMUTE bit is cleared by hardware, but the IDLEF bit is not set in the USART_STS register.
Page 428: Lin (Local Interconnection Network) Mode
AT32F415 Series Reference Manual Table 14- 5 Frame Format LEN bit PCEN bit USART Frame | Start bit | 8-bit data | Stop bit | | Start bit | 7-bit data | Parity bit | Stop bit | | Start bit | 9-bit data | Stop bit |...
Page 429: Figure 14- 9 Break Detection In Lin Mode (11-Bit Break Length - The Lbdlen Bit Is Set)
AT32F415 Series Reference Manual If a ‘1’ is sampled before the 10th or 11th sample, the break detection circuit cancels the current detection and searches for a start bit again. If LIN mode is disabled (LINEN = 1), the receiver continues working as normal USART, without detecting the break.
Page 430: Usart Synchronous Mode
AT32F415 Series Reference Manual Figure 14- 10 Break Detection and Framing Error Detection in LIN Mode In the following examples, assume that LBDLEN = 1( break length is 11 bits), LEN = 0 (8-bit data) Case 1：Break after idle RX line...
Page 431: Figure 14- 11 Example Of Usart Synchronous Transmission
AT32F415 Series Reference Manual Figure 14- 11 Example of USART Synchronous Transmission Input data Output data Synchronous device USART (i.e. Slave SPI ) Figure 14- 12 Example of USART Data Clock Timing (LEN = 0) Idle or the last Idle or the next...
Page 432: Single-Wire Half-Duplex Communication
AT32F415 Series Reference Manual Figure 14- 13 Example of USART Data Clock Timing (LEN = 1) Idle or the last Idle or the next LEN = 1 (9 data bits) Start Stop transmission transmission Clock (CLKPOL = 0, CLKPHA = 0)
Page 433: Smartcard
AT32F415 Series Reference Manual a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware; that is, the USART cannot receive data when it is at transmission state. Namely, in half-duplex mode, transmission has higher priority over reception, and the conflicts between them should be handled by software.
Page 434: Figure 14- 16 Parity Error Detection Using 1.5 Stop Bits
AT32F415 Series Reference Manual ● The assertion of the TRAC flag can be delayed by programming the guard time register (GTVAL). In normal operation, TRAC is asserted when the transmit shift register is empty and no further transmit requests occur. In Smartcard mode, an empty transmit shift register triggers the guard time counter to count up to the programmed value in the guard time register (GTVAL).
Page 435: Irda Sir Endec Block
AT32F415 Series Reference Manual 14.3.12 IrDA SIR ENDEC Block The IrDA mode is selected by setting the IRDAEN bit in the USART_CTRL3 register. In IrDA mode, the following bits must be kept cleared: ● LINEN, STOPB, and CLKEN in the USART_CTRL2 register ●...
Page 436: Continuous Communication Using Dma
AT32F415 Series Reference Manual Figure 14- 17 IrDA SIR ENDEC Block Diagram USART_TX IrDA_OUT Transmit encoder SIREN USART Receive IrDA_IN encoder USART_RX Figure 14- 18 IrDA Data Modulation (3/16) - Normal Mode 3/16 14.3.13 Continuous Communication Using DMA The USART is capable of continuing communication by using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently.
Page 437: Reception Using Dma
AT32F415 Series Reference Manual finishes all the data to be transmitted, the TCIF flag is set in the DMA_ISTS register by the DMA controller. The TRAC flag can be monitored to ensure that the USART communication is completed. This avoids corrupting the last transmission before disabling the USART or entering the Stop mode.
Page 438: Error Flag And Interrupt Generation In Multi-Buffer Communication
AT32F415 Series Reference Manual 14.3.13.3 Error Flag and Interrupt Generation in Multi-buffer Communication In multi-buffer communication, if any error occurs during the communication, the error flag will be asserted after the current byte transmission. An interrupt will be generated if the interrupt enable bit is set.
Page 439: Cts Flow Control
AT32F415 Series Reference Manual 14.3.14.2 CTS Flow Control If the CTS flow control is enabled (CTSEN = 1), then the transmitter checks the CTS input before transmitting the next frame. If CTS is asserted (tied low), then the next data is transmitted (assuming that the data is ready to be transmitted, in other words, if TDE = 0);...
Page 440: Usart Mode Configuration
AT32F415 Series Reference Manual Figure 14- 24 USART Interrupt Mapping Diagram TRAC TRACIEN TDEIEN CTSEN CTSIEN interrupt IDLEF IDLEIEN RDNEIEN ORERR RDNEIEN RDNE PERRIEN PERR LBDF LBDIEN FERR NERR ERRIEN ORERR DMAREN 14.5 USART Mode Configuration Table 14- 7 USART Mode Configuration...
Page 441: Status Register (Usart_Sts)
AT32F415 Series Reference Manual DIV_Decimal DIV_Integer[11：0] USART_BAUDR 保留 [3：0] 0x08 0x0000 USART_CTRL1 0x0C Reserved 0x0000 STOPB USART_CTRL2 ADDR[3：0] [1：0] 0x10 Reserved 0x0000 USART_CTRL3 0x14 Reserved 0x0000 GTVAL[7：0] DIV[7：0] USART_GTP 0x18 Reserved 0x0000 14.6.2 Status Register (USART_STS) Address offset: 0x00 Reset value: 0x00C0...
Page 442 AT32F415 Series Reference Manual TDE: Transmit data register empty This bit is set by hardware when the content of the TDR register is transferred into the shift register. An interrupt is generated if the TDEIEN bit = 1 in the USART_ Bit 7 CTRL1 register.
Page 443: Data Register (Usart_Dt)
AT32F415 Series Reference Manual FERR: Framing error This bit is set by hardware when a de-synchronization, excessive noise, or a break character is detected. It is cleared by a software sequence (a read to the USART_STS register followed by a read to the USART_DT register).
Page 444: Control Register 1 (Usart_Ctrl1)
AT32F415 Series Reference Manual Reserved. Forced to be ‘0’ by hardware. Bit 31:18 DIV_ Integer[11:0]: Integer of USARTDIV Bit 15:4 The 12 bits define the integer of USART Divider (USARTDIV). DIV_Decimal[3:0]: Decimal of USARTDIV Bit 3:0 The 4 bits define the decimalof USART Divider (USARTDIV).
Page 445: Control Register 2 (Usart_Ctrl2)
AT32F415 Series Reference Manual TDEIEN: TDE interrupt enable This bit is set and cleared by software. Bit 7 0: Interrupt is disabled. 1: A USART interrupt is generated when TDE is ‘1’ in the USART_STS register. RDNEIEN: RDNE interrupt enable This bit is set and cleared by software.
Page 446 AT32F415 Series Reference Manual LINEN: LIN mode enable This bit is set and cleared by software. 0: LIN mode is disabled. Bit 14 1: LIN mode is enabled. In LIN mode, the SBR bit in the USART_CTRL1 register can be used to send LIN synch breaks (13 low bits) and to detect LIN sync breaks.
Page 447: Control Register 3 (Usart_Ctrl3)
AT32F415 Series Reference Manual Note: The three bits, CLKPOL, CLKPHA, and LBCP, cannot be modified after enabling transmission. 14.6.7 Control Register 3 (USART_CTRL3) Address offset: 0x14 Reset value: 0x0000 Reserved HALF Reserved Reserved. Forced to be ‘0’ by hardware. Bit 31:11 CTSIEN: CTSF interrupt enable 0: Interrupt is disabled.
Page 448: Guard Time And Prescaler Register (Gtp)
AT32F415 Series Reference Manual HALFSEL: Half-duplex selection Selection of single-wire half-duplex mode Bit 3 0: Half-duplex mode is not selected. 1: Half-duplex mode is selected. IRDALP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes.
Page 449 AT32F415 Series Reference Manual DIV[7:0]: Prescaler value - In IrDA low-power mode: DIV[7:0] = IrDA low-power baud rate is used to divide the system clock to obtain the frequency in low-power mode: The source clock is divided by the value in the register (only 8 significant bits): 00000000: Reserved –...
Page 450: Serial Peripheral Interface (Spi)
AT32F415 Series Reference Manual 15 Serial Peripheral Interface (SPI) 15.1 SPI Introduction The SPI interface supports either the SPI protocol or the I S audio protocol. By default, the SPI function is selected. Users can switch from SPI mode to I S mode by software.
Page 451: Function Overview
AT32F415 Series Reference Manual  Programmable clock polarity (steady state)  Underrun flag in slave transmission mode and overrun flag in master/slave reception mode  16-bit data register for transmission and reception, one data register on each channel side ...
Page 452: Figure 15- 2 Single Master And Single Slave Application
AT32F415 Series Reference Manual  SCK: Serial clock, as output for masters and input for slaves  NSS: Slave select. This is an optional pin which selects master/slave devices. It acts as a “chip select” to allow the SPI master to independently communicate with certain slaves to avoid conflicts on the data lines.
Page 453: Figure 15- 3 Hardware/Software Slave Select Management
AT32F415 Series Reference Manual there is another master processing communication on the bus, and a hardware failure fault (Hard Fault) will be generated. ─ NSS output disabled: Allowed in multimaster mode. Figure 15- 3 Hardware/Software Slave Select Management Clock phase and clock polarity The CPOL and CPHA bits in the SPI_CTRL register can generate four possible timing relationships.
Page 454: Configure Spi In Slave Mode
AT32F415 Series Reference Manual Figure 15- 4 Data Clock Timing Diagram CPHA = 1 CPOL = 1 CPOL = 0 MISO 8-bit or 16-bit data frame format is determined by the DFF16 in SPI_CTRL1 MOSI (To slave) Capture CPHA = 0...
Page 455: Configure Spi In Master Mode
AT32F415 Series Reference Manual transfer, the CPOL and CPHA bits must be configured in the same way in the slave device and the master device. The frame format (MSB-first or LSB-first depending on the LSBEN bit in the SPI_CTRL1 register) must be the same as the master device.
Page 456: Configure Spi For Half-Duplex Communication
AT32F415 Series Reference Manual  Data-in shift register is transferred to Rx buffer, and the RNE flag is set.  An interrupt is generated if the RNEIE bit is set in the SPI_CTRL2 register. After the last sampling clock edge, the RNE bit is set, data byte received in the shift register is moved to the Rx buffer.
Page 457 AT32F415 Series Reference Manual shift register and then parallelly loaded into the SPI_DT register (Rx buffer).  In unidirectional receive-only mode (BDMODE = 0 and RONLY = 1) ─ The sequence begins as soon as SPIEN = 1. ─ Only the receiver is activated, and the received data on the MISO pin are shifted serially into the 8-bit shift register and then are parallelly loaded into the SPI_DT register (Rx buffer).
Page 458 AT32F415 Series Reference Manual generated if the TEIE bit in the SPI_CTRL2 register is set. Writing to the SPI_DT register can clear the TE bit. The software must ensure that the TE flag is set to 1 before attempting to write to Note: the Tx buffer.
Page 459 AT32F415 Series Reference Manual Figure 15- 6 TE/RNE/BSY Behavior during Continuous Transfer in Slave/Full-duplex Mode (BDMODE = 0 and RONLY = 0) Example of slave mode CPOL = 1，CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3...
Page 460 AT32F415 Series Reference Manual Figure 15- 7 TE/BSY Behavior during Continuous Transfer in Master Transmit-only Mode (BDMODE = 0 and RONLY = 0) Example of master mode CPOL = 1，CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3...
Page 461 AT32F415 Series Reference Manual clears the RNE bit). Repeat this operation for each data item to be received. This procedure can also be implemented to handle the interrupts generated at rising edges of the corresponding RNE flags. Note: If the SPI is disabled after the last transfer, please follow the recommended...
Page 462: Crc Calculation
AT32F415 Series Reference Manual Figure 15- 10 TE/BSY Behavior during Discontinuous Transfer (BDMODE = 0 and RONLY = Configuration example：CPOL = 1，CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 MOSI (Output) b0 b1 b2 b3 b4 b5 b6...
Page 463: Status Flag
AT32F415 Series Reference Manual set, and an interrupt is generated when the ERRIE bit in the S PI_CTRL2 register is set. Note: 1. When the SPI is in slave mode, please note that CRC calculation is only enabled after the clock becomes stable. Otherwise, the CRC calculation may be wrong.
Page 464: Disabling Spi
AT32F415 Series Reference Manual  In master mode: The BSY flag is kept high during the whole transfer procedure.  In slave mode: The BSY flag goes low for one SPI clock cycle between each data transfer. Note: Do not use the BSY flag to handle every data transmission or reception. It is better to use the TE and RNE flags instead.
Page 465 AT32F415 Series Reference Manual DMA controller then reads the SPI_DT register, which clears the RNE flag. When only the SPI is used to transmit data, only the SPI Tx DMA channel needs to be enabled. In this case, the OVR flag is set because the data received is not read (Note: Software can ignore this flag).
Page 466: Error Flag
AT32F415 Series Reference Manual Figure 15- 11 Transmission using DMA Configuration example：CPOL = 1, CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 MISO/MOSI (Output) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7...
Page 467: Spi Interrupt
AT32F415 Series Reference Manual bit. Master mode fault affects the SPI peripheral in the following ways:  The MODF bit is set, and an SPI interrupt is generated if the ERRIE bit is set.  The SPIEN bit is cleared. This blocks all outputs from the device and disables the SPI interface.
Page 468: Figure 15- 13 I2S Block Diagram
AT32F415 Series Reference Manual Figure 15- 13 I S Block Diagram Address and data bus Tx buffer I2SC MODF 16-bit MOSI/SD Communication control Shift register MISO LSBEN 16-bit Rx buffer NSS/WS PCMS CHLE YNCS I2SAP[1:0] CPOL DLEN[1:0] I2SSEL I2SEN I2SMOD[1:0]...
Page 469: Supported Audio Protocol
AT32F415 Series Reference Manual the SPI_I2SCLKP register is set. The frequency of output clock signal is set to 256×Fs by default, where Fs is the audio signal sampling frequency. When set in master mode, I S uses its own clock generator to produce the communication clock signal.
Page 470: Figure 15- 15 I2S Philips Protocol Standard Waveforms (24-Bit Frame, Cpol = 0)
AT32F415 Series Reference Manual Figure 15- 15 I S Philips Protocol Standard W aveforms (24-bit frame, CPOL = 0) Reception Transmission 24-bit data Remaining 8 bits forced 0 Channel left 32 Channel right bits This mode needs two write or read operations to/from the SPI_DT register.
Page 471: Figure 15- 19 Example
AT32F415 Series Reference Manual operation shown in Figure 17-19 is required. Figure 15- 19 Example During transmission, MSB should be written to SPI_DT; the TE flag bit is set, indicating that new data can be written, and its interrupt, if allowed, is generated. The transmission is done by hardware;...
Page 472: Figure 15- 21 Msb-Justified 24-Bit Data, Cpol = 0
AT32F415 Series Reference Manual Data are changed on the falling edge of clock signal for transmitter and are read on the rising edge for the receiver. Figure 15- 21 MSB-justified 24-bit Data, CPOL = 0 Reception Transmission 24-bit data Remaining 8 bits force 0...
Page 473: Figure 15- 24 Lsb-Justified 24-Bit Data, Cpol = 0
AT32F415 Series Reference Manual Figure 15- 24 LSB-justified 24-bit Data, CPOL = 0 Transmission Reception 8-bit data forced 0 24-bit data Channel left 32 bits Channel right  In transmission mode If data 0x3478AE is to be transmitted, two write operations to the SPI_DT register are required through software or by DMA.
Page 474: Figure 15- 28 Example
AT32F415 Series Reference Manual operation shown in Figure 17-28 is required. Figure 15- 28 Example During transmission, if TE is ‘1’, users have to write the data to be transmitted (0x76A3 in this case). The 0x0000 field used for extension on 32-bit is transmitted first. The next TE event occurs as soon as valid data begins to be sent from the SD pin.
Page 475: Clock Generator
AT32F415 Series Reference Manual Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data and two synchronization signals needs to be specified by the DLEN bit and the CHLEN bit in the SPI_I2SCTRL register (even in slave mode).
Page 476: Table 15- 2 Audio-Frequency Precision Using System Clock
AT32F415 Series Reference Manual Table 17-2 provides an example of the precision values for different clock configurations. Note: Other configurations can also be used to achieve the optimum clock precision. Table 15- 2 Audio-frequency Precision Using System Clock 16bit 32bit...
Page 477: S Master Mode
AT32F415 Series Reference Manual 44100 46875 6.29% 46875 6.29% 32000 31250 2.34% 31250 2.34% 22050 21634.62 1.88% 21634.62 1.88% 16000 15625 2.34% 15625 2.34% 11025 10817.31 1.88% 10817.31 1.88% 8000 8035.714 0.45% 8035.714 0.45% 15.3.2.4 I S Master Mode When I S is configured in master mode, the serial clock is generated on the CK pin, and the Word Select signal is generated on the WS pin.
Page 478: S Slave Mode
AT32F415 Series Reference Manual require one or two receptions into the Rx buffer. Reading the SPI_DT register can clear the RNE flag bit. I2SCS is updated after each reception. It is sensitive to the WS signal generated by the I S cell.
Page 479: Status Flag
AT32F415 Series Reference Manual the master transmission mode, in slave mode, I2SCS is sensitive to the WS signal from the external S master. This means that the I S slave needs to be ready to transmit the first data before the clock is generated by the master.
Page 480: Error Flag
AT32F415 Series Reference Manual  When I S is disabled. When communication is continuous:  In master transmit mode, the BSY flag is kept high during all the transfers.  In slave mode, the BSY flag goes low for one I S clock cycle between each transfer.
Page 481: S Interrupt
AT32F415 Series Reference Manual 15.3.2.8 I S Interrupt Table 15-3 lists all the I S interrupts. Table 15- 3 I S Interrupt Request Interrupt Event Event Flag Enable Flag Tx buffer empty flag TEIE Rx buffer not empty flag RNEIE...
Page 482 AT32F415 Series Reference Manual SPI_I2SCTR 0x1C Reserved 0x0000 0 0 0 0 0 0 0 0 0 0 0 SPI_I2SCLK 0x20 Reserved 0x0002 0 0 0 0 0 0 0 0 0 0 1 0 2020.06.28 Page 482 Version 1.02...
Page 483: Spi Control Register 1 (Spi_Ctrl1) (Not Used In I2S Mode)
AT32F415 Series Reference Manual 15.4.1 SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode) Address offset: 0x00 Reset value: 0x0000 MCLKP[2:0] BDMODE: Bidirectional data mode enable 0: “2-line unidirectional” mode is selected. Bit 15 1: “1-line bidirectional” mode is selected.
Page 484: Spi Control Register 2 (Spi_Ctrl2)
AT32F415 Series Reference Manual LSBEN: Frame format 0: MSB first Bit 7 1: LSB first Note 1: This bit cannot be changed when communication is ongoing. Note 2: This bit is not used in I S mode. SPIEN: SPI enable 0: SPI is disabled.
Page 485: Spi Status Register (Spi_Sts)
AT32F415 Series Reference Manual ERRIE: Error interrupt enable This bit controls interrupt generation when errors occur (CERR, OVR, or MODF). Bit 5 0: Error interrupt is disabled. 1: Error interrupt is enabled. Reserved. Forced to be ‘0’ by hardware. Bit 4:3...
Page 486: Spi Data Register (Spi_Dt)
AT32F415 Series Reference Manual UDR: Underrun flag 0: No underrun error 1: Underrun error occurs. Bit 3 This bit is set by hardware and reset by software sequence, please refer to Section 15.3.2.7. Note: This bit is not used in SPI mode.
Page 487: Spirxcrc Register (Spi_Rcrc)
AT32F415 Series Reference Manual 15.4.6 SPIRxCRC Register (SPI_RCRC) (Not Used in I S Mode) Address offset: 0x14 Reset value: 0x0000 RCRC[15:0] RCRC[15:0]: Rx CRC register When CRC calculation is enabled, RCRC[15:0] contains the CRC value computed based on the received bytes. This register is reset when the CCE bit in SPI_CTRL1 register is written ‘1’.
Page 488 AT32F415 Series Reference Manual I2SSEL: I S mode selection 0: SPI mode is selected. Bit 11 1: I S mode is selected. Note: This bit can be configured only after SPI or I S is disabled. I2SEN: I S enable 0: I S is disabled.
Page 489: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32F415 Series Reference Manual 15.4.9 SPI_I2S Prescaler Register (SPI_I2SCLKP) Address offset: 0x20 Reset value: 0x0002 I2SM I2SO Reserved I2SDIV[9:8] I2SDIV[7:0] Reserved. Forced to be ‘0’ by hardware. Bit 15:12 I2SDIV[9:8]: I S linear prescaler Bit 12:11 Please refer to the description of I2SDIV[7:0].
Page 490: Can Bus Controller
AT32F415 Series Reference Manual 16 CAN Bus Controller 16.1 Introduction bxCAN is the abbreviation of Basic Extended CAN. It supports the CAN protocols version 2.0A and 2.0B. It is designed to manage a large quantity of incoming messages efficiently with a minimum CPU load.
Page 491: Figure 16- 1 Can Network Topology
AT32F415 Series Reference Manual Network Management and Diagnostic messages are also introduced. ● An enhanced filtering mechanism is required to handle different types of messages. In addition, since application tasks take more CPU time, real-time constraints caused by message reception should be reduced.
Page 492: Operating Mode
AT32F415 Series Reference Manual Figure 16- 2 CAN Block Diagram CAN with 512-byte SRAM Receive FIFO 0 Receive FIFO 1 Tx mailboxes mailbox 0 mailbox 0 mailbox 0 Control register Status register Transmission Tx status register scheduler Rx FIFO 0 status register...
Page 493: Normal Mode
AT32F415 Series Reference Manual 16.3.2.2 Normal Mode Once the initialization is completed, the software must request the hardware to enter Normal mode to start regular reception and transmission. The request to enter Normal mode is issued by software, clearing the INRQ bit in the CAN_MCTRL register, and then wait until the hardware sets the IAK bit in the CAN_MSTS register to confirm.
Page 494: Test Mode
AT32F415 Series Reference Manual 2.SYNC = The state during which bxCAN waits until the CAN bus is idle, which means that 11 consecutive recessive bits are monitored on CANRX. 16.3.3 Test Mode Test modes can be selected by the SIL and/or LBK bits in the CAN_BTMG register. These two bits must be configured in Initialization mode.
Page 495: Loopback And Silent Mode
AT32F415 Series Reference Manual Loopback mode can be used for self-test functions. To be independent of external events, the CAN core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data/remote frame) in Loopback mode. In this mode, bxCAN performs an internal feedback from its Tx output to its Rx input and disregards the actual value of the CANRX pin.
Page 496: Time-Triggered Communication Mode
AT32F415 Series Reference Manual The transmit mailboxes can be configured as transmit FIFO by setting the TFP bit in the CAN_MCTRL register. In this mode, the priority order is given by the transmit request order. This mode is very useful for segmented transmission.
Page 497: Reception Handling
AT32F415 Series Reference Manual 16.3.7 Reception Handling The received messages are stored in FIFO with three-level mailbox depth. In order to save CPU load, simplify the software, and ensure data consistency, the FIFO is completely managed by hardware. The application accesses the messages received first in the FIFO only through the FIFO output mailbox.
Page 498: Identifier Filtering
AT32F415 Series Reference Manual read the FIFO output mailbox to obtain the messages, and release the mailbox by setting the RRFM bit in the CAN_RF register. Then, the FIFO becomes empty again. If a new valid message is received in the meantime, the FIFO stays in pending_1 state, and software can read the FIFO output mailbox to obtain new messages.
Page 499: Figure 16- 9 Filter Bank Scale Configuration - Register Organization
AT32F415 Series Reference Manual The filter banks are configured through the corresponding CAN_FM register. Before configuring a filter bank, it must be deactivated by clearing the FEN bit in the CAN_FA1 register. The filter scale is configured through the corresponding FBSx bit in the CAN_FS1 register. The identifier list or identifier mask mode for the corresponding mask/identifier registers is configured through the FMSx bit in the CAN_FM1 register.
Page 500: Figure 16- 10 Example Of Filter Numbering
AT32F415 Series Reference Manual For filters in identifier list mode (nonmasked filters), the software no longer has to compare the identifier. For masked filters in mask mode, software only compares those masked bits needed (must match bits). When numbering filters, activation state of the filter banks is not taken into account. In addition, each FIFO numbers its own associated filter independently.
Page 501: Message Storage
AT32F415 Series Reference Manual ● For filters with equal scale and in the same mode, priority is given according to the filter number (the lower the number, the higher the priority). Figure 16- 11 Example of Filtering Mechanism Example: 3 filter banks in identifier list mode...
Page 502: Table 16- 1 Transmit Mailbox Mapping
AT32F415 Series Reference Manual sends transmit requests). The status of the transmission is indicated in the CAN_TSTS register. Table 16- 1 Transmit Mailbox Mapping Offset to Transmit Mailbox Base Address Register Name CAN_TMIx CAN_TDTx CAN_TDLx CAN_TDHx Receive mailbox (FIFO) When a message is received, the software can access the FIFO output mailbox to read it. Once the software handles the message (e.g.
Page 503: Error Management
AT32F415 Series Reference Manual 16.3.10 Error Management The error management as described in the CAN protocol is handled entirely by hardware with a Transmit Error Counter (the TEC field in the CAN_ESTS register) and a Receive Error Counter (the REC field in the CAN_ESR register). Its value is incremented or decremented according to the error.
Page 504: Figure 16- 13 Bit Timing
AT32F415 Series Reference Manual Figure 16- 13 Bit Timing Normal bit time SYNC_SEG Segment 1 (BS1) Segment 2 (BS2) t BS1 1×t q t BS2 Transmit Sample point point Baud rate = Normal bit time t BS1 t BS2 Normal bit time = 1 ×...
Page 505: Figure 16- 14 Various Can Frames
AT32F415 Series Reference Manual Figure 16- 14 Various CAN Frames Inter-frame space Data frame (standard identifier) Inter-frame space or overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame space Inter-frame space...
Page 506: Bxcan Interrupt
AT32F415 Series Reference Manual 16.3.12 bxCAN Interrupt Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by the CAN interrupt enable register (CAN_INTEN). Figure 16- 15 Event Flag and Interrupt Generation CAN_INTEN Transmission...
Page 507: Can Registers
AT32F415 Series Reference Manual 16.4 CAN Registers These peripheral registers must be accessed by words (32-bit). Table 16- 3 CAN Register Map and Reset Values Offset Register MCTRL 000h Reserved Reserved Reset Value 0 0 0 0 0 0 1 0...
Page 508 AT32F415 Series Reference Manual TMI1 SID/EID[28:18] EID[17:0] 190h Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...
Page 509: Register Access Protection
AT32F415 Series Reference Manual 218h Reserved 21Ch Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 220h~ Reserved 23Fh FB0R1 240h Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...
Page 510 AT32F415 Series Reference Manual TTC: Time-triggered communication mode Bit 7 0: Time-triggered communication mode is disabled. 1: Time-triggered communication mode is enabled. ABO: Automatic bus-off management This bit determines the conditions under which the CAN hardware exits the bus-off state.
Page 511: Can Main Status Register (Can_Msts)
AT32F415 Series Reference Manual 16.4.2.2 CAN Main Status Register (CAN_MSTS) Address offset: 0x04 Reset value: 0x0000 0C02 Reserved Reserved LSAP Reserved SAKIT WKIT ERIT rc w1 rc w1 rc w1 Reserved. Forced to be ‘0’ by hardware. Bit 31:12 RXS: CANRx signal Bit 11 This bit indicates the actual level of the CAN Rx pin (CAN_RX).
Page 512: Can Tx Status Register (Can_Tsts)
AT32F415 Series Reference Manual 16.4.2.3 CAN Tx Status Register (CAN_TSTS) Address offset: 0x08 Reset value: 0x1C00 0000 LPM2 LPM1 LPM0 TSME2 TSME1 TSME0 NTM[1:0] ARQ2 Reserved TER2 ALS2 TOK2 RQC2 rc w1 rc w1 rc w1 rc w1 ARQ1 Reserved...
Page 513 AT32F415 Series Reference Manual RQC2: Request completed mailbox 2 Set by hardware when the last request (transmit or abort) to mailbox 2 is completed. Cleared by software writing ‘1’ or by hardware on transmission request (TRQ set in the Bit 16 CAN_TMI2 register).
Page 514: Can Receive Fifo 0 Register (Can_Rf0)
AT32F415 Series Reference Manual 16.4.2.4 CAN Receive FIFO 0 Register (CAN_RF0) Address offset: 0x0C Reset value: 0x00 Reserved Reserved Reserved RFP0 rc w1 rc w1 Reserved. Forced to be ‘0’ by hardware. Bit 31:6 RRFM0: Release receive FIFO 0 output mailbox Set by software to release the FIFO output mailbox.
Page 515: Can Interrupts Enable Register (Can_Inten)
AT32F415 Series Reference Manual RFOV1: FIFO 1 overrun This bit is set by hardware when a new message is received and passes the filter while the Bit 4 FIFO 1 is full. This bit is cleared by software. RFFU1: FIFO 1 full Bit 3 Set by hardware when three messages are stored in the FIFO 1.
Page 516: Can Error Status Register (Can_Ests)
AT32F415 Series Reference Manual Reserved. Forced to be ‘0’ by hardware. Bit 7 RFOVIE1: FIFO 1 overrun interrupt enable Bit 6 0: No interrupt is generated when the RFOV bit of FIFO 1 is set. 1: An interrupt is generated when the RFOV bit of FIFO 1 is set.
Page 517: Can Bit Timing Register (Can_Btmg)
AT32F415 Series Reference Manual ERC[2:0]: Last error code Set by hardware according to the error condition on detection of CAN bus error. Cleared by hardware after message is correctly transmitted or received. Hardware does not use error code 7; the value of this bit field can be configured by software, so the updates of the code can be monitored.
Page 518: Can Mailbox Register
AT32F415 Series Reference Manual BS1[3:0]: Time segment 1 Bit 19:16 These bits define the number of time quanta in time segment 1. x (BS1[3:0] + 1) Reserved. Forced to be ‘0’ by hardware. Bit 15:12 BRP[11:0]: Baud rate prescaler These bits define the length of a time quanta (t...
Page 519: Mailbox Data Length And Time Stamp Register ( Can_Tdtx)
AT32F415 Series Reference Manual EID[17:0]: Extended identifier Bit 20:3 The LSBs of the extended identifier. IDT: Identifier extension This bit defines the type of identifier of the mailbox messages. Bit 2 0: Standard identifier 1: Extended identifier RTR: Remote transmission request...
Page 520: Tx Mailbox Data Low Register (Can_Tdlx) (X = 0
AT32F415 Series Reference Manual 16.4.3.3 Tx Mailbox Data Low Register (CAN_TDLx) (x = 0...2) All bits of this register are write-protected when the mailbox is not in empty state. Address offset: 0x188, 0x198, 0x1A8 Reset value: Undefined D3[7:0]: Data byte 3...
Page 521: Rx Fifo Mailbox Identifier Register (Can_Rfix) (X = 0
AT32F415 Series Reference Manual 16.4.3.5 Rx FIFO Mailbox Identifier Register (CAN_RFIx) (x = 0…1) Address offset: 0x1B0, 0x1C0 Reset value: Undefined Note: All Rx mailbox registers are read-only. SID[10:0]/EID[28:18] EID[17:16] EID[15:0] Reserved SID[10:0]/EID[28:18]: Standard identifier or extended identifier Bit 31:21 Based on the IDT bit value, these bits are standard identifier or the MSBs of extended identifier.
Page 522: Rx Fifo Mailbox Data High Register (Can_Rdlx) (X = 0
AT32F415 Series Reference Manual 16.4.3.7 Rx FIFO Mailbox Data High Register (CAN_RDLx) (x = 0…1) Address offset: 0x1B8, 0x1C8 Reset value: Undefined Note: All Rx mailbox registers are read-only. D3[7:0]: Data byte 3 Bit 31:24 Data byte 3 of the message...
Page 523: Can Filter Register
AT32F415 Series Reference Manual 16.4.4 CAN Filter Register 16.4.4.1 CAN Filter Main Control Register (CAN_FM) Address offset: 0x200 Reset value: 0x2A1C 0E01 Note: The non-reserved bits in this register are fully controlled by software. Reserved Reserved FINT Bit 31:1 Reserved. Forced to be reset value.
Page 524: Can Filter Mode Register (Can_Fm1)
AT32F415 Series Reference Manual 16.4.4.2 CAN Filter Mode Register (CAN_FM1) Address offset: 0x204 Reset value: 0x0000 0000 Note: This register can only be written when CAN_FM is set (FINT = 1), which puts filters in Initialization mode. Reserved Reserved Reserved. Forced to be ‘0’ by hardware.
Page 525: Can Filter Activation Register (Can_Fa1)
AT32F415 Series Reference Manual Reserved Reserved. Forced to be ‘0’ by hardware. Bit 31:14 FAFx: Filter assignment for FIFO configuration The message passing through certain filter will be stored in the assigned FIFO. Bit 13:0 0: Filter is assigned to FIFO 0.
Page 526 AT32F415 Series Reference Manual FD[31:0]: Filter bits Identifier mode Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected. 1: Recessive bit is expected. Bit 31:0 Mask mode Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier.
Page 527: Sdio Interface
AT32F415 Series Reference Manual 17 SDIO Interface 17.1 Introduction SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus, MultiMediaCard (MMC), SD memory cards, SDIO cards, and CE-ATA devices. The MultiMediaCard system specifications, published by the MMCA technical committee, are available on the MultiMediaCard Association website (www.mmca.org).
Page 528: Figure 17- 1 Sdio "No Response" And "No Data" Operation
AT32F415 Series Reference Manual Figure 17- 1 SDIO “No Response” and “No Data” Operation From host From host From card to card to host to card SDIO_CMD SDIO_D Operation (No response) Operation (No data) Figure 17- 2 SDIO (Multiple) Data Block Read Operation...
Page 529: Function Overview
AT32F415 Series Reference Manual Figure 17- 4 SDIO Sequential Read Operation From host From card to card to host Data from card to Stop command host stops data transfer SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation...
Page 530: Sdio Adapter
AT32F415 Series Reference Manual Figure 17- 6 SDIO Block Diagram After reset, SDIO_D0 is used for data transfer by default. After initialization, the host can change the data bus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0], or SDIO_D[7:0] can be used for data transfer.
Page 531: Figure 17- 7 Sdio Adaptor
AT32F415 Series Reference Manual Figure 17- 7 SDIO Adaptor Control unit SDIO_CK Command path SDIO_CMD Adapter registers To AHB Data path SDIO_D[7:0] Interface SDIOCLK HCLK The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card.
Page 532: Figure 17- 8 Control Unit
AT32F415 Series Reference Manual Figure 17- 8 Control Unit Control unit Power management Adaptor Clock management SDIO_CK registers To command and data path Figure 17-8 is the block diagram of control unit. It consists of a power management sub-unit and a clock management sub-unit.
Page 533: Figure 17- 10 Command Path State Machine (Cpsm)
AT32F415 Series Reference Manual ● Command path state machine (CPSM) ─ When the command register is written, and the enable bit is set, command transfer starts. When the command transfer is completed, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required (See Figure 17-10).
Page 534: Table 17- 2 Command Format
AT32F415 Series Reference Manual Figure 17- 11 SDIO Command Transfer ● Command format ─ Command: A command is a token that starts an operation. Commands are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available only for MMC V3.31 or previous).
Page 535: Table 17- 4 Long Response Format
AT32F415 Series Reference Manual Table 17- 4 Long Response Format Width Value Description Start bit Transmission bit [133:128] 111111 Reserved CID or CSD (including [127:1] internal CRC7) End bit The command register contains the command index (six bits sent to a card) and the command type;...
Page 536: Figure 17- 13 Data Path Status Machine (Dpsm)
AT32F415 Series Reference Manual The card data bus width can be programmed through the clock control register. If the 4-bit wide bus mode is enabled, 4-bit data is transferred per clock cycle over all four data signals (SDIO_D[3:0]); if the 8-bit wide bus mode is enabled, 8-bit data is transferred per clock cycle over all eight data signals (SDIO_D[7:0]).
Page 537: Table 17- 6 Data Token Format
AT32F415 Series Reference Manual ─ In stream mode, DPSM receives data when the data counter is not 0. When the counter is 0, the remaining data in the shift register is written to the data BUF, and DPSM moves to the Wait_R state.
Page 538: Sdio Ahb Interface
AT32F415 Series Reference Manual The transmit BUF is accessible via 32 sequential addresses. The transmit BUF contains a data output register that holds the data word pointed to by the read pointer. After the data path subunit loads its shift register, it moves the read pointer to the next data and outputs the data.
Page 539: Card Function Overview
AT32F415 Series Reference Manual Enable DMA2 controller and clear all interrupt flag bits. Program the DMA2 Channel 4 source address register as the base address of memory buffer, and DMA2_Channel 4 destination address register as the SDIO_BUF register address. Program DMA2 Channel 4 control register (memory increment, non-peripheral increment, peripheral and source width is word size).
Page 540: Card Identification Process
AT32F415 Series Reference Manual 17.3.2.4 Card Identification Process Card identification process differs for MultiMediaCards and SD cards. For MultiMediaCards, the identification process starts at clock rate, F . All SDIO_CMD line output drivers are open-drain and allow parallel card operation during this process. The identification process is accomplished as follows: The bus is activated.
Page 541: Block Write
AT32F415 Series Reference Manual The SDIO card host sends IO_SEND_OP_COND (CMD5). The received response is the contents of cards operation condition registers. The incompatible cards are set to the inactive state. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address.
Page 542: Stream Access, Stream Write, And Stream Read
AT32F415 Series Reference Manual the card detects a block misalignment error condition at the beginning of the first misaligned block, and the ADDRESS_ERROR error bit is set in the status register. 17.3.2.7 Stream Access, Stream Write, and Stream Read (MultiMediaCard Only) In stream mode, data is transferred in bytes, and no CRC is appended at the end of each block.
Page 543: Erase: Group Erase And Sector Erase
AT32F415 Series Reference Manual 17.3.2.8 Erase: Group Erase and Sector Erase The erasable unit of the MultiMediaCard is the erase group. The erase group is measured in write blocks, which are the basic writable units of the card. The size of the erase group is a card-specific parameter and defined in CSD.
Page 544 AT32F415 Series Reference Manual The password protection feature enables the SDIO card host module to lock and unlock a card with a password. The password is stored in the 128-bit PWD register, and its size is set in the 8-bit PWD_LEN register.
Page 545 AT32F415 Series Reference Manual When the password is matched, the PWD field is cleared, and PWD_LEN is set to 0. When the password sent does not correspond (in size and/or content) to the expected password, the LOCK_UN LOCK_FAILED error bit is set in the card status register, and the password is not changed.
Page 546: Card Status Register
AT32F415 Series Reference Manual in the card status register; the card retains all of its data and remains locked. An attempt to use a force erase on an unlocked card will fail, and the LOCK_UNLOCK_FAILED error bit will be set in the card status register.
Page 547 AT32F415 Series Reference Manual Clear Identifier Value Description Conditio ‘0’ = No error LOCK_UNLOCK_ A sequence error or a password error is detected ‘1’ = Error FAILED in lock/unlock card command. ‘0’ = No error COM_CRC_ERROR The CRC check fails in the previous command.
Page 548: Sd Status Register
AT32F415 Series Reference Manual Clear Identifier Value Description Conditio Reserved for application specific commands Reserved for manufacturer test mode 17.3.2.12 SD Status Register The SD status contains status bits that are related to the SD memory card proprietary features and status bits that may be used for future applications.
Page 549: Table 17- 10 Sd Status
AT32F415 Series Reference Manual Table 17- 10 SD Status Clear Identifier Value Description Conditio ‘00’ = 1 (Default) The current data bus width ‘01’ = Reserved 511:510 DAT_BUS_WIDTH SR defined by SET_BUS_WIDTH ‘10’ = 4-bit wide command ‘11’ = Reserved Card is in secured mode operation ‘0’...
Page 550: Table 17- 11 Speed Class Code Field
AT32F415 Series Reference Manual SPEED_CLASS This 8-bit field indicates the speed class and the value that can be calculated by P /2 (where PW is the write performance). Table 17- 11 Speed Class Code Field SPEED_CLASS Value Definition Type 0...
Page 551: Table 17- 14 The Maximum Of Au Size
AT32F415 Series Reference Manual Table 17- 14 The Maximum of AU Size Capacity 16 MB ~ 64 MB 128 MB ~ 256 MB 512 MB 1 GB ~ 32 GB The Max. of AU Size 512 KB 1 MB 2 MB...
Page 552: Sd I/O Mode
AT32F415 Series Reference Manual 17.3.2.13 SD I/O Mode SD I/O interrupts To allow the SD I/O card to interrupt the MultiMediaCard/SD module, an interrupt function is available on a pin of the SD interface: Pin 8. Pin 8 is used as SDIO_D1 when operating in the 4-bit SD mode, and the card signals interrupt to the MultiMediaCard/SD module with this pin.
Page 553: Table 17- 18 Block-Oriented Write Command
AT32F415 Series Reference Manual To use manufacturer-specific ACMDs, the SD card Host must perform the following steps: 1. Send APP_CMD (CMD55) command The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set, and an ACMD is now expected.
Page 554: Table 17- 19 Block-Oriented Write Protection Command
AT32F415 Series Reference Manual Table 17- 19 Block-oriented W rite Protection Command Respons Type Argument Abbreviation Description Index e format If the card has write protection features, this command sets the write protection SET_WRITE_ CMD28 [31:0] = Data address bit of the addressed group. The write...
Page 555: Response Format
AT32F415 Series Reference Manual Table 17- 23 Application-specific Command Respons Type Argument Abbreviation Description Index e format Indicate the card that the next command [31:16] = RCA CMD55 APP_CMD is an application-specific command [15:0] = Stuff bits rather than a standard command.
Page 556: R2 (The Cid And Csd Registers)
AT32F415 Series Reference Manual 17.3.3.3 R2 (The CID and CSD Registers) Code length = 136 bits. The contents of the CID register are sent as a response to the CMD2 and CMD10 commands. The contents of the CSD register are sent as a response to CMD9. Only the bits [127:1] of the CID and CSD registers are transferred, the reserved bit [0] of these receive registers is replaced by the end bit of the response.
Page 557: R4B
AT32F415 Series Reference Manual 17.3.3.6 R4b For SD I/O only: An SDIO card receiving the CMD5 will respond with a unique SDIO response R4. Table 17- 28 R4b Response Width (Bit) Value Description Start bit Transmission bit [45:40] Reserved Card is ready...
Page 558: R6 (Interrupt Request)
AT32F415 Series Reference Manual 17.3.3.8 R6 (Interrupt Request) Only for SD I/O. This is the normal response to CMD3 by a memory device. Table 17- 30 R6 Response Width (Bit) Value Description Start bit Transmission bit ‘000011’ [45:40] CMD3 RCA[31:16] of winning...
Page 559: Sdio Suspend/Resume Operation
AT32F415 Series Reference Manual 17.3.4.3 SDIO Suspend/Resume Operation While sending data to the card, SDIO can suspend the write operation. The SDIO_CMD[11] bit is set and indicates to CPSM that the current command is a suspend command. CPSM analyzes the response, and when the ACK is received from the card (suspend accepted), it goes idle after acknowledging the CRC token of the current block received.
Page 560 AT32F415 Series Reference Manual SDIO_RSPC RSPCMD[5:0] 0x10 Reserved 0x00000000 0 0 0 0 0 0 SDIO_RSP1 CARDSTS1[31:0] 0x14 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 561: Sdio Power Control Register (Sdio_Power)
AT32F415 Series Reference Manual 17.4.1 SDIO Power Control Register (SDIO_POWER) Address offset: 0x00 Reset value: 0x00000000 Reserved Reserved PWRCTRL Bit 31:2 Reserved. Always read as 0. PWRCTRL: Power supply control bits These bits are used to define the current functional state of the card clock: 00: Power-off: The clock to card is stopped.
Page 562: Sdio Argument Register (Sdio_Arg)
AT32F415 Series Reference Manual BYPS: Clock divider bypass enable bit 0: Disable bypass: SDIOCLK is divided according to the CLKPSC value before driving Bit 10 the SDIO_CK output signal. 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal. PWRSVG: Power saving configuration bit...
Page 563: Sdio Command Register (Sdio_Cmd)
AT32F415 Series Reference Manual 17.4.4 SDIO Command Register (SDIO_CMD) Address offset: 0x0C Reset value: 0x00000000 The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
Page 564: Sdio Command Response Register (Sdio_Rspcmd)
AT32F415 Series Reference Manual 17.4.5 SDIO Command Response Register (SDIO_RSPCMD) Address offset: 0x10 Reset value: 0x00000000 The SDIO_RSPCMD register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long response or OCR response), the RSPCMD field is unknown, although it should contain 111111b (the value of the reserved field from the response).
Page 565: Sdio Data Timer Register (Sdio_Dttmr)
AT32F415 Series Reference Manual 17.4.7 SDIO Data Timer Register (SDIO_DTTMR) Address offset: 0x24 Reset value: 0x00000000 The SDIO_DTTMR register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTTMR register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state.
Page 566: Sdio Data Control Register (Sdio_Dtctrl)
AT32F415 Series Reference Manual 17.4.9 SDIO Data Control Register (SDIO_DTCTRL) Address offset: 0x2C Reset value: 0x00000000 The SDIO_DTCTRL register controls data path state machine (DPSM). Reserved SDIO DMAE TFRM TFRDI TFRE Reserved BLKSIZE TMOD TSTO TSTA Bit 31:12 Reserved. Always read as 0.
Page 567: Sdio Data Counter Register (Sdio_Dtcntr)
AT32F415 Series Reference Manual TFREN: Data transfer enabled bit Data transfer starts when ‘1’ is written to this bit. Depending on the direction bit, TFRDIR, DPSM moves to the Wait_S or Wait_R state. If the RDWTSTART is set at Bit 0 the beginning of the transfer, DPSM enters read wait state.
Page 568: Sdio Clear Interrupt Register (Sdio_Intclr)
AT32F415 Series Reference Manual Bit 22 SDIOIF: SDIO interrupt received Bit 21 RXBUF: Data available in receive BUF TXBUF: Data available in transmit BUF Bit 20 Bit 19 RXBUF_E: Receive BUF empty TXBUF_E: Transmit BUF empty Bit 18 When Hardware Flow Control is enabled, TXBUF_E signal becomes activated when BUF contains 2 words.
Page 569: Sdio Interrupt Mask Register (Sdio_Inten)
AT32F415 Series Reference Manual Bit 31:24 Reserved. Always read as 0. ATACMPL: ATACMPL flag clear bit Bit 23 This bit is set by software to clear the ATACMPL flag. SDIOIF: SDIOIF flag clear bit Bit 22 This bit is set by software to clear the SDIOIF flag.
Page 570 AT32F415 Series Reference Manual ATACMPL: CE-ATA command completion signal received interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated after Bit 23 receiving CE-ATA command completion signal. 0: CE-ATA command completion signal received interrupt is disabled.
Page 571: Sdio Buf Counter Register (Sdio_Bufcntr)
AT32F415 Series Reference Manual DTBLKCMPL: Data block end interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated by data block end. Bit 10 0: Data block end interrupt is disabled. 1: Data block end interrupt is enabled.
Page 572: Sdio Data Buf Register (Sdio_Buf)
AT32F415 Series Reference Manual transfer enable bit, TFREN, is set in the data control register (SDIO_DTCTRL), and DPSM is at the Idle state. If the data length is not word aligned (multiple of 4), the remaining 1 ~ 3 bytes are regarded as a word.
Page 573: Mcu Debug (Mcudbg)
AT32F415 Series Reference Manual 18 MCU Debug (MCUDBG) 18.1 Introduction ® AT32F415 are built with the Cortex -M4 core, which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint).
Page 574: Function Overview
AT32F415 Series Reference Manual 18.2 Function Overview 18.2.1 Debug Support for Low-power Mode To enter low-power mode, the instruction of WFI and WFE are executed. MCU supports several low-power modes, which can either deactivate the CPU clock or reduce the power consumption of the CPU.
Page 575: Trace Pin Assignment
AT32F415 Series Reference Manual ● JTMS/SWDIO: internal pull-up ● JTCK/SWCLK: internal pull-down Once the JTAG I/O is released by the user code, GPIO controller gains control again. The state of these I/Os will resume to the reset state. ● JNTRST: input with pull-up ●...
Page 576: Mcudbg Control Register (Mcudbg_Ctrl)
AT32F415 Series Reference Manual MCUDBG_ CTRL 0xE004 Reser Reser 2004 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value 18.3.1 MCUDBG Control Register (MCUDBG_CTRL) The MCUDBG_CTRL register is mapped on the external PPB bus at base address, 0xE0042000.
Page 577 AT32F415 Series Reference Manual DBG_WWDG_STOP: Debug window watchdog stops when the core enters debug state. Bit 9 0: The window watchdog counter still works normally. 1: The window watchdog counter stops. DBG_IWDG_STOP: Watchdog stops when the core enters debug state.
Page 578: Comparator (Comp)
AT32F415 Series Reference Manual 19 Comparator (COMP) 19.1 COMP Introduction AT32F415 has two embedded ultra-low-power consumption comparators, COMP1 and COMP2. They can be used as independent devices (all ports are provided on I/O), or used together with timers. Comparators feature multiple functions, including: ...
Page 579: Comp Pins And Internal Signals
AT32F415 Series Reference Manual 19.3.2 COMP Pins and Internal Signals When I/Os are used as comparator inputs, they should be configured to analog mode in the GPIOs register. With the alternate function channel provided in the data sheet, comparator output can be mapped to I/O.
Page 580: Power Mode
AT32F415 Series Reference Manual 19.3.6 Power Mode For a given application, COMP power consumption and transfer hysteresis can be adjusted to reach the ideal balance. The COMPx_MDE bit in the COMP_CTRLSTS1 register can be programmed to provide higher speed/power or lower speed/power.
Page 581: Comp Interrupt
AT32F415 Series Reference Manual 19.4 COMP Interrupt Comparator output is internally connected to extended interrupt and event controller. Each comparator has an individual EXTI line to generate interrupt or event. This mechanism can also be used for exiting low-power mode.
Page 582: Comparator Control And Status Register 1 (Comp_Ctrlsts1)
AT32F415 Series Reference Manual 19.5.1 Comparator Control and Status Register 1 (COMP_CTRLSTS1) COMP_CTRLSTS1 is Comparator Control/Status Register. This register includes bits/flags relevant to the comparator. Offset address: 0x00 Reset value: 0x0000 COMP2HY COMP2OUTSEL[2: COMP2INNSEL[2: rw/r rw/r rw/r rw/r rw/r rw/r...
Page 583 AT32F415 Series Reference Manual 111: Reserved Bit 19 Reserved, kept at reset value. COMP2MDE: Comparator 2 mode This bit controls COMP2 operation mode, allowing to adjust speed and power consumption. Bit 18 0: High speed/Maximum power consumption 1: Low speed/Low power consumption Bit 17 Reserved, kept at reset value.
Page 584: Comparator Control/Status Register 2 (Comp_Ctrlsts2)
AT32F415 Series Reference Manual 19.5.2 Comparator Control/Status Register 2 (COMP_CTRLSTS2) COMP_CTRLSTS2 is Comparator Control/Status Register. This register includes bits/flags relevant to the comparator. Offset address: 0x04 Reset value: 0x0001 0001 COMP2INP Reserved rw/r COMP1INP Reserved rw/r Bit 31:18 Reserved, kept at reset value.
Page 585: Interference Filter High Pulse (High_Pulse)
AT32F415 Series Reference Manual 19.5.4 Interference Filter High Pulse (HIGH_PULSE) Offset address: 0x0C Reset value: 0x0000 Reserved H_PULSE_CNT Bit 15:6 Reserved, always read as 0. H_PULSE_CNT: High pulse count Valid level change of filter input signal should be stable at least for H_PULSE_CNT+1 clock cycles, then it can be considered as valid input, and the output will turn to high level.
Page 586: Hsi Auto Clock Calibration
AT32F415 Series Reference Manual 20 HSI Auto Clock Calibration 20.1 ACC Introduction HSI Auto Clock Calibration (HSI ACC) utilizes the SOF signal (with cycle of 1 millisecond) generated by the USB module, to realize sampling and calibration to the HSI clock.
Page 587: Acc Characteristics
AT32F415 Series Reference Manual frequency will decrease by 40 kHz (design value). ● HSITWK: Calibration signal of HSI module. For the divided (1/6) HSI clock, every HSITWK step variation will trim the divided (1/6) HSI clock by 20 kHz frequency (design value), and it is positive correlation.
Page 588: Acc Interrupt Request
AT32F415 Series Reference Manual sampling cycle will be either < C2 or > C2. When this value is < C2, automatic calibration will increase HSICAL or HSITWK based on step definition until the actual sampling value is > C2, to realize the cross of sampling value from < C2 to >...
Page 589: Acc Register Description
AT32F415 Series Reference Manual Figure 20- 3 ACC Interrupt Mapping Diagram 20.5 ACC Register Description For the abbreviations in the register description, please refer to Section 1.4.1. These peripheral registers can be accessed by half-word (16-bit) or word (32-bit). 20.5.1 ACC Register Address Mapping...
Page 590: Status Register (Acc_Sts)
AT32F415 Series Reference Manual 20.5.2 Status Register (ACC_STS) Address offset: 0x00 Reset value: 0x0000 Reserved RSLOS CALRD Bit 31:3 Reserved, forced to be 0 by hardware. RSLOST: Reference Signal Lost During calibration process, if the sampling counter value of calibration module is twice of C2, and SOF reference signal has not been detected, then it means that reference signal is lost.
Page 591: Control Register 2 (Acc_Ctrl2)
AT32F415 Series Reference Manual CALRDYIEN: CALRDY interrupt enable This bit is set or cleared by software. Bit 5 0: Interrupt generation is disabled. 1: When CALRDY in ACC_STS is ‘1’, generate ACC interrupt. EIEN: RSLOST error interrupt enable This bit is set or cleared by software.
Page 592: Compare Value 1 (Acc_C1)
AT32F415 Series Reference Manual 20.5.5 Compare Value 1 (ACC_C1) Address offset: 0x0C Reset value: 0x1F2C Reserved Bit 31:16 Reserved, forced to be 0 by hardware. C1: Compare 1 This value is the lower boundary of trigger calibration; the default value is 7980. When automatic calibration module’s sampling clock number <...
Page 593: Usb Otg Full-Speed (Otg_Fs)
AT32F415 Series Reference Manual 21 USB OTG Full-speed (OTG_FS) 21.1 OTG Module Introduction Portions Copyright (c) Synopsys, Inc (2004 and 2005). All rights reserved. Used with permission. This chapter introduces the structure and use of OTG_FS Core. Terminology: FS: Full speed...
Page 594: Host Mode Function
AT32F415 Series Reference Manual 21.2.2 Host Mode Function OTG_FS interface: ● An external charge pump is required to supply VBUS. ● Supports up to 8 host channels, each can be dynamically configured as any transfer type. ● Embedded hardware scheduling controller: ─...
Page 595: Otg_Fs Function Descriptions
AT32F415 Series Reference Manual 21.3 OTG_FS Function Descriptions Figure 21- 1 Function Diagram Cortex-M4 core USB interrupt Pow er and cl ock USB2.0 control OTG FS Core USB suspend System USB Clock clock area area USB bus 1.25-Kbyte USB data FIFO 21.3.1 OTG Full-speed Core...
Page 596: Dual-Role Device (Drd)
AT32F415 Series Reference Manual ● DP/DM line has embedded pull-up/pull-down resistor, controlled by OTG_FS Core to satisfy current device needs. In device mode, when high-level (B-type effective) occurs on VBUS, the controller will enable DP line’s pull-up resistor to inform the host the connection of a USB full-speed device.
Page 597: Device State
AT32F415 Series Reference Manual Figure 21- 3 Simple USB Peripheral Connections 5 V to VDD V ol t age r egul at or AT32F415xx VBUS PA11 OSC_IN PA12 OSC_OUT 1．A bus power supply device can be designed by using voltage regulator.
Page 598: Device Endpoint
AT32F415 Series Reference Manual to confirm suspend. The device suspend bit in the device status register (the SUSPSTS bit in the OTG_FS_DSTS register) will be automatically set, and the OTG_FS core enters suspend state. The device can autonomously exit the suspend state by setting the remote wakeup signal bit (the RWKUPSIG bit in the OTG_FS_DCTL register) in the device control register and clearing the bit between 1 ms and 15 ms.
Page 599: Usb Host Mode
AT32F415 Series Reference Manual ─ Set odd/even frame of the transfer frame that should be transmitted or received (Only effective to isochronous transfer) ─ Optional configuration: Set the NAK bit to response host with NAK regardless of the FIFO status ─...
Page 600: Usb Host States
AT32F415 Series Reference Manual ． Note: The controller cannot use 5-V VBUS power supply, so an external charge pump is required. If the application board can provide 5-V power supply, then the basic switch power can drive the 5-V VBUS. The external charge pump can be controlled by any universal I/O port. This design is needed for OTG A-type host, A-type device, and USB host.
Page 601: Host Channel
AT32F415 Series Reference Manual Host enumeration Once host detects device connection, it should enter enumeration process to transmit USB reset and configuration command to the new connected device. Since the connected device has pull-up resistor on DP (full-speed device) or DM (low-speed device) line, it will cause instability of the bus.
Page 602: Host Scheduler
AT32F415 Series Reference Manual Host channel transfer The application configures the transfer size and reads transfer status through the host channel transfer size register (HCTSIZx). Before enabling the transfer channel, the transfer size must be configured first. Once the channel is enabled, the transfer size register will become read-only, and can only be updated by OTG_FS core.
Page 603 AT32F415 Series Reference Manual ● Periodic transfer FIFO, the queue status register (HPTXSTS), the non-periodic transfer FIFO, and the queue status register (GNPTXSTS) include: ─ The request number available in the periodic and non-periodic queue (max.:8) ─ Space available in the periodic (non-periodic) TX FIFO (for OUT transfer) ─...
Page 604: Sof Trigger
AT32F415 Series Reference Manual 21.7 SOF Trigger Figure 21- 5 SOF Connection AT32F415 SOF output to external audio control VBUS PA11 ITRE pulse PA12 TIM2 PA10 generator OTG_FS core provides: ● SOF monitoring, tracking, and configuring ● SOF pulse output...
Page 605: Power Supply Option
AT32F415 Series Reference Manual 21.8 Power Supply Option The OTG PHY power supply is determined by the following 3 bits in the general controller configuration register: ● PHY power supply bit (the PWRDOWN bit in the GCCFG register) ─ Switch of PHY full-speed transceiver module. This bit should be configured in advance to allow USB communication.
Page 606: Usb Data Fifo
AT32F415 Series Reference Manual 21.9 USB Data FIFO Figure 21-6 shows the diagram of OTG_FS core and functions. Figure 21- 6 OTG_FS Core Diagram AHB slave interface BIUS AHB Slave unit PSRAM FS serial interface BIUS: bus interface unit; AIU: application interface unit; PFC: packet FIFO controller; MAC: media access controller;...
Page 607: Device Fifo Architecture
AT32F415 Series Reference Manual 21.10 Device FIFO Architecture Figure 21- 7 FIFO Address Mapping and AHB FIFO Mapping in Device Mode A data FIFO DIEPTXF2[31：16] Write access from AHB Dedicated TX TX FIFO #n message to IN endpoint TX FIFO FIFO #n control DIEPTXFx[15：0]...
Page 608: Host Fifo Architecture
AT32F415 Series Reference Manual Dedicated FIFO structure is very flexible, which can greatly decrease application’s loading. These FIFOs do not have request sequence, and there is no need to predict access sequence when USB host accesses non-periodic endpoint. Based on the non-periodic TX FIFO empty level bit (the TXFEMLVL bit in the OTG_FS_GAHBCFG...
Page 609: Host Tx Fifo
AT32F415 Series Reference Manual 21.11.2 Host TX FIFO In host mode, controller uses one TX FIFO to manage all non-periodic (control and bulk transfer) OUT transfers and uses the other TX FIFO to manage all periodic (isochronous and interrupt) OUT transfer.
Page 610: Otg_Fs Interrupt
AT32F415 Series Reference Manual 21.13 OTG_FS Interrupt No matter OTG_FS core works in host mode or device mode, the application cannot access the registers in the other mode. If there is illegal access on the application, mode mismatch interrupt will be generated and affect the corresponding bit (the MODMIS bit in the OTG_FS_GINTSTS register) in the controller interrupt register.
Page 611: Csr Register Mapping
AT32F415 Series Reference Manual ● Host channel register set ● Device mode register set ● Device global register set ● Device endpoint register set ● Power and clock gating register set ● Data FIFO (DFIFO) access register set Only controller global register, Power and clock gating register, data FIFO access register, and host port control and status register are valid in both host mode and device mode.
Page 612: Table 21- 1 Controller Global Control And Status Register (Csrs)
AT32F415 Series Reference Manual Global CSR address mapping These registers are valid both in host mode and device mode . Table 21- 1 Controller Global Control and Status Register (CSRs) Register Code Offset address Register Name OTG_FS_GAHBCFG 0x008 OTG_FS AHB Configuration Register...
Page 613: Table 21- 3 Device Mode Control And Status Register
AT32F415 Series Reference Manual Device mode CSR address mapping These registers should be configured every time when switching to the device mode. Table 21- 3 Device Mode Control and Status Register Register Code Offset address Register Name OTG_FS_DCFG 0x800 OTG_FS Device Configuration Register...
Page 614: Table 21- 4 Data Fifo (Dfifo) Access Register
AT32F415 Series Reference Manual Table 21- 4 Data FIFO (DFIFO) Access Register Data FIFO (DFIFO) access register Address Range Access Device IN endpoint 0/Host OUT channel 0: DFIFO write-only write access 0x1000~0x1FFC Device OUT endpoint 0/Host IN channel 0: DFIFO read-only...
Page 615: Otg_Fs Register Address Mapping
AT32F415 Series Reference Manual 21.14.2 OTG_FS Register Address Mapping Table 21-6 shows the USB OTG register mappings and reset values. Table 21- 6 OTG_FS Register Mapping and Reset Values Offset Register OTG_FS_GAHBCFG 008h Reserved Reserved Reset Value OTG_FS_GUSBCFG TRDTIM 00Ch...
Page 616 AT32F415 Series Reference Manual OTG_FS_GRXFSIZ RXFDEP 024h Reserved Reset Value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_FS_GNPTXFSIZ NPTXFDEP NPTXFSTADDR 028h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0...
Page 617 AT32F415 Series Reference Manual OTG_FS_HCCHAR2 DEVADDR EPTNUM MAXPSIZE 540h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 618 AT32F415 Series Reference Manual Offset Register OTG_FS_HCINT6 5C8h Reserved Reset Value 0 0 0 0 0 0 0 OTG_FS_HCINT7 5E8h Reserved Reset Value 0 0 0 0 0 0 0 OTG_FS_HCINTMSK0 50Ch Reserved Reset Value 0 0 0 0 0 0 0 0...
Page 619 AT32F415 Series Reference Manual Offset Register OTG_FS_DCFG DEVADDR 800h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DCTL TSTCTRL 804h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0...
Page 620 AT32F415 Series Reference Manual Offset Register OTG_FS_DIEPCTL2 TXFNUM MAXPSIZE 940h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 621 AT32F415 Series Reference Manual Offset Register OTG_FS_DIEPINT3 908h Reserved Reset Value OTG_FS_DOEPINT0 B08h Reserved Reset Value OTG_FS_DOEPINT1 B28h Reserved Reset Value OTG_FS_DOEPINT2 B48h Reserved Reset Value OTG_FS_DOEPINT3 B68h Reserved Reset Value PKTC OTG_FS_DIEPTSIZ0 XFERSIZE 910h Reserved Reserved Reset Value 0 0 0 0 0 0 0...
Page 622: Otg_Fs Global Registers
AT32F415 Series Reference Manual 21.14.3 OTG_FS Global Registers These registers are Accessible in both device mode and host mode, and do not need re-initialization when switching to different modes. If there is no special notes, every bit value in the registers is shown in a binary manner.
Page 623: Otg_Fs_Usb Configuration Register (Otg_Fs_Gusbcfg)
AT32F415 Series Reference Manual 21.14.5 OTG_FS_USB Configuration Register (OTG_FS_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 0A00 This register is used to configure core during power-on or core mode switch. It mainly configures USB and USB PHY relevant parameters. The application should configure this register first before transferring data to AHB or USB.
Page 624: Otg_Fs Reset Register (Otg_Fs_Grstctl)
AT32F415 Series Reference Manual USB specification defines that full-speed packet timeout standard is 16-bit to 18-bit times. The application should set this bit according to speed of enumeration. The added bit time of PHY clock is 0.25-bit times. 21.14.6 OTG_FS Reset Register (OTG_FS_GRSTCTL)
Page 625: Otg_Fs Core Interrupt Register (Otg_Fs_Gintsts)
AT32F415 Series Reference Manual current transaction and turn to idle state, and clearing the CSR control bits in the status device driven by AHB clock field. To clear this interrupt, the status mask bit generated for control interrupt status and AHB clock field driven device will be cleared.
Page 626 AT32F415 Series Reference Manual Reserved rc_w1 WKUPINT: Resume/remote wakeup detected interrupt In device mode, this interrupt is generated when detecting resume signal on USB; in Bit 31 host mode, this interrupt is generated when detecting remote wakeup signal on USB.
Page 627 AT32F415 Series Reference Manual Note: Accessible only in device mode IEPTINT: IN endpoint interrupt In device mode, the core sets this bit to indicate that there is a pending IN endpoint event. The application needs to read device all endpoint interrupt register...
Page 628: Otg_Fs Interrupt Mask Register (Otg_Fs_Gintmsk)
AT32F415 Series Reference Manual Note: Accessible in both device mode and host mode OTGINT: OTG interrupt The core sets this bit to indicate that an OTG protocol event occurs. The application must read the OTG interrupt register (OTG_FS_GOTGINT) to get the detailed Bit 2 information of the generated interrupt.
Page 629 AT32F415 Series Reference Manual Bit 27 Reserved PTXFEMPM: Periodic TX FIFO empty mask 0: Mask interrupts Bit 26 1: Unmask interrupts Note: Accessible only in host mode HCHINTM: Host channels interrupt mask 0: Mask interrupts Bit 25 1: Unmask interrupts...
Page 630: Otg_Fs Rx Status Debug Read/Otg Status Read And Pop Register
AT32F415 Series Reference Manual 1: Unmask interrupts Note: Accessible only in device mode GINNAKEFFM: Global non-periodic IN NAK effective mask 0: Mask interrupts Bit 6 1: Unmask interrupts Note: Accessible only in device mode NPTXFEMPM: Non-periodic TX FIFO empty mask...
Page 631 AT32F415 Series Reference Manual 0101: Data reverse bit error (trigger interrupt) 0111: Channel stops. (trigger interrupt) Others: Reserved DPID: Data PID It indicates the data PID of received data packet. 00: DATA0 Bit 16:15 10: DATA1 01: DATA2 11: MDATA...
Page 632: Otg_Fsrx Fifo Size Register (Otg_Fs_Grxfsiz)
AT32F415 Series Reference Manual 21.14.10 OTG_FSRX FIFO Size Register (OTG_FS_GRXFSIZ) Address offset: 0x024 Reset value: 0x0000 0200 The application can define the RAM size for the RX FIFO. Reserved RXFDEP r/rw Bit 31:16 Reserved RXFDEP: RX FIFO depth This value is expressed in 32-bit words.
Page 633: Otg_Fs Non-Periodic Tx Fifo/Request Queue Status Register
AT32F415 Series Reference Manual 21.14.12 OTG_FS Non-periodic TX FIFO/Request Queue Status Register (OTG_FS_GNPTXSTS) Address offset: 0x02C Reset value: 0x0008 0200 Note: In device mode, this register is invalid. This register is read-only; it stores the space available information of non-periodic TX FIFO and non-periodic transfer request queue.
Page 634: Otg_Fs General Core Configuration Register (Otg_Fs_Gccfg)
AT32F415 Series Reference Manual 21.14.13 OTG_FS General Core Configuration Register (OTG_FS_GCCFG) Address offset: 0x038 Reset value: 0x0000 0000 Reserved Reserved Bit 31:21 Reserved SOFOUTEN: SOF output enable Bit 20 0: Not to output SOF pulse 1: Output SOF pulse to the pin VBUSBSESEN: Enable the VBUS sensing “B”...
Page 635: Otg_Fs Core Id Register (Otg_Fs_Guid)
AT32F415 Series Reference Manual 21.14.14 OTG_FS Core ID Register (OTG_FS_GUID) Address offset: 0x03C Reset value: 0x0000 1000 This register is read-only to protect product ID. USERID USERID USERID: Product ID field Bit 31:0 The application can program this ID field.
Page 636: (Where N Is Fifo Number, N = 1
AT32F415 Series Reference Manual 21.14.16 OTG_FS Device IN Endpoint TX FIFO Size Register (OTG_FS_DIEPTXFn) (where n is FIFO number, n = 1...4) Address offset: 0x104 + (FIFO number － 1) × 0x04 Reset value: 0x0200 0400 INEPTXFDEP r/rw INEPTXSTADDR r/rw INEPTXFDEP: IN endpoint TX FIFO depth This value is expressed in 32-bit words.
Page 637: Otg_Fs Host Frame Interval Register (Otg_Fs_Hfir)
AT32F415 Series Reference Manual FSLSPCLKS: FS/LS PHY clock select When core is in full-speed host mode: 01: PHY clock operates at 48 MHz. Others: Reserved When core is in low-speed host mode: 00: Reserved Bit 1:0 01: PHY clock operates at 48 MHz.
Page 638: Otg_Fs Host Periodic Tx Fifo/Request Queue Register
AT32F415 Series Reference Manual FTAREM: Frame time remaining It indicates the time remaining in current frame, expressed in the number of PHY Bit 31:16 clocks. This value is automatically decreased by 1 at every PHY clock. When this value becomes 0, the value defined in the frame interval register will be automatically loaded to this register and transmit a new SOF to USB.
Page 639: Otg_Fs Host All Channel Interrupt Register (Otg_Fs_Haint)
AT32F415 Series Reference Manual 21.14.22 OTG_FS Host All Channel Interrupt Register (OTG_FS_HAINT) Address offset: 0x414 Reset value: 0x0000 0000 When a channel generates flag events, the host channel interrupt bit in this register (the HCINT bit in the OTG_FS_GINTSTS register) will interrupt the application; please refer to Figure 21-9 for more information.
Page 640 AT32F415 Series Reference Manual bit indicating rc_w1 can trigger interrupt to stop the application by the host port interrupt bit in the host interrupt register (the HPRTINT bit in the OTG_FS_GINTSTS register). During port interrupt procedure, the application should read this register and clear the bit that causes interrupt. For bit indicating rc_w1, the application needs to write 1 to clear interrupt.
Page 641 AT32F415 Series Reference Manual PRTSUSP: Port suspend The application can set this bit to make the port enter suspend state. At this state, the core only stops transmitting SOF signal. The application stops PHY clock by the configuring the port clock stop bit. Read accesses to this bit will return current port suspend state.
Page 642: Otg_Fs Host Channel X Characteristic Register (Otg_Fs_Hccharx)
AT32F415 Series Reference Manual 21.14.25 OTG_FS Host Channel x Characteristic Register (OTG_FS_HCCHARx)(where x is channel number, x = 0...7) Address offset: 0x500 + (channel number × 0x20) Reset value: 0x0000 0000 DEVADDR MCNT EPTNUM MAXPSIZE CHENA: Channel enable This bit is set by application and cleared by FS_OTG host core.
Page 643: Otg_Fs Host Channel X Interrupt Register (Otg_Fs_Hcintx)
AT32F415 Series Reference Manual EPTYPE: Endpoint type It indicates the selected transaction type. 00: Control transfer Bit 19:18 01: Isochronous transfer 10: Bulk transfer 11: Interrupt transfer LSPDDEV: Low speed device Bit 17 The application sets this bit to indicate that the device is low-speed device.
Page 644: Otg_Fs Host Channel X Interrupt Mask Register (Otg_Fs_Hcintmskx)
AT32F415 Series Reference Manual 21.14.27 OTG_FS Host Channel x Interrupt Mask Register (OTG_FS_HCINTMSKx)(where x is channel number, x = 0...7) Address offset: 0x50C + (channel number × 0x20) Reset value: 0x0000 0000 This register is used to mask various channel interrupts mentioned in the last section.
Page 645: Otg_Fs Host Channel X Transfer Size Register (Otg_Fs_Hctsizx)
AT32F415 Series Reference Manual 21.14.28 OTG_FS Host Channel x Transfer Size Register (OTG_FS_HCTSIZx)(where x is channel number, x = 0...7) Address offset: 0x510 + (channel number × 0x20) Reset value: 0x0000 0000 DPID PKTCNT XFERSIZ XFERSIZ Bit 31 Reserved DPID: Data PID The application informs the core of the PID type used in the initial transaction by this bit.
Page 646: Otg_Fs Device Control Register (Otg_Fs_Dctl)
AT32F415 Series Reference Manual It indicates the percentage of generated periodic frame completed interrupt time in the whole frame. The application can judge whether isochronous transaction in a frame is fully completed by this interrupt. 00: 80% of frame time...
Page 647: Otg_Fs Device Status Register (Otg_Fs_Dsts)
AT32F415 Series Reference Manual NAK effective bit in the core interrupt register (the GINAKEFF bit in the OTG-FS_GINTSTS register) is cleared. TSTCTRL: Test control 000: Test mode is disable. 001: Test_J mode 010: Test_K mode Bit 6:4 011: Test_SE0_NAK mode...
Page 648: Otg_Fs Device In Endpoint General Interrupt Mask Register
AT32F415 Series Reference Manual Reserved SOFFN Bit 31:22 Reserved Bit 21:8 SOFFN: Frame number of the received SOF Bit 7:4 Reserved ETICERR: Erratic error The core sets this bit when erratic error occurs. If erratic error occurs, the OTG_FS core will enter suspend state and set early suspend in the core interrupt register.
Page 649: Otg_Fs Device Out Endpoint General Interrupt Mask Register
AT32F415 Series Reference Manual TXFIFOUDRM: FIFO underrun mask Bit 8 0: Mask interrupts 1: Unmask interrupts Bit 7 Reserved INEPTNEM: IN endpoint NAK effective mask Bit 6 0: Mask interrupts 1: Unmask interrupts INEPTNMISM: IN token received with EP mismatch mask...
Page 650: Otg_Fs Device All Endpoint Interrupt Register (Otg_Fs_Daint)
AT32F415 Series Reference Manual Bit 7 Reserved B2BSETUP: Back-to-back SETUP packets received mask Bit 6 0: Mask interrupts 1: Unmask interrupts Bit 5 Reserved OUTTEPDM : OUT token received when endpoint disabled mask Bit 4 0: Mask interrupts 1: Unmask interrupts...
Page 651: Otg_Fs Device All Endpoint Interrupt Mask Register
AT32F415 Series Reference Manual 21.14.36 OTG_FS Device All Endpoint Interrupt Mask Register (OTG_FS_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The device all endpoint interrupt mask register is used with the device endpoint interrupt register. When device endpoint events occur, it generates interrupt to stop application. However, the corresponding bits in the device all endpoint interrupt register (OTG_FS_DAINT) is still set when being masked.
Page 652: Otg_Fs Device Control In Endpoint 0 Control Register (Otg_Fs_Diepctl0)
AT32F415 Series Reference Manual 21.14.38 OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) Address offset: 0x900 Reset value: 0x0000 0000 This section describes device control IN endpoint 0 control register. Non-0 control endpoint uses the corresponding endpoint 1-15 registers.
Page 653: Otg_Fs Device Endpoint X Control Register (Otg_Fs_Diepctlx)
AT32F415 Series Reference Manual USBAEPT: USB active endpoint Bit 15 Always ‘1’ to indicate that control port 0 is always active under any configuration. Bit 14:2 Reserved MAXPSIZE: Maximum packet size The application sets the maximum packet size through this bit.
Page 654 AT32F415 Series Reference Manual CNAK: Clear NAK Bit 26 Writing this bit will clear endpoint NAK status. TXFNUM: TX FIFO number Bit 25:22 This bit sets the FIFO number assigned to the endpoint. Every valid IN endpoint should be assigned with an FIFO number. This bit is only valid to IN endpoint.
Page 655: Otg_Fs Device Control Out Endpoint 0 Control Register (Otg_Fs_Doepctl0)
AT32F415 Series Reference Manual 21.14.40 OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) Address offset: 0xB00 Reset value: 0x0000 8000 This section describes device control OUT endpoint 0 control register. Non-0 endpoint control uses the corresponding endpoint 1-15 control register.
Page 656: Otg_Fs Device Out Endpoint X Control Register (Otg_Fs_Doepctlx)
AT32F415 Series Reference Manual Bit 14:2 Reserved MAXPSIZE: Maximum packet size Data packet size of control OUT endpoint 0 should be consistent with the data packet size od control IN endpoint 0. Bit 1:0 00: 64 bytes 01: 32 bytes...
Page 657 AT32F415 Series Reference Manual CNAK: Clear NAK Bit 26 Writing this bit will clear the NAK status of the endpoint. Bit 25:22 Reserved STALL: STALL handshake Only valid to non-control and non-isochronous OUT endpoint (the operation type is rw.) After the application sets this bit, the endpoint will response all commands from the host with STALL.
Page 658: Otg_Fs Device Endpoint X Interrupt Register (Otg_Fs_Diepintx)
AT32F415 Series Reference Manual 21.14.42 OTG_FS Device Endpoint x Interrupt Register (OTG_FS_DIEPINTx)(where x is endpoint number, x = 0...3) Address offset: 0x908 + (endpoint number x 0x20) Reset value: 0x0000 0080 This register indicates the USB and AHB relevant event status that corresponds to the endpoint.
Page 659 AT32F415 Series Reference Manual 21.14.43 OTG_FS Device Endpoint x Interrupt Register (OTG_FS_DOEPINTx)(where x is endpoint number, x = 0...3) Address offset: 0xB08 + (endpoint number x 0x20) Reset value: 0x0000 0080 This register indicates the USB and AHB relevant event status that corresponds to the endpoint.
Page 660: Otg_Fs Device In Endpoint 0 Transfer Size Register (Otg_Fs_Dieptsiz0)
AT32F415 Series Reference Manual 21.14.44 OTG_FS Device IN Endpoint 0 Transfer Size Register (OTG_FS_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must configure this register before enabling the endpoint 0. Once the endpoint 0 is enabled by the endpoint 0 enable bit (the OTG_FS_DIEPCTL0 Register, the EPENA Bit) of the device control endpoint 0 control register, this register can only be modified by the core.
Page 661: Otg_Fs Device Out Endpoint 0 Transfer Size Register (Otg_Fs_Doeptsiz0)
AT32F415 Series Reference Manual 21.14.45 OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) Address offset: 0xB10 Reset value: x0000 0000 The application must configure this register before enabling the endpoint 0. Once the endpoint 0 is enabled by the endpoint enable bit (the OTG_FS_DOEPCTL0 Register, the EPENA Bit) of the device control OUT endpoint 0 control register, this register can only be modified by the core.
Page 662: Otg_Fs Device Endpoint X Transfer Size Register
AT32F415 Series Reference Manual 21.14.46 OTG_FS Device Endpoint x Transfer Size Register (OTG_FS_DIEPTSIZx)(where x is endpoint number, x = 1...3) Address offset: 0x910 + (endpoint number x 0x20) Reset value: x0000 0000 The application must configure this register before enabling the endpoint. Once the endpoint is enabled by the endpoint enable bit (the OTG_FS_DIEPCTLx Register, the EPENA Bit) of the device endpoint x control register, this register can only be modified by the core.
Page 663: Otg_Fs Device In Endpoint Tx Fifo Status Register (Otg-Fs_Dtxfstsx)
AT32F415 Series Reference Manual 21.14.47 OTG_FS Device IN Endpoint TX FIFO Status Register (OTG- FS_DTXFSTSx)(where x is endpoint number, x = 0...3) Address offset: 0x918 + (endpoint number x 0x20) space avail This register is a read-only register for storing the device IN endpoint TX FIFO information.
Page 664 AT32F415 Series Reference Manual 11: 3 packets PKTCNT: Packet count It indicates the USB packet numbers to be transferred at the endpoint. Bit 28:19 Every time when the core writes data to RX FIFO from memory, this field is automatically decremented.
Page 665: Otg_Fs Programming Model
AT32F415 Series Reference Manual 21.15 OTG_FS Programming Model 21.15.1 Core Initialization The application should initialize core in sequence. At power-on state, USB is connected, and the current operation mode bit in the core interrupt register (the CURMOD bit in the OTG_FS_GINTSTS register) will indicate the current operation mode.
Page 666: Device Mode Initialization
AT32F415 Series Reference Manual 21.15.3 Device Mode Initialization The application should follow the steps below to initialize core during power-on or when switching from host mode to device mode, to make the core work in device mode: 1. Configure the following bits in the OTG_FS_DCFG register: ─...
Page 667 AT32F415 Series Reference Manual disabled) before re-assign this channel to other communications. OTG_FS host core cannot stop transactions that have already started on USB. Before disabling channels, the application needs to ensure that at least one space is still available in non-periodic request queue (when non-periodic channel is to be disabled), or in periodic request queue (when periodic channel is to be disabled).
Page 668: Figure 21- 11 Tx Fifo Write Task
AT32F415 Series Reference Manual Figure 21- 11 TX FIFO Write Task Read the GNPTXSTS/ start HPTXSIZ register to get available FIFO and queue space 1 MPS or Wait for the LPS FIFO space NPTXFEMP/PTXFEMP interrupt in the OTG_FS_GINTSTS available？ Write 1 data message...
Page 669: Figure 21- 12 Rx Fifo Read Task
AT32F415 Series Reference Manual Figure 21- 12 RX FIFO Read Task Start RXFLVL interrupt？ Mask RXFLVL Mask RXFLVL Disable mask RXFLVL interrupt interrupt interrupt Read received data message Read from RX FIFO OTG_FS_GRXSTSP PKTSTS 0b0010？是 BCNT ＞ 0？ Bulk and control OUT/SETUP Figure 21-13 shows the typical bulk transaction or control transaction OUT/SETUP procedure.
Page 670: Figure 21- 13 Normal Bulk/Control Out/Setup And In Transaction Procedure
AT32F415 Series Reference Manual Figure 21- 13 Normal Bulk/Control OUT/SETUP and IN Transaction Procedure Application Host Device init_reg(ch_1) Non-periodic request queue init_reg(ch_2) Assumed that this queue can take four requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) write_tx_fifo ch_2 (ch_1) set_ch_en ch_1...
Page 671 AT32F415 Series Reference Manual else if (STALL) Transfer Done = 1 Unmask CHHLT Disable Channel else if (NAK or XACTERR) Rewind Buffer Pointers Unmask CHHLT Disable Channel if (XACTERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLT)
Page 672 AT32F415 Series Reference Manual else if (CHHLT) Mask CHHLT if (Transfer Done or (Erro_Count == 3)) De-allocate Channel else Re-initialize channel else if (ACK) Reset Error Count Mask ACK else if (DTGERR) Reset Error Count The application should wait until XFERC event occurs to write request when request queue has space available.
Page 673: Figure 21- 14 Bulk/Control In Transaction Procedur E
AT32F415 Series Reference Manual Figure 21- 14 Bulk/Control IN Transaction Procedure Device Application Host init_reg(ch_1) Non-periodic request queue init_reg(ch_2) Assume that this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) write_tx_fifo ch_2 (ch_1) set_ch_en ch_1 (ch_2) ch_2 DAT A0...
Page 674 AT32F415 Series Reference Manual g) The application reads received data packet status; if it is not an IN data packet (which means the PKTSTS bit ≠0x0010 in the RXSTSR register), then ignore it. h) The core generates XFERC interrupt after the receive data packet status is read.
Page 675: Figure 21- 15 Normal Interrupt Out/In Transaction P Rocedure
AT32F415 Series Reference Manual Figure 21- 15 Normal Interrupt OUT/IN Transaction Procedure Application Host Device init_reg(ch_1) Periodic request queue init_reg(ch_2) Assumed that this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) ch_2 Odd （micro） frame DAT A0 XFERC interrupt...
Page 676 AT32F415 Series Reference Manual Unmask CHHLT Disable Channel if (STALL) Transfer Done = 1 else if (NAK or XACTERR) Reset Buffer Pointer Reset Error Count Mask ACK Unmask CHHLT Disable Channel else if (CHHLT) Mask CHHLT if (Transfer Done or (Erro_Count == 3))
Page 677 AT32F415 Series Reference Manual if (STALL or BBLERR) Reset Error Count Transfer Done = 1 else if (！FRMOVR) Reset Error Count else if (XACTERR) Increment Error Count Unmask ACK Unmask CHHLT Disable Channel else if (CHHLT) Mask CHHLT if (Transfer Done or (Erro_Count == 3))
Page 678 AT32F415 Series Reference Manual f) During RXFLVL interrupt procedure, the application reads received packet status to know the received byte number and read the corresponding RX FIFO. Before reading the RX FIFO, the RXFLVF interrupt should be masked, and enable the RXFLVL interrupt after complete packet is read.
Page 679: Figure 21- 16 Normal Isochronous Out/In Transaction Procedure
AT32F415 Series Reference Manual Figure 21- 16 Normal Isochronous OUT/IN Transaction Procedure Application Host Device init_reg(ch_1) Periodic request queue init_reg(ch_2) Assume this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) ch_2 Odd (micro) frame DAT A0 XFERC interrupt...
Page 680 AT32F415 Series Reference Manual Unmask CHHLT Disable Channel else if(CHHLT) Mask CHHLT De-allocate Channel Code sample: Isochronous IN Unmask (XACTERR/XFERC/FRMOVR/BBLERR) if (XFERC or FRMOVR) if (XFERC and OTG_FS_HCTSIZx.PKTCNT == 0) Reset Error Count De-allocate Channel else Unmask CHHLT Disable Channel...
Page 681 AT32F415 Series Reference Manual MCNT bit in the OTG_FS_HCCHAR2 register before switching to other channels (to specify the maximum number of packets to be received at the next frame). c) Every time when the application configures the CHENA bit in the OTG_FS_HCCHAR2 register, the core writes an IN request to periodic request queue.
Page 682: Device Mode Programming Model
AT32F415 Series Reference Manual 21.15.5 Device Mode Programming Model Endpoint initialization at USB reset: 1. Set all OUT endpoints to NAK status ─ Set the SNAK bit to ’1’ in the OTG_FS_DOEPCTLx (all OUT endpoints) register 2. Unmask the following interrupt bits: ─...
Page 683: Operation Model
AT32F415 Series Reference Manual 6. After configuring all endpoints, the application needs to make the core transmit a status IN packet. At this time, the core is ready for transmitting or receiving data packets in device mode. Endpoint activation Activating an endpoint or configuring an existing endpoint configure to a new type should follow the steps below: 1.
Page 684: Figure 21- 17 Reading Rx Fifo Data Message In Slave Mode
AT32F415 Series Reference Manual e) Data phase completed mode: PKTSTS = data OUT phase completed, BCNT = 0x0, EPTNUM = endpoint number of OUT endpoint data transaction, DPID = don’t care (0x0) The data indicates that OUT data phase of the defined OUT endpoint is completed. After this message is popped from RX FIFO, the core will generate a transfer completed interrupt of the specified OUT endpoint.
Page 685 AT32F415 Series Reference Manual ─ The required space is 10 DWORD. 3 DWORD space for the first SETUP packet, 1 DWORD space for SETUP phase complete message, and the other 6 DWORD space for storing the other two extra SETUP packet of control endpoint.
Page 686: Figure 21- 18 Processing A Setup Data Message
AT32F415 Series Reference Manual Figure 21- 18 Processing a SETUP Data Message Wait for STUP in OTG_FS_DOEPINTx rem_supcnt = rd_reg(DOEPTSIZx) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[63:32] = mem[5-2* rem_supcnt] Look for Setup Command read write type ctrl-rd/wr/2 phase 2-阶段 setup_np_in_pkt setup_np_in_pkt...
Page 687 AT32F415 Series Reference Manual ─ GINNAKEFFM = 0 in the GINTMSK register 5. Once it is required to exit global OUT NAK mode，the SGOUTNAK bit in the OTG_FS_DCTL register can be cleared. This operation will clear the GOUTNAKEFF (OTG_FS_GINTSTS) interrupt.
Page 688 AT32F415 Series Reference Manual PID number; under this condition, the packet number bit in the register will not be automatically decreased. ─ If RX FIFO does not have space available, isochronous or non-isochronous data packet will be dropped and not written into RX FIFO. In addition, for non-isochronous OUT data packet, NAK handshake signal will be transmitted.
Page 689 AT32F415 Series Reference Manual ─ EONUM (the OTG_FS_DOEPCTLx Register) = SOFFN[0](the OTG_FS_DSTS Register) 3. After reading complete isochronous OUT data packet (including data and status) from the RX FIFO, the core will update the RXDPID bit in the OTG_FS_DOEPTSIZx register based on the last read isochronous OUT data packet in the RX FIFO.
Page 690 AT32F415 Series Reference Manual ─ After the application reads and empties the RX FIFO, it generates XFERC interrupt (OTG_FS_DOEPINTx); at this time, endpoint needs to be re-enabled to receive isochronous OUT data in the next frame. 3. When detecting INCOMISOOUTM interrupt (OTG_FS_GINTSTS), all isochronous OUT endpoint control register (OTG_FS_DOEPCTLx) should be read to check which endpoint has incomplete transfer in the current frame.
Page 691: Figure 21- 19 Bulk Out Transaction
AT32F415 Series Reference Manual Figure 21- 19 Bulk OUT Transaction Host Device Application init_out_ep XFERSIZE = 512 bytes PKTCNT = 1 wr_reg(DOEPTSIZx) XFERSIZE = 512 bytes PKTCNT = 1 wr_reg(DOEPTCTLx) 512 bytes xact_1 RXFLVL interrupt Idle until interrupt rcv_out_pkt() XFERSIZE = 0...
Page 692 AT32F415 Series Reference Manual FIFO. Usually, except for configuring endpoint enable bit, the application must configure the OTG_FS_DIEPCTLx register by read-modify-write operation to prevent register content from being changed. If TX FIFO has sufficient space available, it is allowed to write several data packets to the same endpoint consecutively.
Page 693 AT32F415 Series Reference Manual 6. The application must read periodic IN endpoint OTG_FS_DIEPTSIZx register to know how much data the endpoint has transmitted to USB. 7. The application needs to configure the following bits in the OTG_FS_GRSTCTL register to clear data in the endpoint TX FIFO: ─...
Page 694 AT32F415 Series Reference Manual 4. After data is written into TX FIFO, the core reads the data after receiving IN token. For every non-isochronous IN data packet transfer ended with ACK, the endpoint packet number register will be automatically decreased by 1, until the packet number turns to 0. The packet number register will be automatically decreased because of timeout.
Page 695 AT32F415 Series Reference Manual 3. All data that should be transmitted within a frame must be written into TX FIFO before receiving IN token. For data that should be transmitted within a frame, even if there is only one DWORD not written to TX FIFO, the core will still regard FIFO as empty.
Page 696 AT32F415 Series Reference Manual ● Incomplete isochronous IN data transaction This section describes how the application process internal data when there is incomplete isochronous IN transfer: 1. When any of the following condition occurs, it is regarded as isochronous IN transfer incomplete: ─...
Page 697: Worst Case Response Time
AT32F415 Series Reference Manual 6. When application sets or clears the STALL bit based on SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, configuration to the STALL bit must be done before status transfer phase is established at the control endpoint.
Page 698: Figure 21- 20 Trdtim Under Maximum Time Sequence
AT32F415 Series Reference Manual Figure 21- 20 TRDTIM under Maximum Time Sequence 50ns 100ns 150ns 200ns HCLK PCLK tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 clock cycles 2020.06.28 Page 698 Version 1.02...
Page 699: Revision History
AT32F415 Series Reference Manual 22 Revision History Table 22- 1 Document Revision History Date Version Revision Note 2018.08.12 1.00 Original version 1.Updated front page function descriptions 2018.08.23 1.01 2.Updated Figure 19-14 3.Corrected typos 1. Added the description of PLL configuration mode in 3.2.3 section 2020.6.28...
Page 700 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third party’s products or services...

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