HP Vectra XU5 Reference Manual

Hardware and bios technical reference

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Supplementary manual (48 pages)

Getting started manual (59 pages)

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Vectra XU Hardware and BIOS Technical Reference

Manual

Trademarks

Printed Manual Information

Introduction

Preface

Conventions

Ordering Information for the Phoenix BIOS Manual

Bibliography

System Overview

Introduction

PCI Local Bus Architecture

System Block Diagram

Principal Components and Features

System Board

Processor

Superscalar Architecture

Floating Point Unit (FPU)

Dynamic Branch Prediction

Instruction and Data Cache

Data Integrity

PCI Chip Set

PCI, Cache, and Memory Controller (PCMC)

Local Bus Accelerator (LBX)

The PCI/ISA Bridge (PCEB and ESC)

Super I/O Chip Set

Flexible Drive Controller (FDC)

Serial/Parallel Ports

Graphics/Integrated Video

Video Controller

Video Clock Generator

Video Resolutions Supported

PCI LAN/SCSI-2 Controller

IDE to PCI Controller

Flash ROM

Security Features

System Specifications

Physical Characteristics

Electrical Specifications

Environmental Specifications

Summary of the HP BIOS

Overview

Overview of Address Space

I/O Addresses Used by the System

System Memory Map

Vectra XU Technical Reference

Introduction

Table of Contents

Summary of Contents for HP Vectra XU5

Page 1 IDE to PCI Controller Flash ROM Security Features System Specifications Physical Characteristics Electrical Specifications Environmental Specifications Summary of the HP BIOS Overview Overview of Address Space I/O Addresses Used by the System System Memory Map Vectra XU Technical Reference Introduction...
Page 2 Machine Capability and Extension of Capability Markers BIOS Version Number Year of the ROM BIOS Release Week of the ROM BIOS Release HP BIOS I/O Port Map Addressing System Board Components Interrupt Controllers PCI Interrupt Request Lines The Integrated Ultra VGA Controller...
Page 3 Trademarks Centronics® is a registered trademark of Centronics Data Computer Corporation. Microsoft® and MS-DOS® are U.S. registered trademarks of Microsoft Corporation. LANManager, Microsoft Windows and OS/2 are products of Microsoft Corporation. Novell® and NetWare® are U.S. registered trademarks of Novell, Inc. Pentium™...
Page 4 Printed Manual Information Printed in France, April 1995 HP Part Number D3080-90911, Edition 2 Vectra XU Technical Reference Introduction...
Page 5 Introduction Vectra XU Technical Reference Introduction...
Page 6 Preface This manual is a technical reference and BIOS document for engineers and technicians who provide system level support, or who are engaged in the design of system-compatible products. It is assumed that the reader possesses a fairly detailed understanding of AT- compatible microprocessor functions and digital addressing techniques.
Page 7 Conventions The following conventions are used throughout this manual to identify specific elements: Hexadecimal numbers are identified by a lower case h. For example, 0FFFFFFFh or 32F5h Binary numbers and binary bit patterns are identified by a lower case b. For example, 11101b or 1001011b Vectra XU Technical Reference Introduction...
Page 8: Ordering Information For The Phoenix Bios Manual
Ordering Information for the Phoenix BIOS Manual System BIOS for IBM PCs, Compatibles, and EISA Computers (ISBN 0-201-57760-7) by Phoenix Technologies is available in many bookstores. It can also be ordered directly from the publisher as follows: In the U.S.A. Call Addison-Wesley in Massachusetts at +1-800-447-2226, and be prepared to give a credit card number and expiry date.
Page 9 Phoenix Technologies. Addison-Wesley (publisher) The following Hewlett Packard publications may also assist the reader of this manual. HP Vectra XU PC Setting Up Your PC and Getting Started manuals (D3080B xxxxx, where xxxxx is the language option) HP Vectra XU PC Familiarization Guide (D308xA+49A+90001) HP Vectra PC Service Handbook (5963-6104) The following Intel®...
Page 10: System Overview
System Overview Vectra XU Technical Reference System Overview...
Page 11 Introduction This chapter provides a description of the HP Vectra XU PC Series, and includes detailed system specifications. Vectra XU Technical Reference System Overview...
Page 12 PCI Local Bus Architecture This HP Vectra PC uses the PCI local bus architecture. The PCI (Peripheral Component Interconnect) architecture lets system devices operate at speeds approaching that of the processor and removes the data transfer bottleneck imposed by the ISA, EISA, and MCA buses.
Page 13: System Block Diagram
System Block Diagram Vectra XU Technical Reference System Overview...
Page 14: Principal Components And Features
Principal Components and Features The HP Vectra XU PC is an ISA/PCI-based PC and features the Pentium&TM; microprocessor and the 82430 chip set. Vectra XU Technical Reference System Overview...
Page 15 PCI bus video controller: the HP Vectra XU 5/75 and XU 5/90 has an integrated Ultra VGA+ video controller on the PCI bus with 2 MB of video memory (for 1280 x 1024 resolution in 256 colors) the HP Vectra XU 5/90C and XU 5/100C do not have an integrated video controller.
Page 16 a keyboard/mouse controller and interface one serial connector and one parallel connector--for attaching peripherals an integrated 16-bit Ethernet interface, configurable from SETUP a system board mounted LAN connector (UTP) and link beat LED a system board mounted Coax LAN connector Vectra XU Technical Reference System Overview...
Page 17 Processor The Pentium processor uses 64-bit architecture and is 100% compatible with Intel's family of x86 microprocessors. All application software that has been written for Intel 386 and Intel 486 microprocessors can run on the Pentium without any modification. It contains all the features of the Intel 486 microprocessor, with the following features added to enhance performance: Superscaler Architecture...
Page 18 Superscalar Architecture The Pentium processor's superscaler architecture has two instruction pipelines and a floating-point unit, each capable of independent operation. The two pipelines let the Pentium execute two integer instructions, in parallel, in a single clock cycle. Using the pipelines halves the instruction execution time and almost doubles the performance of the processor, compared to an Intel486 microprocessor of the same frequency.
Page 19 Floating Point Unit (FPU) The Floating Point Unit incorporates optimized algorithms and dedicated hardware for multiply, divide, and add functions. This increases the processing speed of common operations by a factor of three. Vectra XU Technical Reference System Overview...
Page 20 Dynamic Branch Prediction The Pentium processor uses dynamic branch prediction. To dynamically predict instruction branches, the processor uses two prefetch buffers. One buffer is used to prefetch code in a linear way and one to prefetch code depending upon the contents of the Branch Target Buffer (BTB).
Page 21 Instruction and Data Cache The Pentium processor has separate code and data caches on-chip. Each cache is 8 KB in size with a 32-bit line. The caches act as temporary storage for data and instructions from the main memory. As the system is likely to use the same data several times, it is faster to get it from the on-chip cache than from the main memory.
Page 22 Data Integrity The processor uses a number of techniques to maintain data integrity. It employs two methods of error detection: Data Parity Checking This is supported on a byte-by-byte basis, generating parity bits for data addresses sent out of the microprocessor. These parity bits can be checked by the external subsystems that will be using the data.
Page 23 PCI Chip Set The chip set consists of three devices: The PCI, Cache, and Memory Controller (PCMC) The Local Bus Accelerator (LBX) The PCI/ISA bridge (PCEB and ESC). The PCMC and LBX provide the core cache and memory system architecture and PCI interface.
Page 24 PCI, Cache, and Memory Controller (PCMC) The 82434LX PCMC integrates cache and main memory control functions and provides bus control functions for the transfer of information between the microprocessor, cache, main memory and the PCI bus. The cache controller supports the Pentium Cache Write-Back mode and 256 KB of direct mapped Level Two cache using standard or burst SRAMs.
Page 25 Local Bus Accelerator (LBX) The two 82433LX LBX components provide the following data paths: 64-bit data path between the host bus and main memory 32-bit data path between the host microprocessor and the PCI local bus 32-bit data path between the PCI bus and the main memory. The dual port architecture permits concurrent operations on the host bus and the PCI bus.
Page 26 The PCI/ISA Bridge (PCEB and ESC) The PCEB and ESC serve as a bridge between the PCI local bus and the ISA expansion bus. They incorporate the logic for a PCI interface, an ISA interface, a DMA controller that supports fast DMA transfers, data buffers to isolate the PCI and ISA buses, Timer/Counter logic, and NMI control logic.
Page 27 Super I/O Chip Set The basic input/output control functions are provided by the Super I/O chip, PC87332VF. This chip set has the following features: an integrated flexible drive controller that supports 5.25-inch 360 KB and 1.2 MB drives, and 3.5-inch 1.44 MB and 2.8 MB drives a multi-mode parallel port one serial port.
Page 28 Flexible Drive Controller (FDC) The FDC is software and register compatible to the 82077AA and 100% IBM compatible. It has an A and B drive-swapping capability and a non-burst DMA option. Vectra XU Technical Reference System Overview...
Page 29 The parallel port can operate in three modes: Standard mode (PC/XT, PC/AT, and PS/2 compatible) Enhanced mode (Enhanced parallel Port (EPP) compatible) High speed mode (MS/HP Extended Capabilities Port (ECP) compatible). It can be programmed as LPT1 (378h, IRQ7), LPT2 (278h, IRQ5), or disabled with PC87332VF registers.
Page 30 Graphics/Integrated Video According to model, the video subsystem is composed of an Vision864 Graphical User Interface (GUI) accelerator for the PCI bus, a 64-bit true color RAMDAC and DRAM array, or it may have a Matrox Video Board. Refer to the documentation supplied with your Matrox Board.
Page 31 Video Controller The S3 Vision864 video controller offers full compatibility with VGA, CGA, HGC, and MDA. In addition, its features are enhanced beyond Super VGA by hardware that accelerates graphical user interface operation in environments such as Microsoft Windows® or OS/2 Presentation Manager.
Page 32 Video Clock Generator The PC uses an XXX as a video clock generator, providing the dot clock of up to 135 MHz and the memory clock for the video section. If the video mode required is greater than 135 MHz then the frequency doubler in the XXX DAC must be enabled by the BIOS driver. Vectra XU Technical Reference System Overview...
Page 33 Video Resolutions Supported A table detailing all the video resolutions supported can be found under "Video Modes". Vectra XU Technical Reference System Overview...
Page 34 PCI LAN/SCSI-2 Controller The LAN and SCSI-2 PCI devices are integrated in one chip. The PCI LAN controller supports the Ethernet LAN protocol. An UTP (Unshielded Twisted Pair) RJ-25 connector and a BNC coax connector are provided. The MAC address is stored in an EEPROM. The LAN remote start code in the system ROM allows the PC to start (boot) from either a Novell NetWare or LANManager server using the integrated Ethernet interface.
Page 35 IDE to PCI Controller This IDE to PCI controller implementation supports the full Enhanced IDE feature set. The BIOS uses the auto-detected drive geometry information to select the fastest configuration supported by the installed IDE drive. Supports data transfer rate of up to 12 MB/sec 32-bit Windows and DOS I/O transfers (many IDE controllers use Window's integral IDE driver which only supports 16-bit I/O transfers) Vectra XU Technical Reference...
Page 36 The PC uses one 256 KB x 8 Flash ROM and one 128 KB x 8 200 ns Flash ROM. In addition to the base HP BIOS, the Flash contains SETUP, video BIOS, error messages, and ISA and PCI initialization. During programming of the Flash ROM, the power supply switch and the reset button are disabled to prevent accidental interruption.
Page 37 Security Features The PC has many security features to protect stored data, to protect the SETUP configuration, and to prevent unauthorized operation of software applications: user password system administrator password screen blanking and keyboard lock keyboard lock timer communications port protection (ports can be disabled in SETUP) disk drive protection (disks can be disabled or "boot"...
Page 38: System Specifications
System Specifications Vectra XU Technical Reference System Overview...
Page 39: Physical Characteristics
Physical Characteristics System Processing Unit Weight: 24 lbs (11 kg) Dimensions: 16.1 inches (D) by 17.1 inches (W) by 6.6 inches (H) (41 cm by 44 cm 17 cm) Footprint: 2.1 sq ft (0.18 m sq) Keyboard Flat: 18 inches (W) by 7 inches (D) by 1.3 inches (H) (464 mm by 178 mm by 33 mm) Standing: 18 inches (W) by 7 inches (D) by 2 inches (H)
Page 40 Electrical Specifications Input voltage: The HP Vectra XU PC is equipped with a 120 W (rated), full range power supply. This power supply requires an input voltage in the following range: 90 Vac to 264 Vac at a frequency of 47 Hz to 63 Hz.
Page 41: Environmental Specifications
Environmental Specifications System Controller (with hard disk) Operating Temperature Recommended Operating Temperature Storage Temperature Over Temperature Shutdown Operating Humidity Storage Humidity Operating Altitude Storage Altitude NOTE Operating temperature and humidity range may vary depending upon the mass storage devices installed. High humidity levels can cause improper operation of disk drives.
Page 42 Summary of the HP BIOS Vectra XU Technical Reference Summary of the HP BIOS...
Page 43 Overview This chapter is a summary of the main features of the HP system BIOS. For a more detailed and general description of the system BIOS refer to the System BIOS for IBM PCs, Compatibles, and EISA Computers manual by Phoenix Technologies Ltd. Ordering information for this manual can be found in the preface.
Page 44: Overview Of Address Space
8-bit and 16-bit registers (called I/O ports) located in the various system components. When installing an accessory board, ensure that the I/O address space selected is in the free area of the space reserved for accessory boards (100h to 3FFh). Vectra XU Technical Reference Summary of the HP BIOS...
Page 45 Integrated I/O Controller 3B0h–3DFh Video Adapter 3E8h–3EFh Serial Port 3 3F0h–3F7h Primary Flexible Disk Drive Controller 3F8h–3F7h Serial Port 1 Refer to "HP BIOS I/O Port Map" for more detailed information. Vectra XU Technical Reference Summary of the HP BIOS...
Page 46: System Memory Map
Reserved memory used by accessory boards must be located in the area from C8000h to 0EFFFh. After the computer has booted via the LAN, the LAN boot ROM area (E0000 to F0000) is again freed for use by accessory boards. Vectra XU Technical Reference Summary of the HP BIOS...
Page 47: Product Identification
Product identification 10101100b Machine capability marker ppssh BIOS version number pp = primary number ss = secondary number ROM release year (since 1960) stored in BCD Week of the year stored in BCD 'HP' Computer ID Summary of the HP BIOS...
Page 48 Machine Capability and Extension of Capability Markers These bytes identify some of the features and capabilities of the computer. 0F000:00FBh = Machine capability marker Length = one byte Vectra XU Technical Reference Summary of the HP BIOS...
Page 49 Where pp = Primary version number and ss = Secondary version number For example, BIOS release A.01.05 would be expressed as: 0105 NOTE If you use DEBUG to look at the bytes, the numbers will be reversed ( Vectra XU Technical Reference Summary of the HP BIOS 05 01...
Page 50 Where yy is the difference between the current year and 1960 in BCD. For example, if the current year is 1990, you would enter 1990 minus 1960 which is 30h (when expressed in BCD). Vectra XU Technical Reference Summary of the HP BIOS...
Page 51 0F000:00FFh = Week of the ROM BIOS release in BCD. Length = one byte Encoded as follows: Where nn is the week in which the BIOS ROMs were released in BCD. The range is 00h to 51h. Vectra XU Technical Reference Summary of the HP BIOS...
Page 52 HP BIOS I/O Port Map This section describes the HP BIOS I/O port map. "Addressing System Board Components" provides more details on how the BIOS uses the system board components mentioned in the I/O port list. Within the port map: Reserved I/O addresses are reserved for HP private use.
Page 53 03BC–3BF Parallel Port 1 03E8–03EF Serial Port 3 03F0–03F7 Floppy Controller 03F8–03FF Serial Port 1 0CF8 PCI Configuration Address register 0CFC–0CFF PCI Configuration Data register Vectra XU Technical Reference Summary of the HP BIOS...
Page 54: Addressing System Board Components
Channel Function Available ECP mode for parallel port Flexible disk I/O Available Second DMA controller (used for 16 bit transfers): Channel Function Cascade from first DMA controller 5–6 Available 6–7 Available Vectra XU Technical Reference Summary of the HP BIOS...
Page 55 Available for accessory board (ISA/PCI) Available for accessory board (ISA/PCI) Available for accessory board (ISA/PCI) Mouse PENTIUM Available for accessory board (ISA/PCI) Serial port 2 Serial port 1 Available for accessory board (ISA/PCI) Flexible Disk Controller Parallel Port 1 Summary of the HP BIOS...
Page 56 All PCI devices with interrupt transfer support will use and share INTA#. A PCI device supporting multiple functionalities may support several INT lines (for example, the LAN/SCSI-2 controller uses INTA# and INTB#). These devices will also require more than one system interrupt request line. Vectra XU Technical Reference Summary of the HP BIOS...
Page 57 The Integrated Ultra VGA Controller Vectra XU Technical Reference The Integrated Ultra VGA Controller...
Page 58 Overview The HP Vectra XU 5/90C and XU 5/100C systems use either a Matrox MGA PCI/2+ or a Matrox Impression Plus Video board. These video boards are documented in an English- language manual supplied with the board. Matrox Electronic Systems Ltd.
Page 59: Video Memory
Video Memory 2 MB of Video DRAM is preinstalled on the system board. Vectra XU Technical Reference The Integrated Ultra VGA Controller...
Page 60: Video Modes
When the PC is operating in one of the enhanced modes, all accesses to the controller must be made with HP Ultra VGA drivers and utilities such as those supplied with the HP Vectra XU PC. For further details, refer to the README files that come with the utilities.
Page 61 VESA Enhanced Mode Interface Mode Type 10Ah text Applicable 109h text 101h text 101h text ergo 102h graphics 102h graphics ergo 103h graphics 103h graphics ergo 104h graphics 104h graphics ergo 105h graphics 105h graphics ergo 106h graphics 106h graphics ergo 107h graphics...
Page 62 Energy Saving Screen Blanking If the display has power management capabilities, the video controller can reduce the display's power consumption by blanking the screen. This can be enabled by selecting power management options in the PC's SETUP program. When the PC enters a power- saving mode, the video controller is instructed to cut the horizontal and vertical synchronization signals to the monitor.
Page 63 Supported Enhanced Video Modes The following table lists the HP displays which may be used, and the supported enhanced video modes for use with each. For non-HP displays, refer to the manufacturers' documentation. Supported Enhanced Video Modes D1196A D1199A Ergo...
Page 64 VESA feature connector, auxiliary connector, or pass-through connector. The HP Vectra XU supports an output-only VESA feature connector. This connector is integrated on the system board (or on the Matrox MGA II PCI Video board) and is connected directly to the pixel data bus and the synchronization signals.
Page 65 Power-On Self Tests Vectra XU Technical Reference Power-On Self Tests...
Page 66 Overview This chapter describes the power-on self tests (POST) contained in the ROM BIOS. Vectra XU Technical Reference Power-On Self Tests...
Page 67 Power-On Self Test (POST) Each time the system is powered on or a reset is performed, the POST is executed. The POST process verifies the basic functionality of the system components and initializes certain system parameters. The POST performs the tests in the order described in this chapter.
Page 68: Shadow Ram
Shadow RAM On HP personal computers, access to certain ROM data is enhanced by using shadow RAM. During the POST, the BIOS and other ROM data is copied into high-speed shadow RAM. The shadow RAM is addressed at the same physical location as the original ROM in a manner which is completely transparent to applications.
Page 69 8042 Self-Test Timer 0/Timer 2 Test DMA Subsystem Test Interrupt ControllerTest Real-Time Clock Test Memory Tests RAM Address LineIndependence Test Size Extended Memory Real-Mode Memory Test(First 640 KB) Shadow RAM Test Protected Mode RAMTest (Extended RAM) Keyboard/Mouse Tests Keyboard Test Mouse Test Flexible Disk Drive A Tests Flexible Disk...
Page 70 Parallel Port Tests Parallel Port Test Serial Port Tests Serial Port Test Hard Disk Drive C Tests Hard Disk Controller Subsystem Test Ethernet (Integrated) Tests Ethernet HardwareTest System Configuration Tests System Generation Vectra XU Technical Reference Tests the integrated parallel port, if it is enabled, as well as any other parallel ports.
Page 71 A complete description of the error can be displayed by running theROM-based Error Management Utility (EMU). For a list of error codes, refer to the HP Vectra PC Service Handbook. Matrox Electronics Systems Ltd. can be contacted at the following addresses: The Corporate Headquarters is: Canada and U.S.A.
Page 72 Vectra XU Technical Reference Power-On Self Tests...

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