EEPROM is offered for internal register configuration. The 6/9th port of the RTL8366/8369 implements a GMII/MII/RGMII interface for connecting with an external PHY or MAC in specific applications. This interface could be connected to an external CPU or RISC in 1 WAN + 4 LAN or 1 WAN + 8 LAN Router applications.
• The RREF pin of the RTL8366/8369 and the MDI_REF pin of the RTL8212 must connect to GND via a 2.49K +/- 1% Ohm resister. This resister must be placed as close as possible to the RTL8366/8369 and RTL8212.
Avoid this Type of Routing for Long Lengths Preferred Differential Pair Routing for Long Lengths Resin-rich Areas Fiberglass Bundles of Dielectric of Dielectric Figure 1. Long Trace Layout for RSGMII RTL8366/8369 & RTL8212 Layout Guide Track ID: JATR-1076-21 Rev. 1.1...
• Place AC coupling capacitors near output pins of differential pairs. • Locate capacitors for coupled traces at the same location along the differential traces and near output pins of differential pairs. RTL8366/8369 & RTL8212 Layout Guide Track ID: JATR-1076-21 Rev. 1.1...
(Cap placement is not in same location & symmetric) Figure 4. Symmetrical Routing Into AC Caps • RSGMII layout reference is shown in Figure 5. Figure 5. RSGMII Layout Reference RTL8366/8369 & RTL8212 Layout Guide Track ID: JATR-1076-21 Rev. 1.1...
• Keep differential pairs as close as possible and route both traces as identically as possible, meaning width, length, and location. • Avoid vias and layer change if possible. • MDI Differential layout reference is show in Figure 6. Figure 6. MDI Differential Layout Reference RTL8366/8369 & RTL8212 Layout Guide Track ID: JATR-1076-21 Rev. 1.1...
PCB. • The following figures are examples of an RTL8212 footprint. Figure 8. RTL8212 Component Side Footprint Figure 9. RTL8212 Solder Side Footprint RTL8366/8369 & RTL8212 Layout Guide Track ID: JATR-1076-21 Rev. 1.1...
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Layout Guide 3.3. Clock Circuit • Place the crystal as close to the RTL8366/8369 as possible. • Surround the clock with ground trace to minimize high-frequency emissions. • Use only one 1.5K pull up external resistance to 3.3V for MDIO.
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