5
XC2S50-5PQ208C (DINB ASSY: IC8201, DOOB ASSY: IC8611)
• FPGA
These parts program the pin function by configuration ROM (IC8205: DINB ASSY, IC8610: DOOB ASSY).
Pin Arrangement (Top view)
157
208
Pin Function (DINB ASSY: IC8201)
No.
Pin Name
I/O
−
1
GND
2
(TMS)
I
3
SDI_D0
O
4
SDI_D1
O
5
SDI_D2
O
6
SDI_D3
O
7
SDI_D4
O
8
SDI_D5
O
9
SDI_D6
O
10
SDI_D7
O
−
GND
11
−
Vcco
12
−
13
Vccint
14
SDI_DAI
O
15
SDI_BCK
O
16
SDI_LRCK
O
17
SDI_LOCK
O
18
AES_ERROR
O
−
19
GND
20
MODE_SEL
I
21
TP01
O
22
TP02
O
23
TP03
O
24
TP04
O
−
25
GND
−
26
Vcco
27
TP05
O
−
28
Vccint
29
TP06
O
30
TP07
O
5
6
156
105
XC2S50-5PQ208C
1
52
Digital GND
JTAG TMS
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
SDI digital video signal output
Digital GND
I/O power supply (3.3V)
Core power supply (2.5V)
Data output for SDI Embedded Audio
Audio clock output for SDI Embedded Audio
LR clock output for SDI Embedded Audio
The signal which shows whether the SDI-embeded signal locks H: locks, L: unlock
The signal which shows existence of an error of AES/EBU signal H: Error nothing, L: There is an error
Digital GND
For operating mode setting of the AES/EBU receiver H: Master mode, L: Slave mode
FPGA test signal output (Not connected at AVIB side)
FPGA test signal output (Not connected at AVIB side)
FPGA test signal output (Not connected at AVIB side)
FPGA test signal output (Not connected at AVIB side)
Digital GND
I/O power supply (3.3V)
FPGA test signal output (Not connected at AVIB side)
Core power supply (2.5V)
FPGA test signal output (Not connected at AVIB side)
FPGA test signal output (Not connected at AVIB side)
6
7
104
53
Pin Function
PRA-BD11
7
8
A
B
C
D
E
F
87
8