Super Io Schematic; Figure 25 Lpc Super I/O Example - Emerson COM Express Carrier Design Manual

 FWH pin 2 — RST# supports Chip Reset. The LPC_RESET# signal from the COM Express module drives
the reset. The pin functions the same as INIT# above.
12.2.2 Super I/O Schematic
Figure 24 LPC Super I/O Example
SIO Pin Straps: Pin 51 RTSA# Low: SIO Base 2Eh High: SIO 4H; Pin 52 DTRA# Low: Use PNP High: No
PNP; Pin 54 SOUTA Low: Disable KBC High: Enable KBC; Pin 83 SOUTB Low: 24 MHz clock High: 48
MHz clock SIO Keyboard / Mouse controller is disabled with the strapping shown here.
Pull down resistor required on unused pins of a used COM port; floating pins generate interrupts
!
If using the SIO Keyboard / Mouse controller, load the two logic gates shown. These gates
perform level shifting - SIO signals may be up to 5 V; COM Express levels must be 3.3 V maximum.
Gates may be left off for completely legacy free system.
Page 68 of 103 COM Express Carrier Type 2
Design Guide