Table of Contents
Advertisement
Pin No. Terminal name I/O
72
MD6
73
MD5
74
MD4
75
MD3
76
MD2
77
MD1
78
MD0
79
SD7
80
SD6
81
SD5
82
SD4
83
DVSS
84
DVDD3
85
SD3
86
SD2
87
SD1
88
SD0
89
SERR
90
SBGN
91
SENB
92
SDCK
93
DVSS
94
SREQ
95
RSTN
96
DVDD3
97
STDA
98
STCK
99
UPWM
100
DVSS
I/O
External RAM data bus.
I/O
External RAM data bus.
I/O
External RAM data bus.
I/O
External RAM data bus.
I/O
External RAM data bus.
I/O
External RAM data bus.
I/O
External RAM data bus.
O
MPEG data output.
O
MPEG data output.
O
MPEG data output.
O
MPEG data output.
–
Digital power. (0V)
–
Digital power. (3.3V)
O
MPEG data output.
O
MPEG data output.
O
MPEG data output.
O
MPEG data output.
O
MPEG data reliability flag. (Data error: "L")
O
MPEG output sector sync signal. (Sector top: "L")
O
MPEG data effective flag. (Effective state: "L")
O
MPEG data transfer clock.
–
Digital power. (0V)
I
MPEG data request flag. (Request state: "L")
I
Hard reset input. (Reset state: "L")
–
Digital power. (3.3V)
O
Operation state monitor data.
(Output synchronizing with SDCK fall)
O
Operation state monitor sync signal. (Data top bit: "L")
O
General-use PWM output.
–
Digital power. (0V)
Operation function
12-22
DV-550U
Remarks
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
For logic cell
For logic cell
For logic cell
TTL level
For logic cell
Common with PWM.
Common with PWM.
4mA, 5V-I/F
For logic cell
Advertisement
Table of Contents
