LG 65UX340C Service Manual page 40

LGE5352(URSA11)
AD26
URSA_RESET
PAD_RESET
AH4
XIN_URSA
PAD_XOUT
AH3
XO_URSA PAD_XIN
AE9
SDA2_+3.3V_URSA
PAD_I2C_S_SDA
AR1351 AD9
SCL2_+3.3V_URSA
PAD_I2C_S_SCL
33
AD10
PAD_I2C_M_SDA
AE10
PAD_I2C_M_SCL/[VSYNC_LIKE_SP1]
URSA_UART2_TX E8
PAD_GPIO00/[UART2_TX]
F7
URSA_UART2_RX
PAD_GPIO01/[UART2_RX]
E7
URSA_UART1_TX
PAD_GPIO02/[UART1_TX]
F6
PAD_GPIO03/[CHIP_VDET]
AD27
PAD_SPI_CZ
SPI_CZ
AC27
SPI_CK PAD_SPI_CK
AR1352
AC28
PAD_SPI_DI
SPI_DI 33
AC26
SPI_DO PAD_SPI_DO
R13517 0
5V_DET_HDMI_2 AE25
PAD_INTERUPT_R21
AD25
PAD_INTERUPT_R20
R13503 0
5V_DET_HDMI_2
OPT
D7
PAD_IRE/[UART1_RX]
URSA_UART1_RX
R13518 0
AC25
PAD_TESTPIN
AC9
GND_EFUSE
R13519 0
AC19
R13504 33
OPT GPIO[09]
AD19
R13505 33
OPT GPIO[08]
AC18
VID1
GPIO[07]
AE19
VID0
GPIO[06]
AD7
URSA_BIT3 GPIO[64]
AE7
R13509 33
OPT GPIO[65]
AC7
R13510 33
OPT GPIO[66]
AD8
R13511 33
OPT GPIO[67]
AC8
R13512 33
OPT GPIO[63]
M4
R13513 33
OPT GPIO[70]
M5
R13514 33
OPT GPIO[72]
N4
R13515 33
OPT GPIO[73]
N5
R13516 33
OPT GPIO[71]
AE6
NC_1
AD6
NC_2
URSA Option
URSA_OPT_6
URSA_OPT_5
BIT [1/0] Module Division
URSA_OPT_4
0/0 Non Division Div_BIT0
0/1 2 Division
Div_BIT1
1/0 4 Division
URSA_OPT_0
1/1 8 Division
URSA_OPT_1
URSA_BIT0
BIT [2/1/0] Tx Lane
URSA_BIT1
0/0/0 4K@120 (4DDR)
URSA_BIT2
0/0/1 4k@60 (2DDR)
0/1/0 5k@120 (4DDR)
URSA_BIT3
0/1/1 OLED 4K (4DDR)
1/0/0 FHD@120 (4DDR)
1/0/1 FHD@60 (2DDR)
1/1/0 FHD@60 (4DDR)
4K@60Hz (4DDR)
1/1/1
* URSA_BIT3 : READY
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
IC119
AD11
PAD_I2C_HSC_SDA/[VSYNC_LIKE_SPI2]
AC10
PAD_I2C_HSC_SCL/[VSYNC_LIKE_SPI3]
AC23
PAD_SPI1_CK/GPIO58 URSA_OPT_0
AD24
PAD_SPI1_DI/GPIO59 Div_BIT0
AD23
PAD_SPI2_CK/GPIO56 Div_BIT1
AC22
PAD_SPI2_DI/GPIO57 URSA_OPT_4
AE24
URSA_L/D_CK
PAD_SPI3_CK/GPIO54
AE22
PAD_SPI3_DI/GPIO55 URSA_L/D_DI
AD22
URSA_OPT_5
PAD_SPI4_CK/GPIO52
AC21
PAD_SPI4_DI/GPIO53 URSA_OPT_6
AC24
PAD_VSYNC_LIKE/GPIO40 URSA_L/D_VSYNC
+3.3V_U_NORMAL
AE13 DIM0
PAD_DIM00/GPIO32
AD13
DIM1 OPT
PAD_DIM01/GPIO33
R13540
AC13 DIM2
PAD_DIM02/GPIO34 10K
AE15
PAD_DIM03/GPIO35
AC14
PAD_DIM04/GPIO36 URSA_OPT_1
AD14 R13541
URSA_BIT0 10K
PAD_DIM05/GPIO37
AD15
URSA_BIT1
PAD_DIM06/GPIO38
AC15
URSA_BIT2
PAD_DIM07/GPIO39
E4
PAD_TCON0/STV2
D5
PAD_TCON1/OE
E6
PAD_TCON2/YV1C
E5
PAD_TCON3/CPV
F5
PAD_TCON4/STV1
F4
PAD_TCON5/SFT
D6
PAD_TCON6/TPV
D4
PAD_TCON7/POL
AC4
PAD_TCON8/[VX1T_HTPDN]
AD4
PAD_TCON9/[VX1T_LOCKN]
AA4
R13520 0
PAD_TCON10/[HDMI_R_DDC_CLK3] DDC_SCL_HDMI1
AB5
PAD_TCON11/[HDMI_R_DDC_DAT3] R13521 0 DDC_SDA_HDMI1
AB4
PAD_TCON12/[HDMI_R_HP3]
AA5
5V_DET_HDMI_1
PAD_TCON13/[HDMI_R_CEC3] R13501 0
AD5
PAD_TCON14/[HDMI_T_CEC]
AE5
PAD_TCON15/[HDMI_T_HPD]
AD21
PAD_GPIO04 Data_Format_1
AD20
Data_Format_0
PAD_GPIO05
AC6
R13522 0
GPIO[74] DDC_SCL_HDMI2
AC5
GPIO[75] DDC_SDA_HDMI2
R13523 0
AB7
GPIO[76]
AB6
GPIO[69]
AE21
R13524 33
PAD_GPIO10
AC20
PAD_GPIO11 R13525 33
AE12
PAD_GPIO12/[VX1_RX_HTPD_O]
R13585 R13586
AD12
URSA_RX_Vx1_HTPDn 100K 100K
PAD_GPIO13/[VX1_RX_HTPD_V]
AD18
R13542 10K
PAD_GPIO14
AC11
PAD_GPIO15/[VX1_RX_LOCK_O]
R13543 10K
AC12
PAD_GPIO16/[VX1_RX_LOCK_V] URSA_RX_Vx1_HTPDn
AE18
PAD_GPIO17
FLASH_WP_URSA
B1
NC_3
AG1
NC_4
AH2
NC_5
AH27
NC_6
B28
NC_7
AG28
NC_8
+3.3V_U_NORMAL
Division Type
Rx Interface
Module Type
Tx Lane
SPI Flash
IC1351
MX25L3235E
CS
1
SPI_CZ
URSA_FLASH_MX(MULTI)
R13559 SO/SIO1
33
2
SPI_DO
WP/SIO2
1K
R13558
3
FLASH_WP_URSA
OPT
GND
1K
R13562 4
FRC_FLASH_WP
R13564
10K
OPT
HTPDAn
R13557
10K
URSA_TX_HTPD_pulldown
Clock for URSA11
LOCKAn
+3.3V_U_NORMAL
R13552
10K
OPT
E
Q1351
2N3906S-RTK
Vx1_LED_PNP_KEC(MULTI)
B
C
E Q1351-*1
MMBT3906(NXP)
Vx1_LED_PNP_NXP(MULTI)
B
C
Chip Config
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V_U_NORMAL
10K
OPT
R13567
10K
R13563
OPT 10K
10K R13566
R13561
OPT 10K
R13565
10K
R13560
URSA_PQ_DEBUG
P1352
IC1351-*1
W25Q32FVSSIG 12507WS-04L
CS VCC
1 8
DO[IO1] HOLD_OR_RESET[IO3]
2 7
WP[IO2] CLK
3 6
GND DI[IO0]
4 5
URSA_FLASH_WINDBOND(MULTI)
+3.3V_U_NORMAL
5
VCC
C1353
8
0.1uF
16V
HOLD/SIO3
URSA_SYS_DEBUG
7
P1353
10K R13569
12507WS-04L
SCLK
SPI_CK
6
SI/SIO0
SPI_DI
5
5
+3.3V_U_NORMAL
SW1351
1 2
XIN_URSA
3 4
D1351
1N4148W
100V
OPT
XO_URSA
Debugging for URSA
I2C_S Port
P1351
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
DIM0
1
2
DIM1 R13571 33
NON_URSA_SLIDE_SW(MP)
3
SCL2_+3.3V_DB
URSA_DEBUG
SCL2_+3.3V_URSA
R13570 33
4
SDA2_+3.3V_DB
URSA_DEBUG
SCL2_+3.3V_DB
DIM2 5
URSA11
U_UART_GPITO
+3.3V_U_NORMAL
R13576
URSA_PQ_DEBUG
10K
1
2
33
R13582
URSA_UART2_RX
3
URSA_PQ_DEBUG
R13579 33
4 URSA_UART2_TX
URSA_PQ_DEBUG
C1356
0.1uF
16V
URSA_PQ_DEBUG
+3.3V_U_NORMAL
R13573
10K
URSA_SYS_DEBUG
1
2
33
R13580
3 URSA_UART1_RX
URSA_SYS_DEBUG
R13581 33
4 URSA_UART1_TX
URSA_SYS_DEBUG
URSA_SYS_DEBUG
C1355
0.1uF
16V
URSA Reset
+3.3V_U_NORMAL
C1354
1uF
R13577
10V 10K
OPT
URSA_RESET
URSA_RESET_SoC
R13572
0
470K
R13578
OPT
URSA_RESET_READY
0
R13242
OPT
SW1352
JS2235S
1 6
URSA_SCL URSA_SDA
R13574 R13583
0 NON_URSA_SLIDE_SW(MP)
0
2 5
SDA2_+3.3V_URSA
R13575 URSA_SLIDE_SW(DEBUG) R13584
0 0
OPT OPT
3 4
SDA2_+3.3V_DB
2014.
132
LGE Internal Use Only