THine THCV242 Manual

THine THCV242 Manual

Serdes receiver with bi-directional transceiver
Table of Contents

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THCV242_ Rev.2.00_E

1. General Description

THCV242 is designed to support 1080p60 2Mpixel
uncompressed video data over 15m 100ohm
differential STP or single-end 50ohm Coaxial cable
with 4 in-line connectors between camera and
processor by V-by-One® HS.
THCV242 supports a MIPI CSI-2. Each CSI-2 data
lane can transmit up to 1.2Gbps/lane. Virtual channel
is supported. MIPI 2nd port output supports data
copy and distribution.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd input lane supports HDR large
amount of data or camera switch experience.
THCV242 is capable to control and monitor remote
camera module from MPU via GPIO or 1Mbps 2-
wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.

3. Block Diagram

Copyright©2019 THine Electronics, Inc.
THCV242
SerDes receiver with bi-directional transceiver
V-by-One® HS
Main-Link
Rx 2-lane
RX0P
RX0N
RX1P
RX1N
Sub-Link 2-lane
RCM0P
RCM0N
RCM1P
RCM1N

2. Features

MIPI CSI-2 with 1,2 or 4-lane output
MIPI D-PHY supports 80Mbps~1.2Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, User-
defined generic 8-bit
V-by-One® HS 400Mbps~4Gbps x2lane
V-by-One® HS standard version1.5
Video stream switch and copy/distribution
Frame sync remote supply scheme for multiple
camera stream synchronization
Wide range IO voltage from 1.7V to 3.6V
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
QFN64 9x9mm 0.5mm pitch Exp-pad package
THCV242
Settings
GPIO
Controls
2-wire
serial I/F
OSC
1/53
MIPI CSI-2
Data Tx 4-lane
Clock Tx 2-port
MTX0P
MTX0N
MTX1P
MTX1N
MTXCLK0P
MTXCLK0N
MTX2P
MTX2N
MTX3P
MTX3N
MTXCLK1P
MTXCLK1N
THine Electronics, Inc.
Security E

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Summary of Contents for THine THCV242

  • Page 1: General Description

    4 in-line connectors between camera and Video formats: RAW8/10/12/14/16/20, processor by V-by-One® HS. YUV422/420, RGB888/666/565, JPEG, User- THCV242 supports a MIPI CSI-2. Each CSI-2 data defined generic 8-bit lane can transmit up to 1.2Gbps/lane. Virtual channel  V-by-One® HS 400Mbps~4Gbps x2lane is supported.
  • Page 2: Table Of Contents

    MIPI CSI-2 Virtual Channel ......................35 Multiple camera synchronization Frame Vsync supply ..............36 6.6. Status monitoring, Interrupt and Error Detection .................. 38 Internal Error / status signal monitoring pin output ............... 38 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 2/53 Security E...
  • Page 3 11.5. 2-wire serial Slave AC Specifications ....................51 Package ..............................52 Notices and Requests ..........................53 MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 3/53 Security E...
  • Page 4: Pin Configuration

    MTX3N VSSRX MTX1P RX1N MTX1N (TOP VIEW) 65 EXPGND RX1P 24 MTXCLK0P VDDRX 23 MTXCLK0N RSVDL0 MTX0P RSVDL0 MTX0N VSSRX MTX2P RSVDL0 MTX2N ● RSVDL0 18 MTXCLK1P VDDRX 17 MTXCLK1N Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 4/53 Security E...
  • Page 5: Pin Description

    *type symbol ; MO=MIPI Output, CI=CML Input, CB=CML Bi-directional input/output I0=1.2V CMOS Input, I1=1.8~3.3V VDDIO1 domain CMOS Input, I2=1.8~3.3V VDDIO2 domain CMOS Input O=1.8~3.3V VDDIO1 domain CMOS Output, B=1.8~3.3V VDDIO1 domain CMOS Bi-directional input/output P=Pow er, G=Ground Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 5/53 Security E...
  • Page 6: Functional Description

    6.1. Functional Overview THCV242 can receive CML video signal transmitted over 15m length and encode it to MIPI CSI-2 format. With High Speed CML SerDes, high reliability and robustness encoding scheme and CDR (Clock and Data Recovery) architecture, the THCV242 enables to receive RAW/YUV/RGB/JPEG/Generic8bit data through Main-Link by single 100ohm differential pair or 50ohm Coax cable with minimal external components.
  • Page 7: Mprf (Main-Link Private Format)

    MPRF (Main-Link PRivate Format) MPRF format encoding preserves original data packet input to V-by-One® HS transmitter and output the data packet from THCV242. The counterpart transmitter must have installed MPRF format decoder like THCV241 because MPRF is not standard format.
  • Page 8: V-By-One® Hs Standard Format

    UnPacker packet definition. Data can be transmitted normally only when both transmitter and receiver are set to the same available format. Some of the THCV242 format may not be supported by particular counterpart transmitter because THCV242 prepares multiple formats that suit to multiple transmitter devices alternatives.
  • Page 9 V-by-One®HS_D[2] RAW[2] (1st pixel) RAW[2] (2nd pixel) RAW[2] (3rd pixel) V-by-One®HS_D[1] RAW[1] (1st pixel) RAW[1] (2nd pixel) RAW[1] (3rd pixel) V-by-One®HS_D[0] RAW[0] (1st pixel) RAW[0] (2nd pixel) RAW[0] (3rd pixel) Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 9/53 Security E...
  • Page 10 V-by-One®HS_D[4] RAW[6] RAW[6](2nd pixel) RAW[6](2nd pixel) V-by-One®HS_D[3] RAW[5] RAW[5](2nd pixel) RAW[5](2nd pixel) V-by-One®HS_D[2] RAW[4] RAW[4](2nd pixel) RAW[4](2nd pixel) V-by-One®HS_D[1] RAW[3] RAW[3](2nd pixel) RAW[3](2nd pixel) V-by-One®HS_D[0] RAW[2] RAW[2](2nd pixel) RAW[2](2nd pixel) Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 10/53 Security E...
  • Page 11 V-by-One®HS_D[4] RAW[8] RAW[8](2nd pixel) RAW[8](2nd pixel) V-by-One®HS_D[3] RAW[7] RAW[7](2nd pixel) RAW[7](2nd pixel) V-by-One®HS_D[2] RAW[6] RAW[6](2nd pixel) RAW[6](2nd pixel) V-by-One®HS_D[1] RAW[5] RAW[5](2nd pixel) RAW[5](2nd pixel) V-by-One®HS_D[0] RAW[4] RAW[4](2nd pixel) RAW[4](2nd pixel) Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 11/53 Security E...
  • Page 12: Link Status (Htpdn/Lockn)

    It will need same GND potential reference between transmitter and receiver device to connect HTPDN and LOCKN pins directly like above. HTPDN and LOCKN can also be transmitted via Sub-Link without physical wire connection. Assignment can be configurable by 2-wire access to internal register. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 12/53...
  • Page 13 Sub-Link Lane0 LOCKN/HTPDN scheme of releted Main-Link select 0:LOCKN0 1:LOCKN0 | LOCKN1 [1:0] R_LOCKN_LN0_SEL 2:Reserved 2'd0 3:1'b0 (Forced LOCKN/HTPDN=Low) *LOCKN0=LOCKN signal of V-by-One(R) HS Lane0=RX0P/RX0N *HTPDN of the same lane as above set LOCKN lane is used Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 13/53 Security E...
  • Page 14: Local, Remote And Remote Slave Register Programming

    0: 2WIRE slv device addr. is set by AIN<1:0> pin 8'd0 1: 2WIRE slv device addr. is set by following register [6:0] [6:0]2WIRE slave device address value for register control Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 14/53 Security E...
  • Page 15: 2-Wire Serial Read/Write Access To Local Register

    THCV242_ Rev.2.00_E 2-wire serial Read/Write access to local Register HOST MPU can directly access THCV242 local register by 2-wire serial I/F. THCV242 Sub-Link Block Host Sub-Link 2-wire Master Slave Registe r AIN<1:0> = Use r S elect Figure 3. Host to THCV242 local register access configuration...
  • Page 16: 2-Wire Serial I/F Watch Dog Timer

    Addr(h) Register Name width Description Default 0x003B [7:5] reserved 2WIRE WDT Enable R_2WIRE_WD_EN 0:Disable 1'b1 1:Enable [3:1] reserved 2WIRE_WDT_OffsetTime R_2WIRE_WD_OFFSET 1:11'd2047 1'd1 0:11'd1023 0x003C [7:0] R_2WIRE_WD_TIM RW 2WIRE WDT_time=64×{R_2WIRE_WD_TIM<7:0>+1}×{2WIRE_WDT_OffsetTime}×tOSC 8'd255 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 16/53 Security E...
  • Page 17: Sub-Link Setting

    Sub-Link setting THCV242 has Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also HTPDN/LOCKN signals for Main-Link. THCV242 is Sub-Link Master and connectable to Sub- Link Slave device such as THCV241. Sub-Link Polling interval is controllable from about 20us to 800us, that may have relationships on fault/error detection, interrupt, or other UART / GPIO transfer time designed on application.
  • Page 18: Sub-Link 2-Wire Read/Write Access To Remote Register

    Figure 6. Host MPU to Sub-Link Slave Register via THCV242 access configuration HOST MPU can access to remote side 2-wire serial slave register via THCV242 as Sub-Link Master only by THCV242 internal local register control and monitoring on 2-wire Set&Trigger mode1.
  • Page 19 Sub-Link communication time + Sub-Link Slave side internal bus access process time Sub-Link communication time + Remote side 2-wire serial Access Time Figure 8. Sub-Link Master 2-wire slave clock stretching operation Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 19/53 Security E...
  • Page 20 [1] 0: Lane1 Disable, 1:Lane1 Enable [1:0] R_2WIRE_WR_LANE_SEL 4'hF [0] 0: Lane0 Disable, 1:Lane0 Enable *Only active when R_SLINK_MODE=4'd0 or 4'd1 0x00E5 [7:1] reserved R_2WIRE_START 2-wire serial I/F remote access start trigger Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 20/53 Security E...
  • Page 21: Sub-Link 2-Wire Pass Through Mode

    Figure 9. 2-wire Pass Through mode1 Sub-Link Slave command Divided scheme On address processing protocol “Assigned address & rename”, THCV242 2-wire slave respond only to 2-wire device address defined in R_2WIREPT1_PASS_ADRxy1 (x=Lane0 or Lane1, y=0/1/2/3) for remote Pass Through operation. Otherwise, 2-wire commands are ignored except THCV242 itself address. The device address can be renamed before remote send.
  • Page 22 0x004F [7:0] 8'd0 R_2WIREPT2_NOPASS_ADR07 being active only at R_2WIREPT_MODE[0]=1. 2WIRE Pass Through counterpart Sub-Link Slave internal access dedicated address for Lane0, 0x0050 [7:0] R_2WIREPT1_PASS_ADRIN0 8'd0 being active only at R_2WIREPT_MODE[0]=0. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 22/53 Security E...
  • Page 23 0x006F [7:0] R_2WIREPT2_NOPASS_ADR17 8'd0 being active only at R_2WIREPT_MODE[0]=1. 2WIRE Pass Through counterpart Sub-Link Slave internal access dedicated address for Lane1, 0x0070 [7:0] R_2WIREPT1_PASS_ADRIN1 8'd0 being active only at R_2WIREPT_MODE[0]=0. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 23/53 Security E...
  • Page 24: Sub-Link Transaction Time Accuracy Improvement

    Polling Interval poling Polling Interval Polling Interval Sub-Link Master Polling transaction to all Sub-Link lanes Ignored previous Ignored previous Polling Interval Polling Interval Figure 10. Sub-Link transaction time accuraty control Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 24/53 Security E...
  • Page 25: Gpio Setting

    0x10 03 [3:0] R_GPIO2_MODE 4'h0 0:Disable 1:Programable GPO (Output Low ) 2:Programable GPO (Output High) 3:Through GPI Mode 4:Through GPO Mode 5:Second 2WIRE Mode (SCL) 6:Second 2WIRE Mode (SDA) 7~F:Reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 25/53 Security E...
  • Page 26: Register Gpio

    1:Programable GPO (Output Low ) 2:Programable GPO (Output High) 3:Through GPI Mode 4:Through GPO Mode 5:Second 2WIRE Mode (SCL) 6:Second 2WIRE Mode (SDA) 7~F:Reserved Register GPIO GPIO output control are available with register. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 26/53 Security E...
  • Page 27: Through Gpio

    Sub-Link Polling interval Figure 11. Through GPIO bridge sampling As default setting with THCV231 as Sub-Link Slave communication (THCV242 as Sub-Link Master), GPIO1 Sub-Link Polling bridges input to THCV231-GPIO4 Through Mode and GPIO0 Sub-Link Polling bridges input to THCV231-GPIO3 Through Mode respectively.
  • Page 28: Gpio As Secondary 2-Wire Port

    THCV242_ Rev.2.00_E GPIO as secondary 2-wire port GPIO port can be secondary 2-wire port, which can accommodate dual 2-wire access from two processors. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 28/53 Security E...
  • Page 29: Mipi

    [RefDiv] x [OutDiv1] x [OutDiv2] [F(MIPI output)] [FBDiv] [F(Main-Link input)] [RefDiv] x [OutDiv1] x [OutDiv2] MIPI High Speed mode DDR output clock per lane = [F(MIPI output)] / 2 (MHz) Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 29/53 Security E...
  • Page 30 0x21 0x00 0x00 0x00 720p60fps YUV422 74.25 1188 0x20 0x02 0x21 0x00 0x00 0x00 2.97Gbps 1lane YUV422 Normal 594Mbps x2lane 1080p30fps YUV422 74.25 1188 0x20 0x02 0x21 0x00 0x00 0x00 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 30/53 Security E...
  • Page 31: Video Stream Switch And Copy/Distribution

    Cam B 5'd8 1(2port) Disable Cam A Cam A Cam A 5'd10 Disable Cam A Cam B Cam A Cam B 5'd11 Enable Cam A Cam B Cam B Cam A Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 31/53 Security E...
  • Page 32: Header/Packet/Sync Pre-Processing

    Main-Link Lane0 to MIPI Word Count (MSB 8bit) 0x1106 manual setting (Only active when R_VX1_PH_EN=0) [7:0] R_VX1_DATAID0 8'h00 Main-Link Lane0 to MIPI Data ID manual setting 0x1107 (Only active when R_VX1_PH_EN=0) Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 32/53 Security E...
  • Page 33: Mipi Output Setting

    [5] Data PORT0 / 0:OFF, 1:ON [4:3] MIPI CLK lane Enable [4] CLK lane1 / 0:OFF, 1:ON [3] CLK lane0 / 0:OFF, 1:ON [2:0] MIPI Configuration 3'b000:1PORT1LANE 3'b001:1PORT2LANE 3'b010:Reserved 3'b011:1PORT4LANE 3'b100:2PORT1LANE 3'b101:2PORT2LANE 3'b110:Reserved 3'b111:Reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 33/53 Security E...
  • Page 34 Data lane ZERO period setting PORT1 0x161c [7:0] R_TX_THS_TRAIL1 8'h07 Data lane TRAIL period setting PORT1 0x161d [7:4] 2'b00 Reserved 0x161f [3:0] R_REQ_SEL 4'h0 MIPI Tx Lane PORT assignment [3]Lane3, [2]Lane2, [1]Lane1, [0]Lane0 0:PORT0 1:PORT1 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 34/53 Security E...
  • Page 35: Mipi Csi-2 Virtual Channel

    MIPI Virtual Channel information in PH is also bridged from V-by-One® HS at the same time. Virtual Channel information can be intake from Main-Link input and properly applied on MIPI Packet Header by selectable register setting. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 35/53...
  • Page 36: Multiple Camera Synchronization Frame Vsync Supply

    THCV242_ Rev.2.00_E Multiple camera synchronization Frame Vsync supply Frame VSYNC can be supplied from THCV242 to Sub-Link Slave GPO. EXTSYNC input or internally generated VSYNC become supply source. Settings are configurable by 2-wire access to internal register. When internal VSYNC is selected, generated VSYNC is not only sent to remote Sub- Link Slave but also output from EXTSYNC pin.
  • Page 37 0x002E [7:0] R_VS_PHASE_WIDTH *Phase shift difference is 16 xCLK_I as exception when R_VS_PHASE_WIDTH=0 8'd1 *For setting or reset of this register, R_VS_PHASE_EN is supposed to be Disable 0x002F [7:0] reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 37/53 Security E...
  • Page 38: Status Monitoring, Interrupt And Error Detection

    0x14 Vx1_HTPDN0 lane0 0x15 Vx1_HTPDN1 lane1 0x16 Reserved 0x17 Reserved 0x18 Vx1_BETOUT_LATCH0 lane0 0x19 Vx1_BETOUT_LATCH1 lane1 0x1A Reserved 0x1B Reserved 0x1C Vx1_BETOUT_REAL0 lane0 0x1D Vx1_BETOUT_REAL1 lane1 0x1E Reserved 0x1F Reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 38/53 Security E...
  • Page 39 0x32 Reserved 0x33 Reserved 0x34 MLINK_CLK0 lane0 0x35 MLINK_CLK1 lane1 0x36 Reserved 0x37 Reserved 0x38 MIPI_BYTECLK 0x39 OSCCLK 0x3A Reserved 0x3B Reserved 0x3C Reserved 0x3D Reserved 0x3E Reserved 0x3F Reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 39/53 Security E...
  • Page 40 0x54 SLINK_PERR0 lane0, protocol error 0x55 SLINK_PERR1 lane1, protocol error 0x56 Reserved 0x57 Reserved 0x58 SLINK_TMOUT0 lane0, time out error 0x59 SLINK_TMOUT1 lane1, time out error 0x5A Reserved 0x5B Reserved Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 40/53 Security E...
  • Page 41: Internal Error / Status Signal Monitoring Register

    Main-Link(Lane0) BET Error Number (Low er Byte) 0x17 59 [7:0] MLINK0_BET_ERRNUM[7:0] Main-Link(Lane1) BET Error Number (Upper Byte) 0x17 5A [7:0] MLINK1_BET_ERRNUM[15:8] Main-Link(Lane1) BET Error Number (Low er Byte) 0x17 5B [7:0] MLINK1_BET_ERRNUM[7:0] Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 41/53 Security E...
  • Page 42: Interrupt Monitoring

    Interrupt factor can be masked to “0” fixed by particular register appropriate write access. INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status may change at power on condition and THCV242 internal boot up procedure. Table 31. Interrupt monitoring...
  • Page 43: Register Auto Checksum Diagnosis

    Internal Register AutoCheckSum check interval 0x0009 [7:0] R_CKSUM_TIM 8'd19 =1024×64×(R_CKSUM_TIM<7:0>+1) × tOSC 0x000A [7:0] R_CKSUM_VAL RW Internal Register AutoCheckSum expected target value 8'd0 0x000B [7:0] R_CKSUM_RVAL Internal Register AutoCheckSum read value Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 43/53 Security E...
  • Page 44: Power On Sequence

    1frame The first MIPI output from Power On waits vertical blanking period and starts output; therefore, MIPI normal operation may be hold for maximum 1frame, which depends on used video format. Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 44/53 Security E...
  • Page 45: Lock / Re-Lock Sequence

    Lock / Re-Lock Sequence Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial status or unlock status caused by external noise under appropriate parameter set condition. THCV242 LOCK Sequence THCV242 RXnP/RXnN (n=0,1) CDR Training...
  • Page 46: Absolute Maximum Ratings

    Table 37. Recommended Operating Conditions Symbol Parameter Condition Unit 3.3V Drive VDDH Supply Voltage (VDDIO1, VDDIO2) 2.5V Drive 1.8V Drive VDD12 Supply Voltage 1.2V (VDDCORE, VDDRX, VDDTX, VDDPLL) Operating Ambient Temperature degC Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 46/53 Security E...
  • Page 47: Consumption Current

    594Mbps x2lane x2port 1080p30fps YUV422 Iccw12_37 720p120fps RAW Iccw12_38 2.2275Gbps x1lane x2port 891Mbps x2lane x2port 1080p60fps RAW Iccw12_39 720p120fps YUV422 Iccw12_402 2.97Gbps x1lane x2port 1188Mbps x2lane x2port 1080p60fps YUV422 Iccw12_412 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 47/53 Security E...
  • Page 48: Dc Specifications

    CML Input Leak Current High ±15 RXP/N=1.2V PDN=L, IRIL CML Input Leak Current Low ±15 RXP/N=GND IRRIH CML Input Current High RXP/N=1.2V IRRIL CML Input Current Low RXP/N=GND -4.6 RRIN CML Differential Input Resistance Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 48/53 Security E...
  • Page 49: Mipi Transmitter Dc Specifications

    |VTOD| HS-mode Differential Voltage ZID=100ohm VTOHHS HS-mode High Level Output Voltage ZID=100ohm VTOHLP LP-mode High Level Output Voltage VTOLLP LP-mode Low Level Output Voltage -0.05 0.05 ZTOLP LP-mode Output Impedance Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 49/53 Security E...
  • Page 50: Cml Bi-Directional Buffer Dc Specifications

    R_BDCZ_TERM_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_TERM_TX/ RX RTERM Termination Registance [1:0]=2'b01 R_BDCZ_TERM_TX/ RX [1:0]=2'b00 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_DRIVE_TX/ RX IDRIVE Drive Current [1:0]=2'b01 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b00 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 50/53 Security E...
  • Page 51: Ac Specifications

    11.5. 2-wire serial Slave AC Specifications Table 49. 2-wire serial Slave AC Specifications (Sub-Link Master) Symbol Parameter Condition Unit tOSC Cycle of internal oscillator clock 11.7 12.5 15.7 fSCL SCL clock frequency 1000 Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 51/53 Security E...
  • Page 52: Package

    THCV242_ Rev.2.00_E 12. Package TOP VIEW LASER MARK FOR PIN1 BOTTOM VIEW 1.10 6.00 0.09 PIN1 ID 0.20 R 0.25 SIDE VIEW Unit: mm Copyright©2019 THine Electronics, Inc. THine Electronics, Inc. 52/53 Security E...
  • Page 53: Notices And Requests

    THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately.

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