Mitsubishi Electric DD-5000 Service Manual page 48

Table 3-5-5 MD36710X (3/5)
Pin
Name
No.
Digital video port (24 pins)
84 V C L K VCLKx2 signal is divided by 2. Used
as a qualifier of data and sync signal.
85 V M A S T E R Video master/slave selection input. At
high level, video sync in MD36710X
enters master mode. (Video sync and
clock signals are developed.) After
low level, video sync enters slave
mode. (Video sync and clock signals
are entered.)
Only during reset, setting of terminal
can be changed.
87 V D E N # Video enable input (active low). When
active, MD 36710X develops video
data. When deasserting, pixel output
becomes 3-state condition. (But sync
and clock signals are kept to be
active.)
Input is changeable at any time but
becomes effective at the next
VCLKx2.
89 V S Y N C Vertical sync bidirectional signal pin.
Polarity and length are programmable.
90 H S Y N C Horizontal sync bidirectional signal
pin. Polarity and length are
programmable.
91 FI Field identification bidirectional signal
pin. Polarity is programmable.
92 Y [7:0] At 16 bit video mode (Video 8=0),
94 develop luminance signals. At 8 bit
| mode (Video 8=1), develop luminance
97 and color difference signals
99 multiplexed in time sequence
| according to the ITU-R656 standard
101 (in no relation to presence of SAV and
EAV sync code).
98 C B L A N K Composite blank output. Waveforms are
programmable other than polarity.
C [7:0] At 16 bit video mode (Video 8=0),
102 develop color difference signal. At 8
104 bit mode (Video 8=1), m.s. line 3 pin
105 (c [7:5]) is not used, I.s.5 pin (C [4:0])
is used as input from external OSD
device.
106 OSDPLT (C [4]) On-chip OSD palette selector. Selects
OSD Palette0 at low level and OSD
Plette1 at high level.
107 OSDPEL [3:0] OSD pixel input. Used as an entry
109 (C [3:0]) signal to on-chip OSD palette.
|
111
124 V C L K x 2 Main video clock input or output.
Digital audio port (8 pins)
112 AIN Serial input of PCM stereo audio for
A D C
114 AOUT [2:0] Serial output of PCM stereo audio for
115 DAC. After reset, develop signals of
116 low level. Only AOUT [0] supports 24
bit sample width.
117 S/PDIF S/PDIF transmitter output. Possible to
(AOUT [3]) connected to DAC as the forth audio
output (AOUT [3]). After reset,
develop signal of low level.
118 A L R C L K LR clock output of AOUT [3..0] and
AIN. Becomes square waveform in
sampling frequency. Polarity of LR is
programmable.
119 A B C L K Bit clock output of AOUT [3..0] and
AIN. At rising/falling edges
(programmable) AOUT is developed
and AIN is latched.
Function
3-28
Table 3-5-5 MD36710X (4/5)
Pin
Name
No.
132 A M C L K Audio master clock I/O. 384 fs, 256 fs,
192 fs and 128 fs of sampling
frequency can be selected
(programmable).
DVD-DSP interface (13 pins)
143 D V D E R R DVD-DSP error input (Polarity
programmable)
144 D V D S O S DVD-DSP data selector start input
(Polarity programmable)
146 DVDVALID DVD-DSP data effective input
(Polarity programmable)
147 D V D S T R B DVD-DSP data bit strobe (clock)
input. Polarity programmable.
148 D V D R E Q DVD-DSP data requirement output
(Polarity programmable)
149 DVDDAT [7:0] DVD-DSP data input bus
151
|
154
156
|
158
SDRAM interface (35 pins)
38 RAMADD [11:0] SDRAM address bus output
39
42
|
47
49
|
52
54 R A M C S 0 # SDRAM chip select (active low)
output. Lower bit for 2 Mbyte device.
55 R A M C S 1 # SDRAM ship select (active low).
Upper bit for 2 Mbyte device.
56 R A M R A S # Row selection of SDRAM (active low)
output
57 P C L K SDRAM clock output (same as
internal process clock).
59 R A M C A S # Column selection of SDRAM (active
high) output
60 R A M W E # SDRAM write enable (active low)
output
61 R A M D Q M SDRAM data masking (active high)
output
62 RAMDAT [15:0] SDRAM bidirectional data bus
64
|
67
69
|
72
74
|
79
82
TEST signal (3 pins)
83 T E S T M O D E Test pin. Connects to V
127 S C N E N B L Test pin. Connects to GND for normal.
139 I C E M O D E Test pin. Connects to V
Function
for normal.
DD
for normal.
DD