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♦ Based on supply voltage, circuit impedances and logic density, IC technology is presumed to be early MOS.
♦ Gate symbols are presented in accordance with:
logic 1 = 0V, GND
logic 0 = –24V
♦ Outputs are open-collector, closing to GND (logic 1) and requiring external pull-down resistor to –24V (logic 0).
♦ Inferred for flip-flops:
The flip-flops in this logic family appear to be Master/Slave D-type flip-flops with the clocks for the master and slave sections
kept separate. This permits a system design where data capture is done in accordance with the requirements of the logic while all
outputs are changed synchronously by a single clock signal.
ØC = Capture Input (master section clock)
ØT = Transition Input (slave section clock)
The state of the D input is captured when ØC is logic 0 (–24V).
The Q output is set in accordance with the captured state when ØT goes to logic 0.
12
11
10
9
8
7
GND
µPD1
–24V
1
2
3
4
5
6
12
11
10
9
8
7
GND
µPD2
–24V
1
2
3
4
5
6
12
11
10
9
8
7
GND
µPD3
–24V
1
2
3
4
5
6
Sharp Compet 17 Calculator
Section: IC Pinouts and Gate Construction
Page: 16
Rendition: 2020 May 20
N R
1 ØnD3
17 key 4
2 ØnD7
The µPD Integrated Circuit Family
12
11
10
9
8
GND
D
ØC
D
ØC
D
µPD4
Q
ØR
ØT
Q
ØR
ØT
Q
1
2
3
4
5
10
9
8
7
6
GND
GND
ØC
D 1
ØT
In
µPD5
4-bit Shift Register
Q 4
Q 3
Q 2
Q 1
Out
Out
Out
Out
–24V
1
2
3
4
5
10
9
8
7
6
GND
D A1
Q A8
D B1
Q B8
In
Out
In
Out
µPD6
Dual 8-bit Shift Register
ØR ØT
ØC
–24V
1
2
3
4
5
N L
30 KEQ
XC3 1
31 KMC §
XC4 3
7
NEC
V380
ØC
ØR
ØT
C
D1
–24V
D2 G
6
TDA001
TDA002
1
1
2
2
3
3
4
0
4
470K
5
12
11
10
9
GND
µPD7
1
2
3
4
2 XC2
4 XC1
Discrete Gate Construction
Most OR and some AND gates are constructed from discrete diodes and
resistors. More complex logic elements are contained in integrated circuits. The
internal construction of discrete gates is shown in the following diagrams. A
wire–OR or wire–AND construction is indicated by the input line traversing the
width of the gate.
AND Gate
r
R
The diodes and resistors may be individual components or contained in
TDA001 and TDA002 packages.
Most gate outputs have load resistors ( R ) connected from the output to one
side of the power supply. To reduce clutter these resistors are indicated in the
schematic by one of the following letters ( r ) in a box near the output.
Symbol ( r )
A
B
B
E C
C
D
E
H
J
K
nn
a
b
c
5
4
3
2
1
0
d
0
Occasionally individual MOSFET transistors or MOSFETs contained in µPD7
ICs are used as AND gates. The gate of these transistors functions as an
inverted input. Because the MOSFET is a bidirectional device, a diode is usually
required on the other input or the output to prevent 'backflow' of the signal.
8
7
–24V
Special mention must be made of the unusual use of a µPD7 for the 4-bit
5
6
display latch. Controlling pin 6 allows it to function as a sample-and-hold latch,
presumably relying on inter-electrode capacitance to hold the state between
digit updates (see Display).
OR Gate
OR Gate
with 'wired' input
r
r
R
R
Resistance ( R )
15K to VDD
20K to VDD
30K to VDD
50K to VDD
100K to VDD
150K to VDD
300K to VDD
300K to VCL
470K to VCL, internal to TDA002 unit nn
40K to GND
60K to GND
100K to GND
300K to GND
NEC V380 or
G
1/4 of µPD7
D1
D2
C
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