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PLX Technology PEX 8632-AA Quick Start Manual

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PEX 8632-AA Quick Start
Hardware Design Guide
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Version 1.1
October, 2007
www.plxtech.com
www.plxtech.com/support
800 759-3735
408 774-9060
408 774-2169

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  • Page 1 PEX 8632-AA Quick Start Hardware Design Guide Version 1.1 October, 2007 Website: www.plxtech.com Support: www.plxtech.com/support Phone: 800 759-3735 408 774-9060 Fax: 408 774-2169...
  • Page 2 © 2007 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

  • Page 3: Table Of Contents

    BGA Routing Escape and De-Coupling Capacitor Placement............21 Add-In Board Routing ........................23 System Board Routing........................23 Midbus Routing..........................24 PCB Layer Stackup Considerations ....................24 References............................25 PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.
  • Page 4 Table 5. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 8-Port Mode .. 14 Table 6. Configuration Strapping Balls – 12-Port Mode ................15 Table 7. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements – 12-Port Mode 16 PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 5: Preface

    Configuration signal names, October 16, 2007 and added new STRAP_RESERVED tables. Renumbered existing tables accordingly. Applied miscellaneous corrections and enhancements. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.
  • Page 6 THIS PAGE INTENTIONALLY LEFT BLANK. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 viii © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 7: Introduction

    Introduction This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8632 PCI Express Switch and provides examples of how to connect to the various switch interfaces. Switch Interfaces The PEX 8632 device is a 32-Lane, 8- or 12-Port Gen2 switch, designed for high-availability and high-performance systems.

  • Page 8: Pci Express Link Interface

    PCI Express Link. Device 1 Device 2 Channel CDR1 PLL2 Channel CDR2 PLL1 RefClk Figure 1. Sample PCI Express Link Block Diagram PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 9: Transmitter

    The standard de-emphasis level is selectable by way of the PEX 8632 Link Control 2 register Selectable De-Emphasis bit (Configuration register, offset 98h[6]). 400mV VTX-DC-CM TXp - TXn 800mV Figure 2. Single-Ended versus Differential Voltage PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.
  • Page 10 = 750 mV + 162.5 mV = 912.5 mVpp TRANS 750 mV - 162.5 mV = 587.5 mVpp NON-TRANS = 20 log (587.5/912.5) = -3.82 dB TX-DE-RATIO-3.5 DB PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 11: Receiver

    4 each control 12 SerDes, and Port 8 controls 10 SerDes. Each individual SerDes has a 4-bit control word. Table 1 describes the Receiver equalization effects. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 12: Reference Clock

    DC-biasing circuit, and therefore, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603- or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 13: Channel

    Channel length is allowable is to simulate the Channel, using PLX-provided HSPICE models. The PCI Express Base Specification, Revision 2.0, provides additional details for simulating a Channel. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 14: Nt Function

    NT functions, through the PEX 8632’s NT Strapping balls. Figure 5. Enable NT Function with NT Strapping Balls Figure 6. Disable NT Function with NT Strapping Balls PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 15: Hot Plug Controller Interface

    PEX 8632’s PHPC to the external circuit, to build a complete PHPC circuit. Figure 7. PHPC Circuit Block Diagram PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 16: Figure 8. Shpc Interface To Pex 8632 Block Diagram

    Perst# IO 5/21 Interlock INT# IO[10:7]/[26:23] Sltid[3:0] IO 6/22 GPIO AD[2:0] MAX7311 or PCA9698 Figure 8. SHPC Interface to PEX 8632 Block Diagram PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 17: Jtag Interface

    25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to improve signal quality. Figure 9 illustrates a generic JTAG interconnection. Figure 9. JTAG Interface Block Diagram PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 18: C Interface

    PEX 8632 Port. Each Port has five states, which are related to Link Status, Channel Speed, and the Port’s Lane width. Table 2 lists the relationship of the LED On/Off patterns to the Port status. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 19: Strapping Balls

    STRAP_STN0_PORTCFG0 STRAP_STN0_PORTCFG1 Port configuration per Station. STRAP_STN1_PORTCFG0 STRAP_STN1_PORTCFG1 STRAP_TESTMODE0 STRAP_TESTMODE1 Test mode function select. STRAP_TESTMODE2 STRAP_TESTMODE3 STRAP_UPSTRM_PORTSEL0 STRAP_UPSTRM_PORTSEL1 Upstream Port select. STRAP_UPSTRM_PORTSEL2 STRAP_UPSTRM_PORTSEL3 PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 20: Table 4. Active Lanes - 8- And 12-Port Modes

    STRAP_RESERVED8 Must be tied High STRAP_RESERVED9 Must be tied High STRAP_RESERVED16 Must be tied directly to Ground (VSS) STRAP_RESERVED17# Must be tied High PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 21: Strapping Balls - 12 Port Mode

    STRAP_STN1_PORTCFG0 Port configuration per station. STRAP_STN1_PORTCFG1 STRAP_STN2_PORTCFG0 STRAP_STN2_PORTCFG1 STRAP_TESTMODE0 STRAP_TESTMODE1 Test mode function select. STRAP_TESTMODE2 STRAP_TESTMODE3 STRAP_UPSTRM_PORTSEL0 STRAP_UPSTRM_PORTSEL1 Upstream Port select. STRAP_UPSTRM_PORTSEL2 STRAP_UPSTRM_PORTSEL3 PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 22: Gpio Balls

    STRAP_TESTMODE[3:0], the GPIO balls can be set as input, output, and/or bidirectional. The eight dedicated GPIO balls can also be configured as PERST# outputs for the SHPC, when the PEX 8632 is reset. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 23: Power Supplies, Sequencing, And De-Coupling

    The recommendation is that 0201-sized capacsitors be used in close proximity to these power balls, as illustrated in Figure VDD10 VDD10A 1000 pF 0201 Figure 11. Power Balls and Capacitor Placement PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 24: Power Sequencing

    Power supplies isolated through the use of ferrite beads typically have limited access to interplane capacitance, which might have an adverse effect on a given supply rail. 1.9.2 Power Sequencing There is no power sequencing requirement. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 25: Board-Level De-Coupling

    3.3V 2.5V 1.5V 0.0100 1.0V 0.0010 0.0001 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency - Hz Figure 12. Power Plane Impedance versus Frequency PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 26: Figure 13. Capacitor Footprint Effects On Series Inductance

    Figure 13 illustrates examples of how various footprints for 0603-size capacitors can change series inductance. Figure 13. Capacitor Footprint Effects on Series Inductance PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 27: Pcb Layout And Layer Stackup Considerations

    Figure 11 on page illustrates the placements of 0201 de-coupling capacitors underneath the PEX 8632. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 28: Figure 14. Top Layer Bga Layout And Routing Escape

    Figure 14. Top Layer BGA Layout and Routing Escape Figure 15. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 29: Add-In Board Routing

    Differential pairs for PCI Express Gen2 system boards should have a differential impedance between 68 to 105 ohms (85 ohms, nominal). Figure 17. System Board Routing to PCI Express Slot PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 30: Midbus Routing

    Typically, stripline traces are only available for PCBs with six or more layers. Microstrip and stripline traces each have their own properties, which must be weighed when determining which type of trace to use. PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

  • Page 31: References

    PCI Express Card Electromechanical (CEM) Specification, Revision 2.0 Right the First Time: A Practical Handbook on High Speed PCB and System Design, by Lee Ritchie PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1 © 2007 PLX Technology, Inc. All Rights Reserved.

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