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TDO, TDI
TCK, TMS
TRST_N, TAPSEL
TSI_CLK, TSI_FRAME,
TSI_VALID, TSI_DATA
IF_AGC, AGC_SENSE, RF_AGC,
PW M_OUT
SADATA, GPIOx, GPIO,
IFE_AIMP, IFE_VREFP, IFE_VREFN,
IFE_AINN, IFE_RBIAS, IFE_VCM, IFE_VINBIAS
TSO_CLK, TSO_FRAME,
TSO_VALID, TSO_DATA
HDMI_SCL, HDMI_SDA,
HDMI_CEC, HDMI_HPD, HDMI_REXT,
HDMI_D0P, HDMI_D0N, HDMI_D1P,
HDMI_D1N, HDMI_D2P, HDMID2N,
HDMI_CLKP, HDMI_CLKN
VFE_YIN, VFE_CIN,
VFE_CVBS,VFE_REFP, VFE_REFN,
VFE_VCM, VFE_IBEXT, VFE_BG
UART0_TX, UART0_RX
UART1_TX, UART1_RX
I2C0C, I2C0D
I2C1C, I2C1D
I2C2C, I2C2D
GPIO[3:0]
SPI_CLK, SPI_SI, SPI_SO,
SPI_HOLD, SPI_W EN
GADR[4:0]
GDAT[7:0]
GCS_n[5:0]
GDIR, GOE_n, GIOW R_n, GIORD_n, GWE_n
GW S_ACK
GIRQ[3:0]
10/10/06
SupraHD-760-DTS-GEN-v1.0-Preliminary Release
Embedded
Processing Unit
(EPC)
MIPS 4Kec
I Cache
D Cache
MMU
6
EJTAG
Ctlr.
JTAG
Counters/
Ctlr.
Timers
Transport
Processing Unit
(TRP)
4
Xport I/F
Xport Demux
4
AGC
Smart
3
Antenna
7
Demod
4
Video Capture
Unit
13
HDMI
HDMI
PHY
NTSC/PAL
8
Decoder
Flex Bus Unit
(FBU)
2
UART0
2
UART1
2
I2C Ctlr. 1
2
I2C Ctlr. 2
2
I2C Ctlr. 3
4
GPIO
1
IRR
IRR
5
SPI
5
8
6
Modified
5
Guest Bus
1
4
Figure 3: SupraHD-760 Detailed Block Diagram
CONFIDENTIAL INFORMATION-DO NOT COPY
October 10, 2006 11:23 am
BVCI
Memory
Interface Unit
(MIF)
Audio
Processing Unit
(APU)
L/R
Audio
DACs
Display
Processor
(DPC)
Graphics
Video I/F
LVDS Output
MPEG2 Decode
Unit
(VDEC)
uController
(MCU)
Sequencer
(MCE)
BLT
Link List
CLKGEN
DVCXO
PLL
Unique 128-bit
ID
ZR39760
16
SADR[13:0], SBS[1:0]_n
4
SDQM[3:0]
3
SRAS_n, SCAS_n, SW E_n
3
SCLK, SCLK_n, SCKE
4
SDQS[3:0],
16
SDATA[15:0]
SVREF
ACLK
BCLK, LRCLK
10
ADATAO[2:0]
ADATAI[2:0]
IEC958
Shared
4
ADATAO[2:0]
with the
ADATAI[2]
I2S
signals
PIXOUT[23:0],PCLK, DEN, OSDP,
AFHSI, AFVSI
LVDS_C_P, LVDS_C_N,
LVDS_D[7:0]_P, LVDS_D[7:0]_N
LVDS_REXT
2
CLKIN,
CLKOUT
RESET_n
4
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