Watchdog Timer Registers - Asus AAEON AHP-1154 User Manual

A.1

Watchdog Timer Registers

Table 1: Watch dog relative IO address
I/O Base Default Value
Address
0xA00
Table 2: Watchdog relative register table
Register Offset
Watchdog 0x00
WDTRST#
Enable
Pulse Width 0x05
Signal Polarity 0x05
Counting Unit 0x05
Output Signal 0x05
Type
Watchdog Timer 0x05
Enable
Timeout Status 0x05
Timer Counter 0x06
Appendix A – Watchdog Timer Programming
Note
I/O Base address for Watchdog operation.
This address is assigned by SIO LDN7, register
0x60‐0x61.
BitNum Value
7 1
0:1 01
2 0
3 0
4 1
5 1
6 1
Note
Enable/Disable
time out output via WDTRST#
0: Disable
1: Enable
Width of Pulse signal
00: 1ms (do not use)
01: 25ms
10: 125ms
11: 5s
Pulse width is must longer than
16ms.
0: low active
1: high active
Must set this bit to 0
Select time unit.
0: second
1: minute
0: Level
1: Pulse
Must set this bit to 1
0: Disable
1: Enable
1: timeout occurred. Write a 1 to
clear timeout status
Time of watchdog timer
(0~255)
49