1. Manuals
  2. Brands
  3. Avnet Manuals
  4. Control Unit
  5. PicoZed 7010
  6. Hardware user's manual

Avnet PicoZed 7010 Hardware User's Manual

Som (system-on module)
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Zynq
7010 / 7020
SOM
(System-On Module)
Hardware
User Guide
Version 1.4
2/3/2015

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PicoZed 7010 and is the answer not in the manual?

Questions and answers

Related Manuals for Avnet PicoZed 7010

Summary of Contents for Avnet PicoZed 7010

  • Page 1 Zynq 7010 / 7020 (System-On Module) Hardware User Guide Version 1.4 2/3/2015...

  • Page 2: Table Of Contents

    Table of Contents INTRODUCTION ..........................2 FUNCTIONAL DESCRIPTION ......................3 C ......................3 ROGRAMMABLE ............................3 EMORY 2.2.1 DDR3L ............................ 3 2.2.2 Quad-SPI Flash ........................4 2.2.3 eMMC (Multi-Media Controller).................... 5 USB 2.0 OTG..........................6 10/100/1000 E PHY ......................7 THERNET I/O ............................

  • Page 3: Introduction

    VCCPAUX, VCCPLL, VCCO_0, VCCO_DDR, VCCO_MIO1 and VCCO_MIO0 VCCO_34, VCCO_35, and VCCO_13 are powered from Expansion Card via Three 100-pin Micro Headers  Software Vivado Design Suite  Download from www.xilinx.com/support/download.html  Request a free DVD from www.xilinx.com/onlinestore/dvd_fulfillment_request.htm Figure 1 – PicoZed 7010/7020 Block Diagram 3-Feb-2015...

  • Page 4: Functional Description

    The DDR3L interface is designed to use 1.35V SSTL-compatible inputs by default. There is an option to support 1.5V capable DDR3 devices via a resistor change on the PicoZed 7010/7020. This option is provided as a note on the PicoZed 7010/7020 schematics.

  • Page 5: Quad-Spi Flash

    2.2.2 Quad-SPI Flash PicoZed 7010/7020 features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL128S (S25FL128SAGBHIA00) is used on this board. The Multi-I/O SPI Flash memory is used to provide non-volatile boot, application code, and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem (bitstream).

  • Page 6: Emmc (Multi-Media Controller)

    This option offers the user the most flexibility to connect either interface to the Zynq when needed by the application. Software control of the Multiplexer Select signal is the default setting for the PicoZed 7010/7020 System-On-Module from the factory, and is enabled by the jumper resistor position at JT1 position 1-2.

  • Page 7: Usb 2.0 Otg

    480Mbs. VDDIO for this device can be 1.8V or 3.3V, and on the PicoZed 7010/7020 is powered at 1.8V. The PHY is connected to MIO Bank 1/501, which is also powered at 1.8V. This is critical since a level translator cannot be used as it would impact the tight ULPI timing required between the PHY and the Zynq device.

  • Page 8: 10/100/1000 Ethernet Phy

    USB3320 Pin 27 RESET. PicoZed 7010/7020 is configured such that either Host Mode (OTG) or Device Mode can be used depending on the circuitry of the carrier card. With a standard connection to a baseboard (no power supply used to provide USB power to the connector) the device will operate in Device Mode.
  • Page 9 ** Requires a resistor change to the board to use PHY Reset. By default MIO47 is routed to JX3. The datasheet for the Marvell 88E1512 is not available publicly. An NDA is required for this information. Please contact your local Avnet or Marvell representative for assistance. 3-Feb-2015...

  • Page 10: User I/O

    Zynq-7000 AP SoC. Additionally, the PicoZed 7020 version provides access to 25 more user PL IO pins from bank 13. The 100 PL IO pins on the PicoZed 7010 and the 125 PL IO pins on the PicoZed 7020 connect to the Zynq Programmable Logic Sub-System for user implementation of any feasible interface.

  • Page 11: Clock Source

    If an expansion card is connected to PicoZed 7010/7020, the expansion card should also wire-OR to this net and not release it until the expansion card power is also good. Review the PicoZed 7010/7020 schematic for other devices that are reset by the PG_MODULE open drain signal.

  • Page 12: Expansion Headers

    Each pin can carry 500mA of current and support I/O speeds in excess of what Zynq can achieve. PicoZed 7010/7020 does not power the PL VCCIO banks. This is required to be provided by the carrier card. This gives the carrier card the flexibility to control the I/O bank voltages. Separate routes/planes are used for VCCO_34 and VCCO_35 such that the carrier card could potentially power these independently.
  • Page 13 The diagrams listed below illustrate the connections on the Micro Headers. Table 8 – Micro Header JX1 and JX2 Pin Outs Micro Header #1 (JX1) Micro Header #2 (JX2) Signal Name Source Pins Signal Name Source Pins Bank 34 I/Os (Except for Zynq Bank 34 Bank 35 I/Os...
  • Page 14 Table 10 – JX1 Connections PicoZed PicoZed 7010/7020 Net Name Net Name 7010/7020 Pin # Pin # Pin # Pin # 0 - F9 JTAG_TCK JTAG_TMS 0 - J6 0 - F6 JTAG_TDO JTAG_TDI 0 - G6 PWR_ENABLE CARRIER_SRST# 501 - B10 0 - F11 FPGA_VBATT FPGA_DONE...
  • Page 15 Table 11 – JX2 Connections PicoZed PicoZed 7010/7020 PicoZed Net PicoZed Net 7010/7020 Pin # Pin # Pin # Pin # 500 – E8 500 - E9 PS_MIO10 PS_MIO13 500 – C8 500 - C5 PS_MIO14 PS_MIO15 500 – C6 500 - D9 PS_MIO12 PS_MIO11...
  • Page 16 Table 12 – JX3 Connections PicoZed PicoZed 7010/7020 PicoZed Net PicoZed Net 7010/7020 Pin # Pin # Pin # Pin # MGTREFCLK0_P MGTREFCLK1_P MGTREFCLK0_N MGTREFCLK1_N MGTAVCC MGTAVCC MGTRX0_P MGTAVCC MGTRX0_N MGTAVCC MGTTX0_P MGTRX1_P MGTTX0_N MGTRX1_N MGTTX1_P MGTRX2_P MGTTX1_N MGTRX2_N MGTTX2_P MGTRX3_P MGTTX2_N MGTRX3_N...

  • Page 17: Configuration Modes

    NOR, NAND, Quad-SPI, SD Card or JTAG. PicoZed 7010/7020 allows 3 of those boot devices: QSPI is the default, while SD Card and JTAG boot are easily accessible by changing switch settings.

  • Page 18: Jtag Connections

    INIT_B as this is now done with POR. If the application needs to reconfigure the PL, the software design must do this, or you can toggle POR to restart everything. When PL configuration is complete and the end user is using the Avnet PicoZed FMC Carrier Card, a blue LED will illuminate.

  • Page 19: Power Supplies

    PicoZed 7010/7020 is powered through the Micro Header connection between itself and the carrier card. There are five regulators that reside on the PicoZed 7010/7020 that provide 1.0V, 1.35V, 1.8V, 3.3V and 0.675V power rails. These voltages are used to power the peripheral devices on the PicoZed System-On-Module.

  • Page 20: Voltage Regulators

    This circuit sequences power-up of PicoZed 7010/7020. 1.0V comes up first, then 1.8V, then VCCO_DDR3 and then 3.3V. PG_MODULE is connected to PS_POR_B on Zynq, thus when the power supplies are valid, PS_POR_B is released. When the PicoZed 7010/7020 is mated to an end user carrier card, the POWER GOOD outputs 3-Feb-2015...

  • Page 21: Power Supply Sequencing

    PicoZed 7010/7020 also provides a power good signal to the end user carrier card to signal that Vccint and Vccaux are both up and the end user carrier card is free to bring up the Vcco supplies.
  • Page 22 ** VCCIO driven from end user carrier card Figure 7 – Power Supply Sequencing As noted above, if connected to an end user carrier card, the 1.8V power supply’s power good output should is used as the enable to the VCCIO regulators via the PG_1V8 (VCCIO_EN) signal on the Micro Headers.

  • Page 23: Pcb Bypass / Decoupling Strategy

    2.10.4 PCB Bypass / Decoupling Strategy The PicoZed 7010/7020 design follows the PCB decoupling strategy as outlined in UG933 for the 7Z020, CLG400 package. The PicoZed 7010 depopulates a few of these capacitors while maintaining the listed requirements. Figure 9 – CLG400 PL Decoupling Figure 10 –...

  • Page 24: Battery Backup - Device Secure Boot Encryption Key

    This header provides two ground connections and one connection to the VIN voltage. PicoZed 7010/7020 also provides a resistor option for a 3.3V fan via JT3. Two mounting holes (MTG[3:4]) near the Zynq device are provided where an active or passive heat sink might be secured.

  • Page 25: Zynq-7000 Ap Soc I/O Bank Allocation

    Zynq-7000 AP SoC I/O Bank Allocation PS MIO Allocation There are 54 I/O available in the PS MIO. The table below lists the number of required I/O per peripheral and the MIO locations where the interface exists. Table 17 – PS MIO Interface Requirements Interface I/O Required QSPI FLASH...

  • Page 26: Zynq-7000 Ap Soc Bank Voltages

    PL I/O Banks 34, 35, and 13 are powered from the end user carrier card. These bank supplies are designed to be independent on the PicoZed 7010/7020. Maximum flexibility is allowed to the designer for these banks as the voltage level and standards are left to the end user carrier card design.

  • Page 27: Mechanical

    4 Mechanical PicoZed 7010/7020 measures 2.25” x 4.00” (57.15 mm x 101.6 mm) Figure 12 – PicoZed 7010/7020 Top View Mechanical Dimensions PicoZed 7010/7020 has a maximum vertical dimension of 0.366” (9.3mm) Figure 13 – PicoZed 7010/7020 Side View Vertical Dimension...

  • Page 28: Revision History

    5 Revision History Rev date Rev # Reason for change 6 Oct 14 Initial PicoZed 7010/7020 Hardware User Guide 30 Oct 14 DDR3L documented and Diagram Updates 2 Dec 14 Diagram Update Figure 5 and PL IO LVDS support 8 Dec 14...

This manual is also suitable for:

Picozed 7020

Table of Contents