Panasonic TDA 100 Service Manual page 61

Pin No. Pin Name
92 WE3/DQMUU/ICIOW
R/PTK[7]
93 RD/WR
94 AUDSYNC/PTE[7]
95 VssQ
96 CS0/MCS[0]
97 VccQ
98 CS2/PTK[0]
99 CS3/PTK[1]
100 CS4/PTK[2]
101 CS5/PTK[3]
102 CS6/CE1B
103 CE2A/PTE[4]
104 CE2B/PTE[5]
105 CKE/PTK[5]
106 RAS3L/PTJ[0]
107 PTJ[1]
108 CASL/PTJ[2]
109 VssQ
110 CASU/PTJ[3]
111 VssQ
112 PTJ[4]
113 PTJ[5]
114 DACK0/PTD[5]
115 DACK1/PTD[7]
116 PTE[6}
117 PTE[3}
118 RAS3U/PTE[2]
119 PTE[1]
120 TDO/PTE[0]
121 BACK
122 BREQ
123 WAIT
124 RESETM
125 ADTRG/PTH[2]
126 IOIS16/PTG[7]
127 ASEMD0/PTG[6]
128 ASEBRKAK/PTG[5]
129 PTG[4]/CKIO2
130 AUDATA[3]/PTG[3]
131 AUDATA[2]/PTG[2]
132 Vss
- Vss
133 AUDATA[1]/PTG[1]
134 Vcc
- Vcc
135 AUDATA[0]/PTG[0]
136 TRST/PTF[7]/PINT[15]
137 TMS/PTF[6]/PINT[14]
138 TDI/PTF[5]/PINT[13]
139 TCK/PTF[4]/PINT[12]
140 IRS3/PTF[3]/PINT[11]
141 IRS2/PTF[2]/PINT[10]
142 IRS1/PTF[1]/PINT[9]
143 IRS0/PTF[0]/PINT[8]
144 MD0
145 Vcc-PLL1*2
146 CAP1
147 Vss-PLL1*2
148 Vss-PLL2*2
149 CAP2
150 Vcc-PLL2*2
151 AUDCK/PTH[6]
152 Vss
153 Vss
- Vss
154 Vcc
I/O
O/I/O D31-D24 select signal/DOM (SDRAM) /PCMCIA I/O write/I/O port K
O Read/Write
O/I/O AUD synchronization/I/O port E
- Power for I/O (0V)
O Chip select 0/mask ROM chip select 0
- Power for I/O (3.3V)
O/I/O Chip select 2/I/O port K
O/I/O Chip select 3/I/O port K
O/I/O Chip select 4/I/O port K
O/I/O Chip select 5/CE1 (Area 5PCMCIA)/I/O port K
O Chip select 6/CE1 (Area 6PCMCIA)
O/I/O CE2(Area 5PCMCIA)/ I/O port K
O/I/O CE2(Area 6PCMCIA)/ I/O port K
O/I/O CK Enable (SDRAM) / I/O port K
O/I/O RAS for low 32M/64M bytes address (SDRAM) /I/O port J
I/O I/O port J
O/I/O RAS for low 32M/64M bytes address (SDRAM) /I/O port J
- Power for I/O (0V)
O/I/O RAS for low 32M bytes address (SDRAM) /I/O port J
- Power for I/O (3.3V)
I/O I/O port J
I/O I/O port J
O/I/O DMA acknowledge0/I/O port D
O/I/O DMA acknowledge1/I/O port D
I/O I/O port E
I/O I/O port E
O/I/O RAS for low 32M bytes address (SDRAM) / I/O port E
I/O I/O port E
O/I/O Test data output/I/O port E
O Bus acknowledge
I Bus request
I Hardware wait request
I Manual reset request
I Analog trigger/input port H
I IOIS168 (PCMCI) / I/O port G
I ASE mode:4/I/O port G
I/O ASE break acknowledge/I/O port G
I/O Input port G/clock output
I/O/I AUD data/input port G
I/O/I AUD data/input port G
- Power supply (0V)
- Power supply (0V)
I/O/I AUD data/input port G
- Power supply (*3)
- Power supply (*3)
I/O/I AUD data/input port G
I Test reset/input port F/port interruption
I Test mode switch/input port F/port interruption
I Test mode switch/input port F/port interruption
I Test clock/input port F/port interruption
I External interrupt request/input port F/port interruption
I External interrupt request/input port F/port interruption
I External interrupt request/input port F/port interruption
I External interrupt request/input port F/port interruption
I Clock mode setting
- Power for PLL1 (*3)
- External capacity terminal for PLL1
- Power for PLL1 (0V)
- Power for PLL1 (1V)
- External capacity terminal for PLL2
- Power for PLL2 (*3)
I AUD clock/input port H
- Power supply (0V)
- Power supply (0V)
- Power supply (0V)
- Power supply (*3)
61
Description
KX-TDA100CE