NEC V854 UPD703006 User Manual

32/16-bit single-chip microcontroller hardware

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User's Manual

V854

32/16-Bit Single-Chip Microcontroller

Hardware

µ PD703006

µ PD703008

µ PD70F3008

µ PD703008Y

µ PD70F3008Y

Document No.

U11969EJ3V0UM00 (3rd edition)

Date Published March 1999 N CP(K)

1997

Printed in Japan

Table of Contents

Summary of Contents for NEC V854 UPD703006

Page 1 User’s Manual V854 32/16-Bit Single-Chip Microcontroller Hardware µ PD703006 µ PD703008 µ PD70F3008 µ PD703008Y µ PD70F3008Y Document No. U11969EJ3V0UM00 (3rd edition) Date Published March 1999 N CP(K) © 1997 Printed in Japan...
Page 2 [MEMO] User’s Manual U11969EJ3V0UM00...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. V854, and V850 Family are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries.
Page 4 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability •...
Page 6 Major Revisions in This Edition Page Contents Throughout Deletion of BV and BV Modification of voltage of V Addition of µ PD703006 to the target devices p.44 Modification of description in 2.3 (19) MODE0 to MODE2 (Mode 0 to 2) p.47 Modification of recommended connection method for pins P40/AD0 to P47/AD7, P50/AD8 to P57/AD15, P60/A16 to P67/A23, P90/LBEN/WRL, P91/UBEN, P92/R/W/WRH, P93/...
Page 7 INTRODUCTION Readers This manual is intended for users who understand the functions of the V854 ( µ PD703006, 703008, 70F3008, 703008Y, 70F3008Y) and design application systems using the V854. Purpose This manual is intended to enable users to understand the hardware functions described in the Organization below.
Page 8 Related documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents related to devices Document Name Document No. V850 Family Architecture User’s Manual U10243E V850 Family Instruction Table U10229E µ...
Page 9: Table Of Contents
TABLE OF CONTENTS CHAPTER 1 INTRODUCTION ......................23 1.1 General ............................. 23 1.2 Features ........................... 24 1.3 Application Fields ........................25 1.4 Ordering Information ......................25 1.5 Pin Identification (Top View) ....................26 1.6 Function Block Configuration ....................28 1.6.1 Internal block diagram .........................
Page 10 4.3.2 Bus width ............................84 4.4 Memory Block Function ......................85 4.5 Wait Function .......................... 86 4.5.1 Programmable wait function ......................86 4.5.2 External wait function ........................87 4.5.3 Relations between programmable wait and external wait ............87 4.6 Idle State Insertion Function ....................88 4.7 Bus Hold Function ........................
Page 11 5.8 Periods Where Interrupt is Not Acknowledged ..............133 CHAPTER 6 CLOCK GENERATOR FUNCTION ................135 6.1 Features ..........................135 6.2 Configuration ......................... 135 6.3 Selecting Input Clock ......................136 6.3.1 Direct mode ..........................136 6.3.2 PLL mode ........................... 136 6.3.3 Clock control register (CKC) .....................
Page 12 7.6.2 Count clock selection ......................... 188 7.6.3 Overflow ............................. 189 7.6.4 Clearing/starting timer ....................... 189 7.6.5 Compare operation ........................189 7.6.6 Toggle output ..........................191 7.7 Timer 3 Operation ......................... 192 7.7.1 Count operation ......................... 192 7.7.2 Count clock selection ......................... 192 7.7.3 Overflow .............................
Page 13 CHAPTER 9 A/D CONVERTER ......................295 9.1 Features ..........................295 9.2 Configuration ......................... 295 9.3 Control Register ........................297 9.4 A/D Converter Operation ..................... 301 9.4.1 Basic operation of A/D converter ....................301 9.4.2 Operation mode and trigger mode .................... 301 9.5 Operation in the A/D Trigger Mode ..................
Page 14 12.3.4 Port 3 ............................354 12.3.5 Port 4 ............................357 12.3.6 Port 5 ............................359 12.3.7 Port 6 ............................361 12.3.8 Port 7, port 8 ..........................363 12.3.9 Port 9 ............................364 12.3.10 Port 10 ............................366 12.3.11 Port 11 ............................368 12.3.12 Port 12 ............................
Page 15 APPENDIX A REGISTER INDEX ....................... 397 APPENDIX B INSTRUCTION SET LIST ................... 403 APPENDIX C INDEX ........................... 409 User’s Manual U11969EJ3V0UM00...
Page 16 LIST OF FIGURES (1/4) Figure No. Title Page 3-1. Program Counter (PC) ........................ 51 3-2. Interrupt Source Register (ECR) ....................52 3-3. Program Status Word (PSW) ..................... 53 3-4. CPU Address Space ........................56 3-5. Image on Address Space ......................57 3-6.
Page 17 LIST OF FIGURES (2/4) Figure No. Title Page 7-10. Example of TM0 Compare Operation (set/reset output mode) ..........182 7-11. Basic Operation of Timer 1 ....................... 183 7-12. Operation after Occurrence of Overflow (OST1 = 1) .............. 185 7-13. Clearing/Starting Timer by Software (when OST1 = 1) ............185 7-14.
Page 18 LIST OF FIGURES (3/4) Figure No. Title Page 8-18. Acknowledge Signal ........................246 8-19. Stop Condition ........................... 247 8-20. Wait Signal ..........................248 8-21. Example of Arbitration Timing ....................272 8-22. Communication Reservation Timing ..................274 8-23. Communication Reservation Procedure ................... 275 8-24.
Page 19 LIST OF FIGURES (4/4) Figure No. Title Page 12-1. Block Diagram of Type A ......................342 12-2. Block Diagram of Type B ......................342 12-3. Block Diagram of Type C ......................343 12-4. Block Diagram of Type D ......................343 12-5.
Page 20 LIST OF TABLES (1/2) Table No. Title Page 3-1. Program Registers ........................51 3-2. System Register Numbers ......................52 3-3. Interrupt/Exception Table ......................61 4-1. Bus Priority ..........................97 5-1. Interrupt List ..........................100 6-1. Operation of Clock Generator by Power Save Control ............141 6-2.
Page 21 LIST OF TABLES (2/2) Table No. Title Page 9-8. Correspondence between Analog Input Pin and ADCRn Register (4-buffer mode (external trigger select 4-buffer)) ..............317 9-9. Correspondence between Analog Input Pin and ADCRn Register (scan mode (external trigger scan)) ..................318 13-1.
Page 22 [MEMO] User’s Manual U11969EJ3V0UM00...
Page 23: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V854 is a product of NEC’s V850 Family single-chip microcontrollers for real-time control applications. This chapter briefly outlines the V854. 1.1 General The V854 is a 32-/16-bit single-chip microcontroller that employs the CPU core of the V850 Family of high- performance 32-bit single-chip microcontrollers for real-time control applications, and integrates peripheral functions such as ROM/RAM, real-time pulse unit, serial interface, A/D converter, and PWM.
Page 24: Features
CHAPTER 1 INTRODUCTION 1.2 Features Number of instructions : 74 Minimum instruction execution time : 30 ns (at internal 33 MHz) General register : 32 bits x 32 : Signed multiply (16 bits x 16 bits → 32 bits): 1 to 2 clocks Instruction set Saturated operation instructions (with overflow/underflow detection function)
Page 25: Application Fields
CHAPTER 1 INTRODUCTION PWM (Pulse Width Modulation) : 12- to 16-bit resolution PWM: 4 ch A/D converter : 8-bit resolution A/D converter: 16 ch Clock generator : Multiplication function by PLL clock synthesizer (multiplication by one or five) 2-frequency division function by external clock Power save function : HALT/IDLE/software STOP mode Clock output stop function...
Page 26: Pin Identification (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Identification (Top View) P87/ANI15 CLKOUT P86/ANI14 WAIT P85/ANI13 P96/HLDRQ P84/ANI12 P95/HLDAK P83/ANI11 P94/ASTB P82/ANI10 P93/DSTB/RD P81/ANI9 P92/R/W/WRH P80/ANI8 P91/UBEN P77/ANI7 P90/LBEN/WRL P76/ANI6 P67/A23 P75/ANI5 P66/A22 P74/ANI4 P65/A21 P73/ANI3 P64/A20 P72/ANI2 P63/A19 P71/ANI1 P62/A18 P70/ANI0 P61/A17 P60/A16 P57/AD15 P16/TI20/INTP20...
Page 27 CHAPTER 1 INTRODUCTION Pin name P00 to P07 : Port0 P10 to P17 : Port1 A16 to A23 : Address Bus P20 to P26 : Port2 AD0 to AD15 : Address/Data Bus P30 to P36 : Port3 ADTRG : AD Trigger Input P40 to P47 : Port4 ANI0 to ANI15 : Analog Input...
Page 28: Function Block Configuration
CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration 1.6.1 Internal block diagram ASTB Instruction DSTB queue INTC INTP00 to INTP05 INTP10 to INTP14 UBEN INTP20 to INTP24 Note 32-bit LBEN barrel shifter INTP30 Multiplier WAIT INTP50 to INTP53 16 x 16 → 32 A16 to A23 System AD0 to AD15...
Page 29: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU Executes almost all instruction processing such as address calculation, arithmetic/logic operation, and data transfer in 1 clock by using a 5-stage pipeline. Dedicated hardware devices such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) are provided to increase the speed of processing complicated instructions.
Page 30 CHAPTER 1 INTRODUCTION (9) Ports The ports have functions as general ports and functions as control pins as shown below. Port Port Function Control Function Port0 8-bit I/O General port Timer I/O, external interrupt Port1 Port2 1-bit input, NMI, A/D converter trigger, external interrupt 6-bit I/O Port3 7-bit I/O...
Page 31: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The following table shows the names and functions of the V854’s pins. These pins can be divided by function into port pins and other pins. 2.1 Pin Function List (1) Port pins (1/2) Pin Name Function Alternate Function TO00 Port 0.
Page 32 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Function Alternate Function P50 to P57 Port 5. AD8 to AD15 8-bit I/O port. Can be specified in input/output mode in 1-bit units. P60 to P67 Port 6. A16 to A23 8-bit I/O port. Can be specified in input/output mode in 1-bit units.
Page 33 CHAPTER 2 PIN FUNCTIONS (2) Pins other than port pins (1/3) Pin Name Function Alternate Function TO00 Output Pulse signal output from timer 0 and 2. TO01 TO20 TO21 P110 TO22 P112 TO23 P114 TO24 P116 TCLR0 Input External clear signal input to timer 0. P06/INTP04 Input External count clock input to timer 0, 1, and 2.
Page 34 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function Output Serial transmit data output from CSI0 to CSI3 (3-wire). P30/TXD P33/SDA P120 P123 Input Serial receive data input to CSI0 to CSI3 (3-wire). P31/RXD P121 P124 SCK0 Serial clock I/O from/to CSI0 to CSI3 (3-wire). SCK1 P35/SCL SCK2...
Page 35 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function WAIT Input Control signal input inserting wait state to bus cycle. – MODE0 to MODE2 Input Specifies operation mode. – RESET Input System reset input. – Input System clock oscillator connecting pins. Supply external clock to X1. –...
Page 36: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The operating status of each pin in each operation mode is as follows: Operating Status Software IDLE Idle HALT STOP Reset Mode Hold State Mode Mode AD0 to AD15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 1...
Page 37: Pin Function
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Function (1) P00 to P07 (Port0) ... 3-state I/O These pins constitute an 8-bit I/O port, port 0. They also serves as control signal pins. P00 to P07 function not only as I/O port pins, but also as the I/O pins of the real-time pulse unit (RPU) and external interrupt request input pins.
Page 38 CHAPTER 2 PIN FUNCTIONS (3) P20 to P26 (Port 2) ... 3-state I/O These pins constitute an I/O port, port 2, which can be set in the input or output mode in 1-bit units, except P20, which is an input only pin. These pins function not only as port pins but also as NMI input, external interrupt request input, and A/D converter external trigger.
Page 39 CHAPTER 2 PIN FUNCTIONS SO0, SO1 (Serial Output 0, 1) ... output These are serial transmit data output pin for the CSI. Since SO1 is open drain output, connect external pull-up resistor. (vi) SI0, SI1 (Serial Input 0, 1) ... input These are serial receive data input pin for the CSI.
Page 40 CHAPTER 2 PIN FUNCTIONS AD8 to AD15 (Address/Data 8 to 15) ... 3-state I/O These pins constitute a multiplexed address/data bus when the external memory is accessed. They function as the A8 to A15 output pins of a 24-bit address in the address timing (T1 state), and as the higher 8-bit data I/O bus pins of 16-bit data in the data timing (T2, TW, T3).
Page 41 CHAPTER 2 PIN FUNCTIONS (9) P90 to P96 (Port 9) ... 3-state I/O These pins constitute a 7-bit I/O port, port 9, and are also used to output control signals. P90 to P96 function not only as I/O port pins but also as control signal output pins and bus hold control signal output pins in the control mode (external expansion mode) when an external memory is used.
Page 42 CHAPTER 2 PIN FUNCTIONS (vi) HLDAK (Hold Acknowledge) ... output This is an acknowledge signal output pin that indicates that the V854 has set the address bus, data bus, and control bus in the high-impedance state in response to a bus hold request. As long as this signal is active, the address bus, data bus, and control bus remain in a high impedance state.
Page 43 CHAPTER 2 PIN FUNCTIONS (b) Control mode P110 to P117 function as input and output pins for timer 2 when the function is enabled by the port 11 mode control register (PMC11). TO21 to TO24 (Timer Output) ... output These are pulse signals output pins for timer 2. (ii) TI21 to TI24 (Timer Input) ...
Page 44 CHAPTER 2 PIN FUNCTIONS (14) P140 to P147 (Port 14) ... 3-state I/O Port 14 is an 8-bit I/O port that can be set in the input or output mode in 1-bit units. Port 14 functions only as a port. (15) CKSEL (Clock Select) ...
Page 45 CHAPTER 2 PIN FUNCTIONS (b) µ PD703008, 703008Y MODE2 MODE1 MODE0 Operation Mode ROM-less mode 1 Normal operation mode ROM-less mode 2 Single-chip mode 1 Single-chip mode 2 Other than above Setting prohibited (c) µ PD70F3008, 70F3008Y MODE2 MODE1 MODE0 Operation Mode ROM-less mode 1 Normal operation...
Page 46 CHAPTER 2 PIN FUNCTIONS (28) AV (Analog Reference Voltage) ... input This is a reference voltage input pin for the A/D converter. (29) V (Programming Power Supply) This pin supplies positive power for the PROM mode. This is for µ PD70F3008 or 70F3008Y. (30) NC (No Connection) This pin is not connected internally.
Page 47: Pin I/O Circuit Type And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuit Type and Connection of Unused Pins When connecting to V or V via resistor, it is recommended to use 1 to 10-kΩ resistor. I/O Circuit Type Recommended Connection P00/TO00, P01/TO01 Independently connect to V or V via resistor.
Page 48: I/O Circuits Of Pins
CHAPTER 2 PIN FUNCTIONS 2.5 I/O Circuits of Pins Type 5-K Type 1 data P-ch IN/OUT P-ch output N-ch disable N-ch input enable Type 2 Type 9 P-ch comparator – N-ch (threshold voltage) input enable Schmitt trigger input with hysteresis characteristics Type 3 Type 13-G data...
Page 49: Chapter 3 Cpu Functions
CHAPTER 3 CPU FUNCTIONS The CPU of the V854 is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline. 3.1 Features Minimum instruction cycle: 30 ns (at internal 33-MHz operation) Address space: 16 Mbytes linear General registers: Thirty-two 32-bit registers Internal 32-bit architecture Five-stage pipeline control...
Page 50: Cpu Register Set
CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The registers of the V854 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32 bits wide. For details, refer to V850 Family User’s Manual Architecture.
Page 51: Program Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general registers and a program counter. (1) General registers Thirty-two general registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 52: System Register Set
CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Table 3-2. System Register Numbers System Register Name Usage Operation EIPC Status saving registers during These registers save the PC and PSW when an exception interrupt or interrupt occurs.
Page 53 CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Status Word (PSW) After reset 00000020H Bit Position Bit Name Function 31 to 8 Reserved field (fixed to 0). NMI Pending Indicates that NMI processing is in progress. This flag is set when NMI is accepted, and disables multiple interrupts.
Page 54: Operation Modes
CHAPTER 3 CPU FUNCTIONS 3.3 Operation Modes 3.3.1 Operation modes The V854 has the following operations modes. These modes are selected by the MODE pin (n = 0 to 2). (1) Normal operation modes (a) Single-chip mode ( µ PD703008, 70F3008, 703008Y, 70F3008Y only) After the system has been released from the reset status, the pins related to the bus interface are set for port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started.
Page 55 CHAPTER 3 CPU FUNCTIONS (c) µ PD70F3008, 70F3008Y Pin Status Operation Mode MODE2 MODE1 MODE0 Normal operation ROM-less mode 1 mode ROM-less mode 2 Single-chip mode 1 Single-chip mode 2 7.8 V Flash memory programming mode Other than above Setting prohibited User’s Manual U11969EJ3V0UM00...
Page 56: Address Space
CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space The CPU of the V854 is of 32-bit architecture and supports up to 4 Gbytes of linear address space (data space) during operand addressing (data access). When referencing instruction addresses, a linear address space (program space) of up to 16 Mbytes is supported.
Page 57: Image (Virtual Address Space)
CHAPTER 3 CPU FUNCTIONS 3.4.2 Image (Virtual Address Space) The core CPU supports 4 Gbytes of “virtual” addressing space, or 256 memory blocks, each containing 16-Mbyte memory locations. In actuality, the same 16-Mbyte block is accessed regardless of the values of bits 31 to 24 of the CPU address.
Page 58: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 8 bits are set to “0”, and only the lower 24 bits are valid. Even if a carry or borrow occurs from bit 23 to bit 24 as a result of branch address calculation, the higher 8 bits ignore the carry or borrow and remain “0”.
Page 59: Memory Map
CHAPTER 3 CPU FUNCTIONS 3.4.4 Memory map The V854 reserves areas as shown below. Each mode is specified by using the MODEn pin at reset (n = 0 to Note Note Single-chip mode Single-chip mode ROM-less mode (external expansion mode) XXFFFFFFH Peripheral I/O area Peripheral I/O area...
Page 60: Area
CHAPTER 3 CPU FUNCTIONS 3.4.5 Area (1) Internal ROM area A 1-Mbyte area corresponding to addresses 000000H to 0FFFFFH is reserved for the internal ROM area. The V854 is provided with physical internal ROM as follows: Internal ROM products are µ PD703008, 70F3008, 703008Y and 70F3008Y only. Caution •...
Page 61 CHAPTER 3 CPU FUNCTIONS Interrupt/exception table The V854 increases the interrupt response speed by assigning destination addresses corresponding to interrupts/exceptions. The collection of these destination addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is granted, execution jumps to the corresponding destination address, and the program written at that memory address is executed.
Page 62 CHAPTER 3 CPU FUNCTIONS Caution The internal ROM area becomes the external memory area in ROM-less mode or in the µ PD703006. For normal operation after reset, keep the destination address for the reset routine in external memory address 0. (2) Internal RAM area The V854 is provided with 4 Kbytes of addresses FFE000H to FFEFFFH as a physical internal RAM area.
Page 63 CHAPTER 3 CPU FUNCTIONS (3) Peripheral I/O area A 4-Kbyte area of addresses FFF000H to FFFFFFH is reserved as a peripheral I/O area. The V854 is provided with a 1-Kbyte area of addresses FFF000H to FFF3FFH as a physical peripheral I/O area, and the image of FFF000H to FFF3FFH can be seen on the rest of the area (FFF400H to FFFFFFH).
Page 64 CHAPTER 3 CPU FUNCTIONS (4) External memory area The µ PD703008, 70F3008, 703008Y, and 70F3008Y can use an area of up to xx100000H to xxFFDFFFH as an external memory area in the single-chip mode. The µ PD703006, 703008, 70F3008, 703008Y, and 70F3008Y can use an area of up to xx000000H to xxFFDFFFH as an external memory area in the ROM-less mode.
Page 65 CHAPTER 3 CPU FUNCTIONS Figure 3-7. External Memory Area (when expanded to 4 Mbytes) XXFFFFFFH Peripheral I/O Internal RAM XXFFDFFFH Image Physical external memory 3FFFFFH External memory Image 000000H Image XX100000H Note Internal ROM XX000000H Note The image of the physical external memory can be seen continuously in the ROM-less mode or with the µ...
Page 66 CHAPTER 3 CPU FUNCTIONS Figure 3-8. External Memory Area (when fully expanded) XXFFFFFFH Peripheral I/O Internal RAM XXFFDFFFH External memory XX100000H Note Internal ROM XX000000H Note This area becomes an external memory area in the ROM-less mode or with the µ PD703006. User’s Manual U11969EJ3V0UM00...
Page 67: External Expansion Mode
CHAPTER 3 CPU FUNCTIONS 3.4.6 External expansion mode The V854 allows external devices to be connected to the external memory space by using the pins of ports 4, 5, 6, and 9. To connect an external device, the port pins must be set in the external expansion mode by using the MODEn pins and memory expansion mode register (MM).
Page 68 CHAPTER 3 CPU FUNCTIONS (1) Memory expansion mode register (MM) This register sets the mode of each pin of ports 4, 5, 6, and 9. In the external expansion mode, an external device can be connected to the external memory area of up to 16 Mbytes. However, the external device cannot be connected to the internal RAM area, peripheral I/O area, and internal ROM area in the single-chip mode (access is restricted to external locations 100000H through FFE00H).
Page 69: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTIONS 3.4.7 Recommended use of address space The architecture of the V854 requires that a register that serves as a pointer be secured for address generation in operand data accessing for data space. The address in this pointer register ±32 Kbytes can be accessed directly from instruction.
Page 70 CHAPTER 3 CPU FUNCTIONS Figure 3-9. Recommended Memory Map Program space Data space FFFFFFFFH Peripheral I/O FFFFF3D2H FFFFF3D1H FFFFF000H FFFFEFFFH Internal XXFFFFFFH Peripheral I/O FFFFE000H XXFFF3D2H FFFFDFFFH XXFFF3D1H External XXFFF000H memory XXFFEFFFH FF800000H FF7FFFFFH Internal XXFFE000H 01000000H XXFFDFFFH 00FFFFFFH Note Peripheral I/O External XX800000H...
Page 71: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTIONS 3.4.8 Peripheral I/O registers (1/6) Bit Units for Manipulation Address Function Register Name Symbol After Reset 1 bit 8 bits 16 bits 32bits FFFFF000H Port 0 Undefined FFFFF002H Port 1 FFFFF004H Port 2 FFFFF006H Port 3 FFFFF008H Port 4 FFFFF00AH...
Page 72 CHAPTER 3 CPU FUNCTIONS (2/6) Bit Units for Manipulation Address Function Register Name Symbol After Reset 1 bit 8 bits 16 bits 32bits FFFFF05AH Port 13 mode control register PMC13 FFFFF060H Data wait control register FFFFH FFFFF062H Bus cycle control register AAAAH FFFFF064H System control register...
Page 73 CHAPTER 3 CPU FUNCTIONS (3/6) Bit Units for Manipulation Address Function Register Name Symbol After Reset 1 bit 8 bits 16 bits 32bits FFFFF106H Interrupt control register CC0IC1 FFFFF108H Interrupt control register CC0IC2 FFFFF10AH Interrupt control register CC0IC3 FFFFF10CH Interrupt control register P1IC0 FFFFF10EH Interrupt control register...
Page 74 CHAPTER 3 CPU FUNCTIONS (4/6) Bit Units for Address Function Register Name Symbol Manipulation After Reset 1 bit 8 bits 16 bits 32bits FFFFF1B4H Event divide control register 2 EDVC2 FFFFF1B6H Event divide counter 0 EDV0 FFFFF1B8H Event divide counter 1 EDV1 FFFFF1BAH Event divide counter 2...
Page 75 CHAPTER 3 CPU FUNCTIONS (5/6) Bit Units for Manipulation Address Function Register Name Symbol After Reset 1 bit 8 bits 16 bits 32bits FFFFF2B2H Compare register 20 CM20 Undefined FFFFF2C0H Timer control register 21 TMC21 FFFFF2D0H Timer 21 TM21 0000H FFFFF2D2H Compare register 21 CM21...
Page 76 CHAPTER 3 CPU FUNCTIONS (6/6) Bit Units for Manipulation Address Function Register Name Symbol After Reset 1 bit 8 bits 16 bits 32bits FFFFF39EH A/D conversion result register 7 ADCR7 Undefined FFFFF3C0H Port 13 buffer register FFFFF3C2H Output latch FFFFF3D0H Clock output mode register CL0M User’s Manual U11969EJ3V0UM00...
Page 77: Specific Registers
CHAPTER 3 CPU FUNCTIONS 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to program runaway, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal store operations occur, this is notified by the system status register (SYS).
Page 78 CHAPTER 3 CPU FUNCTIONS 2. The instructions ((4) interrupt disable cancel, (5) NOP instruction) following the store instruction for the specific register for setting the software STOP mode and IDLE mode are executed before a power save mode is entered. (1) Command Register (PRCMD) The command register (PRCMD) is a register used when write-accessing the special register to prevent incorrect writing to the special registers due to the erroneous program execution.
Page 79 CHAPTER 3 CPU FUNCTIONS (2) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read/written in 8- or 1-bit units. Address After reset PRERR UNLOCK FFFFF078H 0000000XB Bit Position Bit Name...
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Page 81: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V854 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 4.1 Features 16-bit data bus Can be connected to external devices with pins having alternate function as port Wait function •...
Page 82: Bus Control Pins And Control Register
CHAPTER 4 BUS CONTROL FUNCTION 4.2 Bus Control Pins and Control Register 4.2.1 Bus control pins The following pins are used for interfacing to external devices: External Bus Interface Function Corresponding Port (pins) Address/data bus (AD0 to AD7) Port 4 (P40 to P47) Address/data bus (AD8 to AD15) Port 5 (P50 to P57) Address bus (A16 to A23)
Page 83: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Bus Access 4.3.1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows: Resource (bus width) Bus Cycle Type Internal ROM Internal RAM Internal Peripheral External Memory (32 bits) (32 bits) I/O (16 bits)
Page 84: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.3.2 Bus width The V854 carries out peripheral I/O access and external memory access in 8-, 16-, or 32-bit. The following shows the operation for each access. (1) Byte access (8 bits) Byte access is divided into two types, the access to even address and the access to odd address. (a) Access to even address (b) Access to odd address Byte data...
Page 85: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Memory Block Function The 16-Mbyte memory space is divided into memory blocks of 1-Mbyte units. The programmable wait function and bus cycle operation mode can be independently controlled for every two memory blocks. FFFFFFH FFFFFFH Block 15 Peripheral I/O area...
Page 86: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Wait Function 4.5.1 Programmable wait function To facilitate interfacing with low-speed memories and I/O devices, up to 3 data wait states can be inserted in a bus cycle for two memory blocks. The number of wait states can be programmed by using data wait control register (DWC).
Page 87: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, any number of wait states can be inserted in a bus cycle by sampling the external wait pin (WAIT) to synchronize with the external device. The external WAIT signal does not affect the access times of the internal ROM, internal RAM, and peripheral I/ O areas.
Page 88: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Idle State Insertion Function To facilitate interfacing with low-speed memory devices and meeting the data output float delay time (t ) on memory read accesses, one idle state (TI) can be inserted into the current bus cycle after the T3 state. The bus cycle following continuous bus cycles starts after one idle state.
Page 89: Bus Hold Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Bus Hold Function 4.7.1 Outline of function When P95 and P96 of port 9 are programmed to be in the control mode, the functions of the HLDRQ and HLDAK pins become valid. When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus, the external address/data bus and strobe pins go into a high-impedance state, and the bus is released (bus hold status).
Page 90: Bus Timing
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Timing (1) Memory read (0 wait) CLKOUT Address A16 to A23 Address Data AD0 to AD15 ASTB WRL, DSTB, UBEN, LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
Page 91 CHAPTER 4 BUS CONTROL FUNCTION (2) Memory read (1 wait) CLKOUT Address A16 to A23 Address Data AD0 to AD15 ASTB WRL, DSTB, UBEN, LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
Page 92 CHAPTER 4 BUS CONTROL FUNCTION (3) Memory read (0 wait, idle state) CLKOUT Address A16 to A23 Address Data AD0 to AD15 ASTB DSTB, WRL, UBEN, LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
Page 93 CHAPTER 4 BUS CONTROL FUNCTION (4) Memory read (1 wait, idle state) CLKOUT Address A16 to A23 Address Data AD0 to AD15 ASTB WRL, DSTB, UBEN, LBEN WAIT Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0. 2.
Page 94 CHAPTER 4 BUS CONTROL FUNCTION (5) Memory write (0 wait) CLKOUT Address A16 to A23 Note Address Data AD0 to AD15 ASTB DSTB WRL, UBEN, LBEN WAIT Note AD0 to AD7 output invalid data when odd address byte data is accessed. AD8 to AD15 output invalid data when even address byte data is accessed.
Page 95 CHAPTER 4 BUS CONTROL FUNCTION (6) Memory write (1 wait) CLKOUT Address A16 to A23 Note Address Data AD0 to AD15 ASTB DSTB WRL, UBEN, LBEN WAIT Note AD0 to AD7 output invalid data when odd address byte data is accessed. AD8 to AD15 output invalid data when even address byte data is accessed.
Page 96 CHAPTER 4 BUS CONTROL FUNCTION (7) Bus hold timing CLKOUT HLDRQ HLDAK A16 to A23 Address Undefined Address AD0 to AD15 Address Data Undefined Address ASTB DSTB, WRL, UBEN, Undefined LBEN WAIT Remarks 1. indicates the sampling timing. 2. The dotted line indicates the high-impedance state. Caution When the bus hold state is entered after the write cycle, a high-level signal may be briefly output from the R/W pin immediately before the HLDAK signal changes from the high...
Page 97: Bus Priority
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority There are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch (continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (continuous) in that order.
Page 98: Internal Peripheral I/O Interface
CHAPTER 4 BUS CONTROL FUNCTION 4.11 Internal Peripheral I/O Interface Access to the internal peripheral I/O area is not output to the external bus. Therefore, the internal peripheral I/O area can be accessed in parallel with instruction fetch access. Accesses to the internal peripheral I/O area takes, in most cases, three clock cycles. However, when accessing to certain timer/counter registers, wait may take place from 3 to 4 cycles.
Page 99: Chapter 5 Interrupt/Exception Processing Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V854 is provided with a dedicated interrupt controller (INTC) for interrupt processing and can process a total of 32 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event that occurs dependently on program execution.
Page 100 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt List (1/2) Interrupt/Exception Source Default Exception Vector Restored Type Classification Control Generating Name Generating Source Priority Code Address Register Unit Reset Interrupt RESET – Reset input – – 0000H 00000000H Undefined Non-maskable Interrupt –...
Page 101 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 5-1. Interrupt List (2/2) Interrupt/Exception Source Default Exception Vector Restored Type Classification Control Generating Name Generating Source Priority Code Address Register Unit Maskable Interrupt INTP30/ CC3IC0 INTP30/CC3 Pin/RPU 0190H 00000190H nextPC INTCC3 coincidence Interrupt INTCSI0 CSIC0 CSI0 transmission/...
Page 102: Non-Maskable Interrupt
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2 Non-Maskable Interrupt The non-maskable interrupt is accepted unconditionally, even when interrupts are disabled (DI states) in the interrupt disabled (DI) status. The NMI is not subject to priority control and takes precedence over all the other interrupts.
Page 103: Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.1 Operation If the non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher half-word (FECC) of ECR.
Page 104 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-2. Accepting Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service routine is executing: Main routine (PSW. NP = 1) NMI request → NMI request → NMI request pending because PSW. NP = 1 Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service routine is executing: Main routine...
Page 105: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.2 Restore Execution is restored from the non-maskable interrupt processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from FEPC and FEPSW, respectively, because the EP bit of PSW is 0 and the NP bit of PSW is 1.
Page 106: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when all the interrupts and requests have been accepted, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 107: Maskable Interrupts
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V854 has 31 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are accepted according to the default priority.
Page 108 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION User’s Manual U11969EJ3V0UM00...
Page 109: Operation
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.1 Operation If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler routine: (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower half-word of ECR (EICC). (4) Sets the ID bit of PSW and clears the EP bit.
Page 110 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-5. Maskable Interrupt Processing INT input INTC accepted XXIF = 1 Interrupt request? XXMK = 0 Interrupt unmasked? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with same priority?
Page 111: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.2 Restore To restore execution from the maskable interrupt processing, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of PC and PSW from EIPC and EIPSW because the EP bit of PSW is 0 and the NP bit of PSW is 0.
Page 112: Priorities Of Maskable Interrupts
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.3 Priorities of maskable interrupts The V854 provides multiple interrupt service that accepts an interrupt while servicing another interrupt. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bits (xxPRn0 to xxPRn2) of the interrupt control register (xxICn).
Page 113 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Interrupt Nesting Process (1/2) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is accepted because the priority of (level 3) (level 2) b is higher than that of a and interrupts are enabled.
Page 114 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-7. Example of Interrupt Nesting Process (2/2) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is kept pending because its Interrupt request k priority is lower than that of i.
Page 115 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 5-8. Example of Processing Interrupt Requests Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are accepted Processing of interrupt request b • Interrupt request c (level 1) first according to their priorities.
Page 116: Interrupt Control Register (Xxicn)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control register can be read/written in 8- or 1-bit units. Address After reset xxICn...
Page 117 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Address and bit of each interrupt control register is as follows: Address Register FFFFF100H OVIC0 OVIF0 OVMK0 OVPR02 OVPR01 OVPR00 FFFFF102H OVIC1 OVIF1 OVMK1 OVPR12 OVPR11 OVPR10 FFFFF104H CC0IC0 CC0IF0 CC0MK0 CC0PR02 CC0PR01 CC0PR00 FFFFF106H CC0IC1 CC0IF1 CC0MK1...
Page 118: In-Service Priority Register (Ispr)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.5 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently accepted. When an interrupt request is accepted, the bit of this register corresponding to the priority level of that interrupt is set to 1 and remains set while the interrupt is serviced.
Page 119: Noise Elimination
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.7 Noise elimination INTP, TI, TCLR, and ADTRG pins are attached with respective digital noise elimination circuit. Thereby, the input levels of these pins are sampled at each sampling clock (f ). As a result, if the same level cannot be detected three times consecutively, the input pulse is eliminated as a noise.
Page 120: Edge Detection Function
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Cautions 1. In the case that the input pulse width is two to three sampling clocks, it is indefinite whether the input pulse is detected as a valid edge or eliminated as a noise. 2. To securely detect the level as a pulse, input the same level at least three sampling clocks. 3.
Page 121 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt mode registers 1 to 6 (INTM1 to INTM6) These registers specify the valid edges of external interrupt requests or each type of trigger that are input from external pins. The valid edge of each pin can be specified to be the rising, falling, and both rising and falling edges. Both the registers can be read/written in 8- or 1-bit units.
Page 122 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Edge detection of INTP30 pin To set the valid edge of INTP30 pin, write values to INTM7 register. The valid edge can be selected from the followings. • Rising edge • Falling edge • Both rising and falling edges The edge detected INTP30 signal becomes the capture trigger of CC3 register and CP3 register of timer function.
Page 123 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (a) External interrupt mode register 7 (INTM7) This register specifies the sampling clock (f ) and the valid edge of digital noise elimination by INTP30 pins. This register can be read/written in 8- or 1-bit units. Address After reset INTM7...
Page 124: Frequency Divider
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.3.9 Frequency divider The V854 can internally divide the frequency of the signals input to P11 to P13 (INTP11 to INTP13) pins. The divided result becomes external interrupt request signal or timer capture trigger. Frequency division ratio is set to event divide control register (EDVC) and comparing it with the value in event divide counter (EDV), and if they coincide, the value becomes the internal event signal, so that the frequency of the INTP signal is divided.
Page 125 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION Address After reset EDV05 EDV04 EDV03 EDV02 EDV01 EDV00 EDV0 FFFFF1B6H EDV1 EDV15 EDV14 EDV13 EDV12 EDV11 EDV10 FFFFF1B8H FFFFF1BAH EDV2 EDV26 EDV25 EDV24 EDV23 EDV22 EDV21 EDV20 (2) Event divide control register 0 to 2 (EDVC0 to EDVC2) These registers set the frequency division ratio of the valid edge of INTPn input signal (n = 11 to 13).
Page 126: Software Exception
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always accepted. 5.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 127: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.2 Restore To restore or return execution from the software exception service routine, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC.
Page 128: Exception Status Flag (Ep)
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.4.3 Exception status flag (EP) The EP flag in PSW is a status flag used to indicate that trap processing is in progress. It is set when a trap occurs. After reset 00000020H Bit Position Bit Name Function Exception Pending...
Page 129: Exception Trap
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5 Exception Trap The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V854, an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap. An illegal op code exception occurs if the subop code field of an instruction to be executed next is not a valid op code.
Page 130: Restore
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.5.3 Restore To restore or return execution from the exception TRAP, the RETI instruction is used. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1.
Page 131: Multiple Interrupt Processing
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.6 Multiple interrupt processing Multiple interrupt processing is a function that allows the nesting of interrupts. If a higher priority interrupt is generated and accepted, it will be allowed to stop a current interrupt service routine in progress. Execution of the original routine will resume once the higher priority interrupt routine is completed.
Page 132 CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) To accept maskable interrupts in service routine Service routine of maskable interrupt or exception • Saves EIPC to memory or register • Saves EIPSW to memory or register • EI instruction (enables interrupt acceptance) ←...
Page 133: Interrupt Response Time
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION 5.7 Interrupt Response Time Interrupt Response Time from the interrupt request generation to the interrupt processing activation is as follows: Figure 5-14. Pipeline Operation at Interrupt Request Acknowledge (General Description) 7 to 14 system clocks 4 system clocks Internal system clock (CLKOUt output)
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Page 135: Chapter 6 Clock Generator Function
CHAPTER 6 CLOCK GENERATOR FUNCTION The clock generator (CG) produces and controls the internal system clock ( φ ) which is supplied to all the internal hardware units including the CPU. 6.1 Features Multiplication function by PLL (Phase Locked Loop) synthesizer Clock source = φ...
Page 136: Selecting Input Clock
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.3 Selecting Input Clock The clock generator consists of an oscillator and a PLL synthesizer. It generates, for example, a 32.768 (Max. 33)- MHz internal system clock ( φ ) when a 6.5536-MHz crystal resonator or ceramic resonator is connected across the X1 and X2 pins at 5-x multiplication.
Page 137: Clock Control Register (Ckc)
CHAPTER 6 CLOCK GENERATOR FUNCTION Examples of the clock used in the PLL mode Internal System Clock Frequency ( φ ) [MHz] Multiplication External Oscillator/External Clock Frequency (f ) [MHz] Note 1-x multiplication 33.000 33.000 Note 25.000 25.000 20.000 20.000 Note 16.000 16.000...
Page 138 CHAPTER 6 CLOCK GENERATOR FUNCTION The sequence of setting data in this register is the same as the power save control register (PSC). However, the limitation items listed in Cautions 2 for the 3.4.9 Specific registers do not apply. For details, refer to 6.5.2 Control register.
Page 139: Pll Lock-Up
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.4 PLL Lock-up Following the power-on reset or when existing the software STOP mode is released, a certain length of time will be required for the PLL to stabilize. This required time is called PLL lock-up time. The status in which the frequency is not stable is called unlock status and the status in which it has been stabilized is called lock status.
Page 140: Power Save Control
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5 Power Save Control 6.5.1 General The V854 is provided with the following power save or standby modes to reduce power consumption when CPU operation is not required. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues operation but the operating clock of the CPU stops.
Page 141 CHAPTER 6 CLOCK GENERATOR FUNCTION The operations of the clock generator in the normal, HALT, IDLE, and software STOP modes are shown in Table 6-1. By combining and selecting the mode best suited for a specific application, the power consumption of the system can be effectively reduced.
Page 142: Control Registers
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.2 Control registers (1) Power save control register (PSC) This is an 8-bit register that controls the power save mode. This is a specific register, and only the access by the specific sequence is valid during write cycles. For details, refer to 3.4.9 Specific registers. This register can be read/written in 8- or 1-bit units.
Page 143: Halt Mode
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.3 HALT mode (1) Entering and operation status In the HALT mode, the clock generator (oscillator circuit and PLL synthesizer) operates, while the operating clock of the CPU stops. The internal peripherals continue to function in reference to the internal system clock. The total lower consumption of the system can be reduced by entering the HALT mode during the idle time of the CPU.
Page 144 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing HALT mode The HALT mode can be released by the non-maskable interrupt request, an unmasked maskable interrupt request, or a RESET signal input. (a) Releasing by interrupt request The HALT mode is unconditionally released by the NMI request or an unmasked maskable interrupt request, regardless of the priority.
Page 145: Idle Mode
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.4 IDLE mode (1) Entering and operation status In this mode, both the CPU clock and the internal system clock are stopped to further reduce power consumption. However, since the clock generator continues to run, normal operation can resume without having to wait for the oscillator and PLL circuit to stabilize.
Page 146 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing IDLE mode The IDLE mode is released by the NMI signal input or RESET signal input. (a) Releasing by NMI signal input The NMI request is accepted and serviced as soon as the IDLE mode has been released. If the IDLE mode is entered in the NMI processing routine, however, only the IDLE mode is released, and the interrupt will not be accepted.
Page 147: Software Stop Mode
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.5.5 Software STOP mode (1) Entering and operation status In this mode, the CPU clock, the internal system clock, and the clock generator are stopped, reducing power consumption to only leakage current. In this state, power consumption is minimized. The software STOP mode is entered by programming the PSC register (Specific register) using the store (ST/ SST) or bit manipulation (SET1/CLR1/NOT1) instruction (refer to 3.4.9 Specific register).
Page 148 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Releasing software STOP mode The STOP mode is released by the NMI signal input or RESET signal input. It is necessary to ensure the oscillation stabilization time when releasing from the STOP mode in the PLL mode (CKSEL bit = “0”) and oscillator connection mode (CESEL bit = “0”).
Page 149: Specifying Oscillation Stabilization Time
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.6 Specifying Oscillation Stabilization Time The time required for the oscillator circuit to become stabilized after the STOP mode has been released can be specified in the following two ways: (1) Securing time using internal time base counter (NMI pin input) When the valid edge is input to the NMI pin, the STOP mode is released.
Page 150 CHAPTER 6 CLOCK GENERATOR FUNCTION (2) Securing time by signal level width (RESET pin input) The STOP mode is released when the falling edge is input to the RESET pin. The time required for the clock output from the oscillator circuit to become stabilized is specified by the low- level width of the signal input to the RESET pin.
Page 151 CHAPTER 6 CLOCK GENERATOR FUNCTION Table 6-5. Example of Count Time TBCS Frequency Division Count Time = 5.0 MHz = 6.6 MHz = 25.0 MHz = 33.0 MHz 13.1 ms 9.8 ms 2.6 ms 2.0 ms 26.2 ms 19.6 ms 5.2 ms 4.0 ms Figure 6-1.
Page 152: Clock Output Control
CHAPTER 6 CLOCK GENERATOR FUNCTION 6.7 Clock Output Control The V854 can output CLKOUT signal which has the same frequency as that of the system clock and CLO signal which is the frequency division of the system clock. • CLKOUT signal = φ (system clock) •...
Page 153: Clo Signal Output Control
CHAPTER 6 CLOCK GENERATOR FUNCTION The PSC register reset value is 00H in ROMless mode 1 and 2 and single-chip mode 2 and C0H in single-chip mode 1 and PROM mode. Therefore, the CLKOUT signal is output during the reset period in ROMless mode 1 and 2 and single-chip mode 2.
Page 154 CHAPTER 6 CLOCK GENERATOR FUNCTION (1) Clock output mode register (CLOM) This register controls clock output function. This register can be read/written in 8- or 1-bit units. Address After reset CLOM FFFFF3D0H Bit Position Bit Name Function Level Selects output level of CLO signal 0 : Low-level output 1 : High-level output Clock Enable...
Page 155 CHAPTER 6 CLOCK GENERATOR FUNCTION (3) Operations in standby mode (a) HALT mode The status before setting HALT mode is maintained. Clock continues to be output while clock is being output. When clock output is disabled, the signal of the same level that of the LV bit before HALT mode is set is output.
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Page 157: Chapter 7 Timer/Counter Function (Real-Time Pulse Unit)
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.1 Features Timer 0: 24-bit timer/event counter (1 channel) • Capture/compare registers: 4 • Can be used as a trigger of A/D converter (CC03 coincidence) • Set/reset outputs: 2 • Clearing and starting timer •...
Page 158: Basic Configuration
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2 Basic Configuration Table 7-1. List of Real-Time Pulse Unit (RPU) Configuration Timer Count Clock Register Read/ Clear Condition Generated Capture Trigger Compare Width Write Interrupt Match (R/W) Signal Trigger φ /2, φ /4, φ /8, Timer 0 •...
Page 159: Timer 0
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (1) Timer 0 (24-bit timer/event counter) Clear and Noise Edge count control TCLR0/INTP04 elimination detection INTOV0/ Noise Edge TI0/INTP05 INTP04/ elimination detection φ INTP05 φ TM0 (24) φ OVF0 /256 Noise Edge INTP00 CC00 (24) elimination detection...
Page 160: Timer 2
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer 2 (16-bit interval timer counter) INTCM2n/INTP2n Clear & start control Noise Edge TI2n/INTP2n elimination detection φ φ TM2n (16) OVF2n φ /256 CM2n (16) TO2n Remark n : 0 to 4 φ...
Page 161 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.1 Timer 0 (1) Timers 0, 0L (TM0, TM0L) TM0 functions as a 24-bit interval timer, free-running timer or event counter for external signals. It is used to measure cycles and frequency, and also for pulse generation. Only 32-bit read access is enabled for TM0 (however, the high-order 8 bits are fixed to 0), and only 16-bit read access is enabled for TM0L.
Page 162 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.2 Timer 1 (1) Timers 1, 1L (TM1, TM1L) TM1 functions as a 24-bit free-running timer or event counter. Timers 1 to 14 are used to measure cycles and frequency, and also for programmable pulse generation. TM1 is specified in 32-bit access, and TM1L is specified in lower 16-bit acccess.
Page 163 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Compare registers 10, 11 (CM10, CM11, CM10L, CM11L) The compare registers are 24-bit registers connected to TM1. These registers can be read or written in 32- bit units. CM1n is specified in 32-bit access to this register. CM1nL is specified in lower 16-bit access. CM1n can be read or written in 32-bit units.
Page 164 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.3 Timer 2 (1) Timers 20 to 24 (TM20 to TM24) TM2n is a 16-bit timer and is mainly used as an interval timer for software. TM2n can be only read in 16-bit units. Addresses After reset TM2n...
Page 165: Timer 3
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.2.4 Timer 3 (1) Timer 3 (TM3) TM3 is a 16-bit timer and is mainly used as an interval timer for software. This timer can be only read in 16-bit units. Address After reset FFFFF350H 0000H TM3 is started or stopped by the CE3 bit of timer control register 3 (TMC3).
Page 166: Control Register
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.3 Control Register (1) Timer control register 00 (TMC00) TMC00 specifies control of count enable/disable and the count clock of TM0. This register can be read/written in 8- or 1-bit units. Address After reset TMC00 OST0 PRM03...
Page 167 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Timer control register 01 (TMC01) TMC01 selects the function of the capture/compare register and sets enable/disable of the timer clear function. The contents of the register and the timer count operation are not affected even if the contents of TMC01 is rewritten during timer 0 operation.
Page 168 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) Timer control register 02 (TMC02) TMC02 selects the function of the capture/compare register and sets enable/disable of the timer clear function. This register can be read/written in 8- or 1-bit units. Address After reset TMC02 IMS05...
Page 169 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Timer control register 1 (TMC1) TMC1 specifies count enable/disable and controls the count clock of TM1. This register can be read/written in 8- or 1-bit units. Address After reset TMC1 OST1 IMS1 PRM13 PRM12 PRM11...
Page 170 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (5) Timer control register 20 to 24 (TMC20 to TMC24) TMC2n specifies count enable/disable and controls the count clock of TM2n. This register can be read/written in 8- or 1-bit units. Address After reset TMC20 CE20 IMS20...
Page 171 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (6) Timer control register 3 (TMC3) TMC3 specifies count enable/disable and controls the count clock of TM3. This register can be read/written in 8- or 1-bit units. Address After reset TMC3 CMS3 PRM33 PRM32 PRM31 PRM30...
Page 172 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (7) Timer output control registers 0 and 1 (TOC0, TOC1) TOC0, TOC1 control the timer outputs from the TO00, TO01, and TO20 to TO24 pins. These registers can be read/written in 8- or 1-bit units. Address After reset TOC0...
Page 173 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (8) Timer overflow status register (TOVS) The overflow flags TM0 to TM3 are assigned. This register can be read/written in 8- or 1-bit units. By testing and resetting the TOVS register via software, occurrence of an overflow can be polled. Address After reset TOVS...
Page 174: Timer 0 Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4 Timer 0 Operation 7.4.1 Count operation Timer 0 functions as a 24-bit interval timer or event counter, as specified by timer control registers 00 to 02 (TMC00 to TMC02). Timer 0 performs counting up by count clock. Start/stop of counting is controlled by the CE0 bit of timer control register 00 (TMC00).
Page 175: Count Clock Selection
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.2 Count clock selection An internal or external count clock frequency can be input to timer 0. Which count clock frequency is used is selected by the PRM00 to PRM03 bits of the TMC00 register. Caution Do not change the count clock frequency while the timer operates.
Page 176: Overflow
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.3 Overflow If the TM0 register overflows as a result of counting the count clock frequency to FFFFFFH, a flag is set to the OVF0 flag of the TOVS registers, and an overflow interrupt (INTOV0) is generated. The value of the OVF0 flag is retained until it is changed by user application.
Page 177: Clearing/Starting Timer
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.4 Clearing/starting timer There are three methods of clearing/starting timer 0: by overflow, by TCLR0 signal input, and by CC03 coincidence. (1) Clearing/starting by overflow For the details of the operation, refer to 7.4.3 Overflow. (2) Clearing/starting by TCLR0 signal input Timer 0 usually starts the count operation when the CE0 bit of the TMC00 register is set to 1.
Page 178 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-4. Relations between Clear/Start by TCLR0 Signal Input and Overflow (when ECLR0 = 1, OST0 = 1) Overflow FFFFFFH Count starts CE0 ← 1 TCLR0 ← 1 TCLR0 ← 1 TCLR0 ← 1 INTOV0 (3) Clearing/starting by CC03 match Timer 0 usually starts the count operation when CCLR =1, CMS03 = 1, and the CE0 bits of the TMC00 registers...
Page 179: Capture Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-6. Relations between Clear/Start by CC03 Coincidence and Overflow Operation (when CCLR0 = 1, OST0 = 1) Overflow FFFFFFH Clear & start Clear & start Count starts CCLR0 ← 1 CC03 ← n CE0 ←...
Page 180 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-7. Example of TM0 Capture Operation Capture trigger CC00 INTP00 (Capture trigger) (Capture trigger) Remark The capture operation is not performed even if the interrupt request (INTP00) is input when CE0 is cleared to 0.
Page 181: Compare Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.4.6 Compare operation When the TMC01 register is set as a compare register, the capture/compare registers (CC00 to CC03) perform a comparison between the value of the compare register with the count values of TM0. When the count values of TM0 coincide with the value of the compare register programmed in advance, a coincidence signal is sent to the output control circuit (refer to Figure 7-9).
Page 182 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Timer 0 has two timer output pins: TO00 and TO01. The count values of TM0 are compared with the values of CC02. When the two values coincide, the output level of the TO01 pin is set. The count values of TM0 are also compared with the values of CC03. When the two values coincide, the output levels of the TO01 pin are reset.
Page 183: Timer 1 Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.5 Timer 1 Operation 7.5.1 Count operation Timer 1 functions as a 24-bit free-running timer or event counter, as specified by timer control register 1 (TMC1). Timer 1 performs counting up by count clock. Start/stop of counting is controlled by the CE1 bit of timer control register 1 (TMC1).
Page 184: Overflow
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) External count clock The signal input to the TI1 pins is counted. At this time, timer 1 operates as an event counter. To set an external count clock, see the table below. PRM13 PRM12 PRM11...
Page 185: Clearing/Starting Timer
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-12. Operation after Occurrence of Overflow (OST1 = 1) Overflow Overflow FFFFFFH FFFFFFH Count starts OST ← 1 CE1 ← 1 CE1 ← 1 INTOV1 7.5.4 Clearing/starting timer There are two methods of clearing/starting timer 1: by overflow and by software. (1) Clearing/starting by overflow For the details of the operation, refer to 7.5.3 Overflow.
Page 186: Capture Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.5.5 Capture operation A capture operation that captures and holds the count values of TM1 and loads them to a capture register in asynchronization with an external trigger can be performed. The trigger divided by the valid edge from the external interrupt request input pin INTP1n is used as the capture trigger.
Page 187: Compare Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.5.6 Compare operation A comparison between the value in a compare register with the count values of TM1 can be performed. When the count values of TM1 coincide with the value of the compare register programmed in advance, INTCM10 coinciding with CM10 is generated as a trigger of the real time output port.
Page 188: Timer 2 Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.6 Timer 2 Operation 7.6.1 Count operation Timer 2 functions as a 16-bit interval timer. The operation is specified by the timer control registers 20 to 24 (TMC20 to TMC24). The operation of timer 2 counts the internal count clocks ( φ /2 to φ /256 or the external count clock (TI2n)) specified by the PRM2n0 to PRM2n3 bits of the TMC2n register.
Page 189: Overflow
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) External count clock The signal input to the TI2n pins are counted. At this time, timer 2 operates as an event counter. To set an external count clock see the table below. PRM2n3 PRM2n2 PRM2n1...
Page 190 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-17. Operation with CM2n at 1 to FFFFH Count clock Count up TM2n clear Clear TM2n CM2n Coincidence detection (INTCM2n) Remark Interval time = (N + 1) × count clock cycle N = 1 to 65535 (FFFFH) Figure 7-18.
Page 191: Toggle Output
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.6.6 Toggle output Toggle output is an operation mode to invert output levels each time the value of the compare register (CM20 to CM24) coincides with that of CM2n (n = 0 to 4). The relations between timers to be compared and compare register to timer outputs are shown below.
Page 192: Timer 3 Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.7 Timer 3 Operation 7.7.1 Count operation Timer 3 functions as a 16-bit interval timer. The operation is specified by the timer control registers 3 (TMC3). The operation of timer 3 counts the internal count clocks ( φ /2 to φ /256) specified by the PRM30 to PRM33 bits of the TMC3 register.
Page 193: Clearing/Starting Timer
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.7.4 Clearing/starting timer There are three methods of clearing/starting timer 3: by coincidence of compare register, by capture trigger of CC3, and by software. (1) Clearing/starting by compare coincidence of CC3 If CC3 is specified as a compare register by the CMS 3 bit, TM3 clears its value at the next count clock and starts count operation when the set value of the compare register (CC3) and the value of TM3 coincide.
Page 194: Compare Operation
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-21. Example of TM3 Capture Operation (when ES301 = 0, ES300 = 0, CMS3 = 0, CE3 = 1) INTP30 CC3 trigger CP3 trigger INTCC3 7.7.6 Compare operation When the TM3 register is set as a compare register, the capture/compare register (CC3) performs a comparison between the value in a compare register and the count value of TM3.
Page 195: Application Examples
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.8 Application Examples (1) Operation as interval timer (timer 0, timer 2, and timer 3) The following shows that timer 2 used as an interval timer that repeatedly generates an interrupt request at time intervals specified by the count value set in advance to compare register CM20.
Page 196 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (2) Pulse width measurement (timer 0, timer 1, and timer 3) An example of pulse width measurement is shown below. In this example, the width of the high or low level of an external pulse input to the INTP00 pin is measured. The value of timer 1 (TM0) is captured to a capture/compare register (CC00) in synchronization with the valid edge of the INTP00 pin (both the rising and falling edges) and is pended, as shown in Figure 7-24.
Page 197 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-25. Setting Procedure for Pulse Width Measurement (timer 0) Pulse width measurenent initial setting Setting of TMC00 register ; Specifies count clock Setting of INTM1 register ; Specifies both edges as valid INTM1.
Page 198 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) PWM output (timer 0) Any square wave can be output to timer output pin (TOn) by combining the use of timer 0 and the timer output function and can be used as a PWM output. Shown below is an example of PWM output using two capture/compare registers, CC00 and CC01 .
Page 199 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-28. Example of PWM Output Programming Procedure PWM output initial setting Setting of TOC1n register ; Specifies active level (high level) TOCn. ENTO0n ← 1 Enables timer ouput TOCn. ALV0n ← 1 Setting of TMC01 register ;...
Page 200 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-29. Example of Interrupt Request Processing Routine, Modifying Compare Value INTCC00 interrupt processing INTCC01 interrupt processing Sets time (number of counts) to reset TO00 Sets time (number of counts) to set TO00 output to 1 next, to compare register CC00 output to 0 next, to compare register CC01 RETI...
Page 201 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (4) Frequency measurement (timer 0, timer 1, and timer 3) Timer 0, timer 1, and timer 3 can be used to measure the cycle or frequency of an external pulse input to the INTP pin.
Page 202 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) Figure 7-31. Example of Set-up Procedure for Frequency Measurement Cycle measurement initial setting ; Specifies count clock of TM0 Setting of TMC00 register Setting of TMC01 register ; Specifies CC00 register TMC01. CMS00 ← 0 as capture register Setting of INTM1 register ;...
Page 203: Note
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.9 Note Coincidence is detected by the compare register immediately after the timer value matches the compare register value, and does not take place in the following cases: (1) When compare register is rewritten (timer 0 to timer 3) Count clock Value of timer n –...
Page 204 CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) (3) When timer is cleared (timer 0, timer 2, and timer 3) Count clock Note 1 Note 2 Value of timer FFFEH FFFFH Internal coincidence clear Compare register value 0000H Coincidence detection ↑ Coincidence does not occur Notes 1.
Page 205: Chapter 8 Serial Interface Function
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.1 Features The V854 is provided with three types of serial interfaces which operate as 6-channel transmission/reception channels. Four channels can be used simultaneously. There are the following three types of interfaces. (1) Asynchronous serial interface (UART) : 1 channel (2) Clocked serial interface (CSI) : 4 channels : 1 channel ( µ...
Page 206: Asynchronous Serial Interface (Uart)
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2 Asynchronous Serial Interface (UART) 8.2.1 Features Transfer rate: 150 bps to 153600 bps (Baud rate generator used, @ φ = 33-MHz operation) 110 bps to 614400 bps (Baud rate generator used, @ φ = 19.660-MHz operation) 110 bps to 38400 bps (Baud rate generator used, @ φ...
Page 207: Configuration Of Asynchronous Serial Interface
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.2 Configuration of asynchronous serial interface The asynchronous serial interface is controlled by the asynchronous serial interface mode register (ASIMn) and the asynchronous serial interface status register (ASIS). The receive data is stored in the receive buffer (RXB), and the transmit data is written to the transmit shift register (TXS).
Page 208 CHAPTER 8 SERIAL INTERFACE FUNCTION (8) Selector Selects the source of the serial clock. Figure 8-1. Block Diagram of Asynchronous Serial Interface Internal bus 16/8 ASIM0 ASIM1 16/8 Receive PS1 PS0 CL SL SOLS buffer RXBL ASIS Receive Transmit PE FE OVE SOT shift register shift register TXSL...
Page 209: Control Registers
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.3 Control registers (1) Asynchronous serial interface mode registers 0, 1 (ASIM0, ASIM1) These registers specify the transfer mode of the UART. They can be read/written in 8- or 1-bit units. Address After reset ASIM0 SCLS FFFFF0C0H Bit Position...
Page 210 CHAPTER 8 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function 5, 4 PS1, PS0 Parity Select Specifies parity bit. Operation No parity. Extended bit operation 0 parity Transmission side → Transmits with parity bit 0 Reception side → Does not generate parity error on reception Odd parity Even parity •...
Page 211 CHAPTER 8 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function SCLS Serial Clock Source Specifies serial clock. 0 : Specified by BRGC0 and BPRM0 1 : φ /2 • When SCLS = 1 φ /2 is selected as serial clock source. In asynchronous mode, baud rate is expressed as follows because sampling rate of x16 is used: φ...
Page 212 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register (ASIS) This register contains three error flags that indicate the receive error status for each character received and the status of the transmit shift register. The error flags always indicate the status of an error that has occurred most recently. If two or more errors occur before the current received data, only the status of the error that has occurred last is retained.
Page 213 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) Receive buffers (RXB, RXBL) RXB are 9-bit buffer registers that hold the receive data. When a 7- or 8-bit character is received, the higher bit of these registers are 0. When reading 16-bit data from the receive buffer, RXB is specified. When data is read from the lower 8bits, RXBL is specified.
Page 214 CHAPTER 8 SERIAL INTERFACE FUNCTION (4) Transmit shift registers (TXS, TXSL) TXS are 9-bit shift registers for data transmission. The transmit operation is started when data is written to these registers during transmission enable status. If data is written to the transmit shift register in the transmission disabled status, the values written are ignored. Transmission complete interrupt request (INTST) is generated after each complete data frame including TXS is transmitted.
Page 215: Interrupt Request
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.4 Interrupt request UART generates the following three types of interrupt requests: • Receive error interrupt (INTSER) • Reception completion interrupt (INTSR) • Transmission completion interrupt (INTST) Of these three, the receive error interrupt has the highest default priority, followed by the reception completion interrupt and transmission completion interrupt.
Page 216: Operation
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.2.5 Operation (1) Data format Full-duplex serial data is transmitted/received. One data frame of the transmit/receive data consists of a start bit, character bit, parity bit, and stop bit, as shown in Figure 8-2. The length of the character bit, parity, and the length of the stop bit in one data frame are specified by the asynchronous serial interface mode registers (ASIMn).
Page 217 CHAPTER 8 SERIAL INTERFACE FUNCTION (c) Transmission interrupt request When one frame of data or character has been completely transferred, a transmission completion interrupt request (INTST) occurs. Unless the data to be transmitted next is written to the TXS or TXSL registers, the transmission is aborted. The communication rate drops unless the next transmit data is written to the TXS or TXSL registers immediately after transmission has been completed.
Page 218 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) Reception When reception is enabled, sampling of the RXD pin is started, and reception of data begins when the start bit is detected. Each time one frame of data or character has been received, the reception completion interrupt (INTSR) occurs.
Page 219 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-4. Asynchronous Serial Interface Reception Completion Interrupt Timing Stop Parity/ RXD (input) extend Start INTSR interrupt (d) Reception error flag Three error flags, parity error, framing error, and overrun error flags, are related with the reception operation.
Page 220: Clocked Serial Interface 0 To 3 (Csi0 To Csi3)
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3 Clocked Serial Interface 0 to 3 (CSI0 to CSI3) 8.3.1 Features Number of channels: 4 channels (CSIn) High transfer speed CSI0, CSI2, CSI3: 8.25 Mbps max. ( φ /4 use, φ = 33 MHz) CSI1: 2.00 Mbps max.
Page 221 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-6. Block Diagram of Clocked Serial Interface CSI0 CSIM0 CTXE0 CRXE0 CSOT0 MOD0 CLS01 CLS00 SO latch Serial I/O shift register (SIO0) BRG0 Serial clock SCK0 control circuit Interrupt INTCSI0 Serial clock counter control circuit Note CSI1 Note...
Page 222: Control Registers
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.3 Control registers (1) Clocked serial interface mode register 0 to 3 (CSIM0 to CSIM3) These registers specify the basic operation mode of CSIn. They can be read/written in 8- or 1-bit units (note, however, that bit 5 can only be read). Address After reset CSIM0...
Page 223 CHAPTER 8 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function 1, 0 CLSn1, CLSn0 Clock Source Specifies serial clock. CLSn1 CLSn0 Specifies Serial Clock SCKn pin External clock Input Internal clock Specified by BPRMn register Note 1 Output φ /4 Note 2 Output φ...
Page 224: Basic Operation
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.4 Basic operation (1) Transfer format The CSI performs interfacing by using three lines: one clock line and two data lines. Serial transfer is started by executing an instruction that writes transfer data to the SIOn register. During transmission, the data is output from the SOn pin in synchronization with the falling edge of SCKn.
Page 225 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Enabling transmission/reception Each CSIn has only one 8-bit shift register and does not have a buffer. Transmission and reception are therefore performed simultaneously. (a) Transmission/reception enabling condition The transmission/reception enabling condition of CSIn is specified by the CTXEn and CRXEn bits of the CSIMn register.
Page 226: Transmission In Csi0 To Csi3
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.5 Transmission in CSI0 to CSI3 Transmission is started when data is written to the SIOn register after transmission has been enabled by the clocked serial interface mode register (CSIMn) (n = 0 to 3). (1) Starting transmission Transmission is started by writing the transmit data to the shift register (SIOn) after the CTXE bit of the clocked serial interface mode registers (CSIMn) has been set (the CRXE bit is cleared to “0”).
Page 227: Reception In Csi0 To Csi3
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.6 Reception in CSI0 to CSI3 Reception is started if the status is changed from reception disabled to reception enabled status by the clocked serial interface mode registers (CSIMn) or if the SIOn registers are read by the CPU with reception enabled (n = 0 to 3).
Page 228: Transmission/Reception In Csi0 To Csi3
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.7 Transmission/reception in CSI0 to CSI3 Transmission and reception can be executed simultaneously if both transmission and reception are enabled by the clocked serial interface mode registers (CSIMn) (n = 0 to 3). (1) Starting transmission/reception Transmission and reception can be performed simultaneously (transmission/reception operation) when both the CTXEn and CRXEn bits of the clocked serial interface mode registers (CSIMn) are set to 1.
Page 229 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-9. Timing of 3-Wire Serial I/O Mode (transmission/reception) SCKn DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSIn Serial transmission/ reception completion interrupt occurs Transfer starts in synchronization with falling edge of SCKn Execution of SIOn write instruction Remark n = 0 to 3 User’s Manual U11969EJ3V0UM00...
Page 230: System Configuration Example
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.3.8 System configuration example Data 8 bits long is transferred by using three types of signal lines: serial clock (SCKn), serial input (SIn), and serial output (SOn). This feature is effective for connecting peripheral I/Os and display controllers that have a conventional clocked serial interface.
Page 231: I 2 C Bus ( Μ Pd703008Y And 70F3008Y Only)
CHAPTER 8 SERIAL INTERFACE FUNCTION C Bus ( µ PD703008Y and 70F3008Y only) 8.4 I 8.4.1 Features C bus format Multi-master serial bus Serial data automatic discrimination function Transfer speed: standard mode : 100 Kbps max. high-speed mode : 400 Kbps max. Chip select by address Wake-up function Acknowledge signal (ACK) control function...
Page 232: Functions
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.2 Functions The following two modes are available for I C bus. • Operation stop mode • I C (Inter IC) bus mode (supports multi-master) (1) Operation stop mode Used when serial transfer is not carried out, reduces power consumption. (2) I C bus mode (supports multi-master) Performs 8-bit data transfer with more than one device, using two lines, each for the serial clock (SCL) and...
Page 233 Figure 8-12. Block Diagram of I C Bus Internal bus IIC control register (IICC) IIC status register (IICS) IICE LREL WREL SPIE WTIM ACKE STT SPT MSTS ALD EXC COI TRC ACKD STD SPD Slave address register (SVA) CLEAR Coincidence signal SO latch CL0 CL1 IIC shift register (IIC)
Page 234: Configuration
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.3 Configuration The I C bus is configured with the following hardware. Table 8-2. I C Bus Configuration Item Configuration Register IIC shift register (IIC) Slave address register (SVA) Control register IIC clock selection register (IICCL) IIC status register (IICS) IIC control register (IICC) (1) IIC shift register (IIC)
Page 235 CHAPTER 8 SERIAL INTERFACE FUNCTION (8) Serial clock control circuit Generates clocks to be output to SCL pin from the sampling clock in the master mode. (9) Serial clock wait control circuit Controls wait timings. (10) Acknowledge output circuit, stop condition detection circuit, start condition detection circuit, acknowledge detection circuit Performs output and detection of various control signals.
Page 236: Serial Interface Control Register
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.4 Serial interface control register C bus is controlled by the following three registers. • IIC control register (IICC) • IIC status register (IICS) • IIC clock selection register (IICCL) The following registers are also used. •...
Page 237 CHAPTER 8 SERIAL INTERFACE FUNCTION (1) IIC control register (IICC) This register performs enabling/disabling I C operation, setting of wait timing, and other settings of I operation. This register is set by 1- or 8-bit memory manipulation instruction. It becomes 00H by RESET input. Address After reset IICC...
Page 238 CHAPTER 8 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function WTIM Wait Timing Controls generation of wait and interrupt request. 0 : Interrupt request generates at the fall of the eighth clock For master : Waits keeping clock output in low level after outputting eight clocks For slave : Waits for master setting clock output in low level after inputting eight clocks 1 : Interrupt request generates at the fall of the ninth clock...
Page 239 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) IIC status register (IICS) IIC status register indicates the I C status. This register is set by 1- or 8-bit memory manipulation instruction. It can only be read. It becomes 00H by RESET input. Address After reset IICS...
Page 240 CHAPTER 8 SERIAL INTERFACE FUNCTION Bit Position Bit Name Function Transmit/Receive Condition Indicates current communication status. 0 : Receiving status (status other than transmitting status). SDA line goes into high-impedance state. 1 : Transmitting status. The value of SO latch can be output to SDA line (valid after the fall of the ninth clock of the first byte).
Page 241 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) IIC clock selection register (IICCL) IICCL is a register that sets the transfer clock of I This register is set by 1- or 8-bit memory manipulation instruction. It becomes 00H by RESET input. Address After reset Note Note...
Page 242: I 2 C Bus Functions
CHAPTER 8 SERIAL INTERFACE FUNCTION Caution In operations during restart, carry out writing of address data to the IIC shift register after the start conditions trigger is cleared and the start conditions are detected. Address After reset IIC07 IIC06 IIC05 IIC04 IIC03 IIC02...
Page 243: Definition And Controls Of I 2 C Bus
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.6 Definition and controls of I C bus The serial data communication format of I C bus and the signals used are explained below. Figure 8-14 shows each transfer timing of “start condition”, “data”, and “stop condition”, which are output onto the serial data bus of I C bus.
Page 244 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Address The 7-bit data following the start condition is defined as an address. The address is an 7-bit data which the master outputs to select a specific slave from the two or more slaves connected to the bus line.
Page 245 CHAPTER 8 SERIAL INTERFACE FUNCTION (3) Transfer direction specification The master transmits 1-bit data because it specifies the transmit direction following the 7-bit address. When the transmit direction specification bit is 0, the master transmits data to the slave. When the transmit direction specification bit is 1, the master receives data from the slave. Figure 8-17.
Page 246 CHAPTER 8 SERIAL INTERFACE FUNCTION (4) Acknowledge signal (ACK) The acknowledge signal is a signal for checking serial data reception in the transmit and receive sides. The receive side sends back the acknowledge signal each time it receives an 8-bit data. The transmit side receives the acknowledge signal after transmitting the 8-bit data.
Page 247 CHAPTER 8 SERIAL INTERFACE FUNCTION (5) Stop condition The stop condition is generated when the SDA pin changes from low level to high level while the SCL pin is high level. The stop condition is a signal which the master outputs to the slave when a serial transfer has ended. The slave is provided with the hardware to detect the stop condition.
Page 248 CHAPTER 8 SERIAL INTERFACE FUNCTION (6) Wait signal (WAIT) The wait signal is a signal by which the master or the slave informs the other that it is preparing for transmitting/ receiving data (wait status). The master of the slave informs the wait status to the other by inputting the low level to the SCL pin. Both the master and slave can start the next transfer when the wait status is released.
Page 249 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-20. Wait Signal (2/2) (2) When both master and slave are 9-clock wait (master: transmission, slave: reception, ACKE = 1) Master Both master and slave wait after outputting the ninth clock IIC ← data (wait released) Slave IIC ←...
Page 250 CHAPTER 8 SERIAL INTERFACE FUNCTION (7) I C interrupt (INTIIC) The following shows the INTIIC interrupt request generation timing and the value of the IIC status register (IICS) in INTIIC interrupt timing. (a) Master operation Start-Address-Data-Data-Stop (normal transmission/reception) <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0...
Page 251 CHAPTER 8 SERIAL INTERFACE FUNCTION (ii) Start-Address-Data-Start-Address-Data-Stop (restart) <1> When WTIM = 0 AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 1 0 x x x 1 1 0 B 2: IICS = 1 0 x x x 0 0 0 B 3: IICS = 1 0 x x x 1 1 0 B 4: IICS = 1 0 x x x 0 0 0 B 5: IICS = 0 0 0 0 0 0 0 1 B...
Page 252 CHAPTER 8 SERIAL INTERFACE FUNCTION (iii) Start-Code-Data-Data-Stop (extension code transmission) <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 1 0 1 0 x 1 1 0 B 2: IICS = 1 0 1 0 x 0 0 0 B 3: IICS = 1 0 1 0 x 0 0 0 B 4: IICS = 0 0 0 0 0 0 0 1 B Remark...
Page 253 CHAPTER 8 SERIAL INTERFACE FUNCTION (b) Slave operation (when receiving slave address data (SVA coincides)) Start-Address-Data-Data-Stop <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 0 0 1 x 1 1 0 B 2: IICS = 0 0 0 1 x 0 0 0 B 3: IICS = 0 0 0 1 x 0 0 0 B 4: IICS = 0 0 0 0 0 0 0 1 B...
Page 254 CHAPTER 8 SERIAL INTERFACE FUNCTION (ii) Start-Address-Data-Start-Address-Data-Stop <1> When WTIM = 0 (SVA coincides after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 0 1 x 1 1 0 B 2: IICS = 0 0 0 1 x 0 0 0 B 3: IICS = 0 0 0 1 x 1 1 0 B 4: IICS = 0 0 0 1 x 0 0 0 B...
Page 255 CHAPTER 8 SERIAL INTERFACE FUNCTION (iii) Start-Address-Data-Start-Code-Data-Stop <1> When WTIM = 0 (receives extension code after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 0 1 x 1 1 0 B 2: IICS = 0 0 0 1 x 0 0 0 B 3: IICS = 0 0 1 0 x 0 1 0 B 4: IICS = 0 0 1 0 x 0 0 0 B...
Page 256 CHAPTER 8 SERIAL INTERFACE FUNCTION (iv) Start-Address-Data-Start-Address-Data-Stop <1> When WTIM = 0 (address does not coincide after restart (except extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 0 1 x 1 1 0 B 2: IICS = 0 0 0 1 x 0 0 0 B 3: IICS = 0 0 0 0 x x 1 0 B 4: IICS = 0 0 0 0 0 0 0 1 B...
Page 257 CHAPTER 8 SERIAL INTERFACE FUNCTION (c) Slave operation (when receiving extension code) Start-Code-Data-Data-Stop <1> When WTIM = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 0 1 0 x 0 1 0 B 2: IICS = 0 0 1 0 x 0 0 0 B 3: IICS = 0 0 1 0 x 0 0 0 B 4: IICS = 0 0 0 0 0 0 0 1 B Remark...
Page 258 CHAPTER 8 SERIAL INTERFACE FUNCTION (ii) Start-Code-Data-Start-Address-Data-Stop <1> When WTIM = 0 (SVA coincides after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 1 0 x 0 1 0 B 2: IICS = 0 0 1 0 x 0 0 0 B 3: IICS = 0 0 0 1 x 1 1 0 B 4: IICS = 0 0 0 1 x 0 0 0 B...
Page 259 CHAPTER 8 SERIAL INTERFACE FUNCTION (iii) Start-Code-Data-Start-Code-Data-Stop <1> When WTIM = 0 (receives extension code after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 1 0 x 0 1 0 B 2: IICS = 0 0 1 0 x 0 0 0 B 3: IICS = 0 0 1 0 x 0 1 0 B 4: IICS = 0 0 1 0 x 0 0 0 B...
Page 260 CHAPTER 8 SERIAL INTERFACE FUNCTION (iv) Start-Code-Data-Start-Address-Data-Stop <1> When WTIM = 0 (address does not coincides after restart (except extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS = 0 0 1 0 x 0 1 0 B 2: IICS = 0 0 1 0 x 0 0 0 B 3: IICS = 0 0 0 0 0 x 1 0 B 4: IICS = 0 0 0 0 0 0 0 1 B...
Page 261 CHAPTER 8 SERIAL INTERFACE FUNCTION (d) Operation of not joining communication Start-Code-Data-Data-Stop AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 0 0 0 0 0 0 1 B Remark generates only when SPIE = 1 (e) Operation of arbitration defeat (operates as a slave after arbitration defeat) When defeated in arbitration during slave address data transmission <1>...
Page 262 CHAPTER 8 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 1 0 1 x 1 1 0 B (example: reads ALD during interrupt processing) 2: IICS = 0 0 0 1 x 1 0 0 B 3: IICS = 0 0 0 1 x x 0 0 B 4: IICS = 0 0 0 0 0 0 0 1 B Remark...
Page 263 CHAPTER 8 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 1 1 0 x 0 1 0 B (example: reads ALD during interrupt processing) 2: IICS = 0 0 1 0 x 1 1 0 B 3: IICS = 0 0 1 0 x 1 0 0 B 4: IICS = 0 0 1 0 x x 0 0 B 5: IICS = 0 0 0 0 0 0 0 1 B...
Page 264 CHAPTER 8 SERIAL INTERFACE FUNCTION (ii) When defeated in arbitration during transmitting extension code AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 0 1 1 0 x 0 1 0 B (example: reads ALD during interrupt processing) Set LREL =1 by software (when not joining communication) 2: IICS = 0 0 0 0 0 0 0 1 B Remark...
Page 265 CHAPTER 8 SERIAL INTERFACE FUNCTION <2> When WTIM = 1 AD6 to AD0 D7 to D0 D7 to D0 1: IICS = 1 0 0 0 1 1 1 0 B 2: IICS = 0 1 0 0 0 1 0 0 B (example: reads ALD during interrupt processing) 3: IICS = 0 0 0 0 0 0 0 1 B Remark always generates...
Page 266 CHAPTER 8 SERIAL INTERFACE FUNCTION <2> Extension code AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 1: IICS = 1 0 0 0 x 1 1 0 B 2: IICS = 0 1 1 0 x 0 1 0 B (example: reads ALD during interrupt processing) Set IICC : LREL = 1 by software (when not joining communication) 3: IICS = 0 0 0 0 0 0 0 1 B Remark...
Page 267 CHAPTER 8 SERIAL INTERFACE FUNCTION (vi) When attempting to generate restart condition and defeated in arbitration because the data is low level <1> When WTIM = 0 STT = 1 AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 1: IICS = 1 0 0 0 x 1 1 0 B 2: IICS = 1 0 0 0 x 0 0 0 B 3: IICS = 0 1 0 0 0 0 0 0 B (example: reads ALD during interrupt processing)
Page 268 CHAPTER 8 SERIAL INTERFACE FUNCTION (vii) When attempting to generate restart condition and defeated in arbitration at stop condition because the data is low level <1> When WTIM = 0 STT = 1 AD6 to AD0 D7 to D0 1: IICS = 1 0 0 0 x 1 1 0 B 2: IICS = 1 0 0 0 x 0 0 0 B 3: IICS = 0 1 0 0 0 0 0 1 B Remark...
Page 269 CHAPTER 8 SERIAL INTERFACE FUNCTION (viii) When attempting to generate stop condition and defeated in arbitration because the data is low level <1> When WTIM = 0 SPT = 1 AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 1: IICS = 1 0 0 0 x 1 1 0 B 2: IICS = 1 0 0 0 x 0 0 0 B 3: IICS = 0 1 0 0 0 0 0 0 B (example: reads ALD during interrupt processing)
Page 270 CHAPTER 8 SERIAL INTERFACE FUNCTION (8) Interrupt request (INTIIC) generation timing and wait control INTIIC generates and wait control is performed by the settings of the WTIM bit of the IIC control register (IICC) at the timings shown in Table 8-3. Table 8-3.
Page 271 CHAPTER 8 SERIAL INTERFACE FUNCTION (9) Address coincidence detection The I C bus can select the specific slave device when the master transmits the slave address. Address coincidence detection can be automatically performed by hardware. If the local address is set to the slave address register (SVA), INTIIC interrupt request generates only when the slave address transmitted from the master and the address set in SVA coincide or when an extension code is received.
Page 272 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-21. Example of Arbitration Timing Master 1 Hi-Z Hi-Z Master 1 arbitration defeat Master 2 Transfer line Status when Arbitration Occurs Interrupt Request Issue Timing Note 1 Address transmitting Fall of the eighth or ninth clock after byte transfer Read/write information after address transmission Transferring extension code Read/write information after extension code transmission...
Page 273 CHAPTER 8 SERIAL INTERFACE FUNCTION (13) Wake-up function Wake-up function generates interrupt request (INTIIC) when the local address and an extension code are received in the slave function of I When address does not coincide, unnecessary interrupt does not generate, so that efficient processing is possible.
Page 274 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-22. Communication Reservation Timing Program IIC write processing Commu- Hardware Setting SPD Setting nication reserva- processing and INTIIC tion Output by the master which has occupied the bus The communication reservation is acknowledged at the following timings. The communication reservation is made by setting the STT of IICC = 1 before stop condition detection after STD of IICS = 1 is set.
Page 275 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-23 shows the communication reservation procedure. Figure 8-23. Communication Reservation Procedure STT ← 1 Sets STT flags (communication reservation) Definition of Defines communication is reserved communication reservation (set by defining user flag in any RAM) Wait Secures wait time by software...
Page 276 CHAPTER 8 SERIAL INTERFACE FUNCTION (b) Operation during communication reservation (when a multi-master is used) If a slave is selected during communication reservation, when writing a “1” to the WREL bit, write a “0” to the STT bit at the same time. After that, following stop condition detection, write a “1” to the STT bit again.
Page 277: Communication Operation
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.7 Communication operation (1) Master operation The following shows the master communication procedure. Figure 8-25. Master Operation Procedure START IICCL ← xxH Selects transfer clock IICC ← xxH IICE = SPIE = WTIM = 1 STT = 1 INTIIC = 1? IIC write...
Page 278 CHAPTER 8 SERIAL INTERFACE FUNCTION (2) Slave operation The following shows the slave communication procedure. Figure 8-26. Slave Operation Procedure START IICC ← xxH IICE = 1 INTIIC = 1? EXC = 1? Joining communication? LREL = 1 COI = 1? TRC = 1? WTIM = 0 WTIM = 1...
Page 279: Timing Chart
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.4.8 Timing chart In the I C bus mode, a target slave device is selected from more than one slave device when the master outputs an address to the serial bus. The master transmits the TRC bit that indicates the transfer direction of data following the slave address and starts serial communication with the slave.
Page 280 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-27. Example of Master→ Slave Communication (9-clock wait is selected both for master and slave) (1/3) (1) Start condition-address Processing of master device IIC ← Address IIC ← Data ACKD WTIM ACKE WREL INTIIC MSTS Transmission Transfer line...
Page 281 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-27. Example of Master → Slave Communication (9-clock wait is selected both for master and slave) (2/3) (2) Data Processing of master device IIC ← Data IIC ← Data ACKD WTIM ACKE WREL INTIIC MSTS Transmission Transfer line...
Page 282 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-27. Example of Master → Slave Communication (9-clock wait is selected both for master and slave) (3/3) (3) Stop condition Processing of master device IIC ← Data IIC ← Address ACKD WTIM ACKE WREL INTIIC (When SPIE = 1) MSTS...
Page 283 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-28. Example of Slave → Master Communication (9-clock wait is selected both for master and slave) (1/3) (1) Start condition-address Processing of master device IIC ← Address IIC ← FFH Note ACKD WTIM ACKE Note WREL INTIIC...
Page 284 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-28. Example of Slave → Master Communication (9-clock wait is selected both for master and slave) (2/3) (2) Data Processing of master device IIC ← FFH IIC ← FFH Note Note ACKD WTIM ACKE Note Note WREL...
Page 285 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-28. Example of Slave → Master Communication (9-clock wait is selected both for master and slave) (3/3) (3) Stop condition Processing of master device IIC ← FFH IIC ← Address Note ACKD WTIM ACKE Note WREL INTIIC...
Page 286: Baud Rate Generator 0 To 3 (Brg0 To Brg3)
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.5 Baud Rate Generator 0 to 3 (BRG0 to BRG3) 8.5.1 Configuration and function The serial clock of the serial interface can be selected from the baud rate generator output or φ (internal system clock) for each channel. A baud rate generator is provided with the following four systems, which can be set independently.
Page 287 CHAPTER 8 SERIAL INTERFACE FUNCTION Figure 8-29. Block Diagram of Baud Rate Generator BRG0 BPRM0 BRGC0 Coincidence UART Clear CSI0 TMBRG0 Prescaler CSI1 BRG1 CSI2 BRG2 CSI3 BRG3 User’s Manual U11969EJ3V0UM00...
Page 288 CHAPTER 8 SERIAL INTERFACE FUNCTION (1) Dedicated baud rate generators (BRG0 to BRG3) The dedicated baud rate generators (BRGn) consist of an 8-bit timer (TMBRGn) that generates a serial clock for transmission/reception, a compare register (BRGCn), and a prescaler (n = 0 to 3). (a) Input clock Internal system clock ( φ...
Page 289 CHAPTER 8 SERIAL INTERFACE FUNCTION Table 8-6. Baud Rate Generators 0 to 3 Set-up Values (when typical clocks are used) (1/2) (a) UART φ = 33 MHz φ = 25 MHz φ = 16 MHz φ = 12.5 MHz Baud Rate [bps] BRGC Error BRGC...
Page 290 CHAPTER 8 SERIAL INTERFACE FUNCTION Table 8-6. Baud Rate Generators 0 to 3 Set-up Values (when typical clocks are used) (2/2) (b) CSI φ = 33 MHz φ = 25 MHz φ = 16 MHz φ = 12.5 MHz Baud Rate [bps] BRGC Error BRGC...
Page 291: Baud Rate Generator Compare Registers 0 To 3 (Brgc0 To Brgc3)
CHAPTER 8 SERIAL INTERFACE FUNCTION (c) Error of baud rate The error of the baud rate is calculated as follows: Actual baud rate (baud rate with error) Error [%] = – 1 x 100 Desired baud rate (normal baud rate) Example: (9520/9600 –...
Page 292: Baud Rate Generator Prescaler Mode Registers 0 To 3 (Bprm0 To Bprm3)
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.5.3 Baud rate generator prescaler mode registers 0 to 3 (BPRM0 to BPRM3) These registers control the timer/count operation of the dedicated baud rate generator and select a count clock. They can be read/written in 8- or 1-bit units. Address After reset BPRM0...
Page 293: Selection Of Operational Serial Interface
CHAPTER 8 SERIAL INTERFACE FUNCTION 8.6 Selection of Operational Serial Interface CSI0 and CSI1 of the V854 are alternate pins for UART and I C. Therefore, they are used selecting either UART or I The selection is made by the following registers. (1) Selecting CSI0 or UART The setting is made by the ASIM0 register and the CSIM0 register.
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Page 295: Chapter 9 A/D Converter
CHAPTER 9 A/D CONVERTER 9.1 Features Analog input: 16 channels 8-bit A/D converter On-chip A/D conversion result register (ADCR0 to ADCR7) 8 bits x 8 A/D conversion trigger mode A/D trigger mode Timer trigger mode External trigger mode Sequential conversion 9.2 Configuration The A/D converter of the V854 adopts the sequential conversion method, and uses the A/D converter mode registers (ADM0, ADM1), and ADCRn register to perform A/D conversion operations (n = 0 to 7).
Page 296 CHAPTER 9 A/D CONVERTER (6) A/D Conversion Result Register n (ADCRn) 8-bit register for retaining the A/D conversion result. The conversion result is loaded from the sequential conversion register (SAR) each time A/D conversion ends. This register becomes undefined by RESET input. (7) Controller Selects the analog input, generates the sample hold circuit operation timing, and controls the conversion trigger according to the mode set to the ADM0/ADM1 register.
Page 297: Control Register
CHAPTER 9 A/D CONVERTER 9.3 Control Register (1) A/D converter mode register 0 (ADM0) The ADM0 register is an 8-bit register which executes the selection of the analog input pin, specification of the operation mode, and conversion operations. This register can be read/written in 8- or 1-bit units, However, when the data is written to the ADM0 register during A/D conversion operations, the conversion operation is initialized and conversion is executed from the beginning.
Page 298 CHAPTER 9 A/D CONVERTER Bit Position Bit Name Function 2 to 0 ANIS2 to Analog Input Select ANIS0 Specifies analog input pin to A/D convert. ANIS2 ANIS1 ANIS0 Select Mode Scan Mode ANI0/ANI8 ANI0/ANI8 ANI1/ANI9 ANI0, ANI1/ANI8, ANI9 ANI2/ANI10 ANI0 to ANI2/ANI8 to ANI10 ANI3/ANI11 ANI0 to ANI3/ANI8 to ANI11 ANI4/ANI12...
Page 299 CHAPTER 9 A/D CONVERTER (2) A/D converter mode register 1 (ADM1) The ADM1 register is an 8-bit register which specifies the conversion operation time and trigger mode. This register can be read/written in 8- or 1-bit units. However, when the data is written to the ADM1 register during A/D conversion, the conversion operation is initialized and conversion is executed from the beginning again.
Page 300 CHAPTER 9 A/D CONVERTER The following shows the correspondence of each analog input pin to the ADCRn register (except 4-buffer mode). Analog Input Pin ADCRn Register PS = 0 PS =1 ANI0 ANI8 ADCR0 ANI1 ANI9 ADCR1 ANI2 ANI10 ADCR2 ANI3 ANI11 ADCR3...
Page 301: A/D Converter Operation
CHAPTER 9 A/D CONVERTER 9.4 A/D Converter Operation 9.4.1 Basic operation of A/D converter A/D conversion is executed in the following order. (1) The selection of the analog input and specification of the operation mode and trigger mode, etc., should be set in the ADMn register Note 1 (n = 0, 1).
Page 302 CHAPTER 9 A/D CONVERTER (1) Trigger mode There are three types of trigger modes which serve as the start timing of A/D conversion processing: A/D trigger mode, timer trigger mode, and external trigger mode. These trigger modes are set by the ADM0 register. (a) A/D trigger mode Generates the conversion timing of the analog input for the ANI0 to ANI15 pins inside the A/D converter unit.
Page 303 CHAPTER 9 A/D CONVERTER (a) Select mode A/D converts one analog input specified by the ADM0 register. The conversion results are stored in the ADCRn register corresponding to the analog input (n = 0 to 7). For this mode, the one-buffer mode and four-buffer mode are provided for storing the A/D conversion results.
Page 304 CHAPTER 9 A/D CONVERTER • Four-buffer mode A/D converts one analog input four times and stores the results in the four registers corresponding to analog input. The A/D conversion end interrupt (INTAD) is generated when the four A/D conversions end. Figure 9-4.
Page 305 CHAPTER 9 A/D CONVERTER Figure 9-4. Operation Timing Example of Select Mode: 4-Buffer Mode (ANI6) (2/2) Analog input ADCR register ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 A/D converter ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 ANI8 ANI9 ANI10 ANI11 ANI12...
Page 306 CHAPTER 9 A/D CONVERTER (b) Scan mode Selects the analog inputs specified by the ADM0 register sequentially from the ANI0 pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the analog input. When the conversion of the specified analog input ends, the INTAD interrupt is generated (n = 0 to 7).
Page 307 CHAPTER 9 A/D CONVERTER Figure 9-5. Operation Timing Example of Scan Mode: 4-Channel Scan (ANI0 to ANI3) (2/2) Analog input ADCR register ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 A/D converter ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 ANI8 ANI9 ANI10...
Page 308: Operation In The A/D Trigger Mode
CHAPTER 9 A/D CONVERTER 9.5 Operation in the A/D Trigger Mode When the CE bit of the ADM0 register is set to 1, A/D conversion is started. 9.5.1 Select mode operation The A/D converter converts the analog input specified by the ADM0 register. The conversion results are stored in the ADCRn register corresponding to the analog input.
Page 309 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode (A/D trigger select: 4-buffer) The A/D converter converts one analog input four times and stores the results in four ADCRn registers. (Refer to Table 9-2, Figure 9-7.) When A/D conversion ends four times, an INTAD interrupt is generated and the A/D conversion terminates.
Page 310: Scan Mode Operation
CHAPTER 9 A/D CONVERTER 9.5.2 Scan mode operation The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially and converted to digital. The A/D conversion results are stored in the ADCRn register corresponding to the analog input.
Page 311: Operation In The Timer Trigger Mode
CHAPTER 9 A/D CONVERTER 9.6 Operation in the Timer Trigger Mode The A/D converter can set conversion timings with the coincidence interrupt signals of the RPU compare register. TM0 and the capture/compare register (CC03) are used for the timer for specifying the analog conversion trigger. The following two modes are provided according to the specification of the TMC00 register.
Page 312 CHAPTER 9 A/D CONVERTER Table 9-4. Correspondence between Analog Input Pin and ADCRn Register (1-buffer mode (timer trigger select 1-buffer)) Trigger Analog Input A/D Conversion Results Register INTCC03 interrupt ANI0/ANI8 ADCR0 INTCC03 interrupt ANI1/ANI9 ADCR1 INTCC03 interrupt ANI2/ANI10 ADCR2 INTCC03 interrupt ANI3/ANI11 ADCR3 INTCC03 interrupt...
Page 313 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode operation (Timer trigger select: 4-buffer) A/D conversion of one analog input is executed four times, and the results are stored in the ADCRn register (Refer to Table 9-5, Figure 9-10). The A/D converter converts one analog input four times using the coincidence interrupt signal (INTCC03) as a trigger, and stores the results in four ADCRn registers.
Page 314: Scan Mode Operation
CHAPTER 9 A/D CONVERTER 9.6.2 Scan mode operation The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially, and A/D conversion is executed the number of times specified using the coincidence interrupt as trigger. The conversion results are stored in the ADCRn register corresponding to the analog input (refer to Table 9-6, Figure 9-11).
Page 315: Operation In The External Trigger Mode
CHAPTER 9 A/D CONVERTER 9.7 Operation in the External Trigger Mode In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing. The ADTRG pin is also used as the P22 pin. To set the external trigger mode, set the PMC22 bit of the PMC2 register to 1 and bits TRG1 to TRG0 of the ADM1 register to 10.
Page 316 CHAPTER 9 A/D CONVERTER Figure 9-12. Example of 1-Buffer Mode (external trigger select 1-buffer) Operation ADTRG ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 ANI4 ADCR4 A/D Converter ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 User’s Manual U11969EJ3V0UM00...
Page 317 CHAPTER 9 A/D CONVERTER (2) 4-buffer mode (External trigger select: 4-buffer) The A/D converter converts one analog input four times using the ADTRG signal as a trigger and stores the results in four ADCRn registers (refer to Table 9-8, Figure 9-13). The INTAD interrupt is generated and conversion ends when the four A/D conversions end.
Page 318: Scan Mode Operation (External Trigger Scan)
CHAPTER 9 A/D CONVERTER 9.7.2 Scan mode operation (External trigger scan) The analog inputs from ANI0/ANI8 to the analog input specified with the ADM0 register are selected sequentially and converted to digital when triggered by the ADTRG signal. The A/D conversion results are stored in the ADCRn register corresponding to the analog input (refer to Table 9-9, Figure 9-14).
Page 319: Precautions Regarding Operations
CHAPTER 9 A/D CONVERTER 9.8 Precautions Regarding Operations 9.8.1 Stop of conversion operations When 0 is written to the CE bit of the ADM0 register during conversion, conversion stops and the conversion results are not stored in the ADCRn register (n = 0 to 7). 9.8.2 Interval of the external/timer trigger Set the interval (input time interval) of the trigger during the external or timer trigger mode longer than the conversion time specified by the FR2 to FR0 bits of the ADM1 register.
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Page 321: Chapter 10 Real-Time Output Function
CHAPTER 10 REAL-TIME OUTPUT FUNCTION 10.1 Configuration and Function The real-time output function is realized by hardware consisting principally of the buffer register (PB) and the output latch (RTP) as shown in Figure 10-1. The real-time output function is a procedure that transfers the data previously prepared in the PB register to the output latch by hardware simultaneously with the generation of CM10 coincidence interrupt of timer 1, and outputs it to external.
Page 322: Control Register
CHAPTER 10 REAL-TIME OUTPUT FUNCTION 10.2 Control Register (1) Buffer register (PB) The buffer register is a register to which the data to be output from the real-time output port is written beforehand. This register can be read/written in 8- or 1-bit units. Address After reset FFFFF3C0H...
Page 323: Example
CHAPTER 10 REAL-TIME OUTPUT FUNCTION 10.4 Example The following shows an example of using RTP0 to RTP7 as an 8-bit real-time output port. The contents of the buffer register (PB) is output to RTP0 to RTP7 in each coincidence of the contents of TM1 and CM10 of timer 1.
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Page 325: Chapter 11 Pwm Unit
CHAPTER 11 PWM UNIT 11.1 Features PWMn: 4 channels 12- to 16-bit PWM output port Main pulse + additional pulse configuration Main pulse 4/5/6/7/8 bits Additional pulse 8 bits Repeat frequency: 129 kHz to 2 MHz (f = 33 MHz) PWMC Pulse width overwrite frequency selection: each one pulse/256 pulse Active level of the PWM output pulse can be selected.
Page 326: Configuration
CHAPTER 11 PWM UNIT 11.2 Configuration Figure 11-1 shows the configuration of the output circuit of PWMn. (1) Prescaler Divides the frequency of φ and generates PWM operational clock (f ). Prescaler output is selected by the PWMC PWPn0/PWPn1 bit of the PWPRn register. (2) Reload control Controls the reload of the modulo values of x-bit down counter and the 8-bit counter.
Page 327: Control Register
CHAPTER 11 PWM UNIT 11.3 Control Register (1) PWM control register 0 to 3 (PWMC0 to PWMC3) Controls PWMn operation, specifies the output active level, and specifies the bit length of the main pulse. This register can be read/written in 8- or 1-bit units. The contents of this register can also be changed during PWMn operation (PWME = 1).
Page 328 CHAPTER 11 PWM UNIT (2) PWM prescaler register 0 to 3 (PWPR0 to PWPR3) This register selects the operation clock (f ) of PWMn, and can be read/written in 8- or 1-bit units. Change PWMC the contents of this register while the bits of the PWMCn register are 0. If the contents of this register are changed when the setting of the PWMEn bit is 1, the operation cannot be guaranteed.
Page 329 CHAPTER 11 PWM UNIT (3) PWM modulo registers 0 to 3 (PWM0 to PWM3) The PWM modulo registers 0 to 3 are 16-bit registers used to determine the pulse width of the PWMn pulse. These registers can be read/written in 16-bit units. These registers consist of the following two parts.
Page 330: Pwm Operations
CHAPTER 11 PWM UNIT 11.4 PWM Operations 11.4.1 Basic operations of PWM The duty of the PWM pulse output is determined as follows by the value set to the modulo H register of the PWM modulo register (PWMn: n = 0 to 3 ). (Value of modulo H register) Note 1 Note 2...
Page 331 CHAPTER 11 PWM UNIT Figure 11-3. Example of PWM Output by Main Pulse and Additional Pulse 16-bit resolution is gained when the 256 outputs are averaged PWMn = xx40H Main pulse BRM additional pulse (Modulo L = 40H) PWM output PWMn = xxC0H Main pulse BRM additional pulse...
Page 332: Enabling/Disabling Pwm Operation
CHAPTER 11 PWM UNIT 11.4.2 Enabling/disabling PWM operation To output the PWM pulse, the PWME bit of the PWM control register (PWMCn) is set (1) after setting data to the PWM prescaler register (PWPRn) and the PWM modulo register (PWMn) (n = 0 to 3). Thereby, PWM pulse with active level specified by the PALVn bit of the PWMCn register is output from the PWM output pin.
Page 333: Specification Of Active Level Of Pwm Pulse
CHAPTER 11 PWM UNIT 11.4.3 Specification of active level of PWM pulse The PALVn bit of the PWM control register (PWMCn) specifies the active level of the PWM pulse output from the PWM output pin (n = 0 to 3). When the PALVn bit is set (1), a pulse with high active level is output, and when it is cleared (0), a pulse with low active level is output.
Page 334 CHAPTER 11 PWM UNIT (x+8) Figure 11-7. Example 1 of PWM Output Timing (PWM pulse width rewrite cycle 2 PWMC PWM pulse PWM pulse (x+8) (x+8) cycles cycles PWMn output pin Contents of PWMn register Enables Rewrites PWM output PWMn register PWM pulse width PWM pulse width PWM pulse width...
Page 335: Repetition Frequency
CHAPTER 11 PWM UNIT 11.4.5 Repetition frequency The repetition frequency of the PWMn is shown below (n = 0 to 3). Main Pulse Additional Pulse Repetition Frequency Pulse Width Rewrite Cycle Large Cycle (SYNn bit = 0) Small Cycle (SYNn bit = 1) 4 bits 8 bits PWMC...
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Page 337: Chapter 12 Port Function
CHAPTER 12 PORT FUNCTION 12.1 Features The ports of the V854 have the following features: Number of pins: input: 16 I/O: 96 Also function as I/O pins of other peripheral functions Can be set in input/output mode in 1-bit units User’s Manual U11969EJ3V0UM00...
Page 338: Basic Configuration Of Ports
CHAPTER 12 PORT FUNCTION 12.2 Basic Configuration of Ports The V854 is provided with a total of 112 input/output port pins (of which 16 are input-only port pins) that make up ports 0 to 14. The configuration of the V854’s ports is shown below. (P20 cannot be used for a port function.) Port 0 Port 7 Port 1...
Page 339 CHAPTER 12 PORT FUNCTION (1) Function of each port The ports of the V854 have the functions shown in the table below. Each port can be manipulated in 8- or 1-bit units and perform various types of control operations. In addition to port functions, the ports also have functions as internal hardware input/output pins, when placed in the control mode.
Page 340 CHAPTER 12 PORT FUNCTION (2) Register for setting function at reset and port/control mode of each port pin (1/2) Function after Reset (Input/output is shown in parentheses) Register for Port Name Pin Name In Single-Chip In Single-Chip In ROM-less In ROM-less Setting Mode Mode 1 Mode 2...
Page 341 CHAPTER 12 PORT FUNCTION (2/2) Function after Reset (Input/output is shown in parentheses) Register for Port Name Pin Name In Single-Chip In Single-Chip In ROM-less In ROM-less Setting Mode Mode 1 Mode 2 Mode 1 Mode 2 Port 9 P90/LBEN/WRL P90 (input) LBEN (output) WRL (output)
Page 342 CHAPTER 12 PORT FUNCTION Figure 12-1. Block Diagram of Type A PMCmn PMmn Output signal in control mode PORT Address Remark m: port number n: bit number Figure 12-2. Block Diagram of Type B PMCmn PMmn PORT Address Input signal Noise elimination Edge detection in control mode...
Page 343 CHAPTER 12 PORT FUNCTION Figure 12-3. Block Diagram of Type C PMCmn PMmn Output signal in control mode PORT Address Input signal in control mode Remark m: port number n: bit number Figure 12-4. Block Diagram of Type D PMCmn PMmn PORT Address...
Page 344 CHAPTER 12 PORT FUNCTION Figure 12-5. Block Diagram of Type E MODE0 to MODE2 MM0 to MM2 Input/output control circuit PMmn Output signal PORT in control mode Address Input signal in control mode Remark m: port number n: bit number Figure 12-6.
Page 345 CHAPTER 12 PORT FUNCTION Figure 12-7. Block Diagram of Type G Input signal ANI0 to ANI15 in control mode Remark m: 7, 8 n: 0 to 7 Figure 12-8. Block Diagram of Type H MODE0 to MODE2 MM0 to MM2 Input/output control circuit PM96 PORT...
Page 346 CHAPTER 12 PORT FUNCTION Figure 12-9. Block Diagram of Type I Noise elimination Address Edge detection Figure 12-10. Block Diagram of Type J PMmn PORT Address Remark m: port number n: bit number User’s Manual U11969EJ3V0UM00...
Page 347 CHAPTER 12 PORT FUNCTION Figure 12-11. Block Diagram of Type K PMCmn PMmn Output signal in control mode PORT N-ch Address Input signal in control mode Remark m: port number n: bit number User’s Manual U11969EJ3V0UM00...
Page 348: Port Pin Function
CHAPTER 12 PORT FUNCTION 12.3 Port Pin Function 12.3.1 Port 0 Port 0 is an 8-bit input/output port that can be set to the input or output mode in 1-bit units. Address After reset FFFFF000H Undefined Bit Position Bit Name Function 7 to 0 Port 0...
Page 349 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 0 is set by port mode register 0 (PM0). The control mode is set by port mode control register 0 (PMC0). Port 0 mode register (PM0) This register can be read/written in 8- or 1-bit units.
Page 350: Port 1
CHAPTER 12 PORT FUNCTION 12.3.2 Port 1 Port 1 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset FFFFF002H Undefined Bit Position Bit Name Function 7 to 0 Port 1 (n = 7 to 0) I/O port...
Page 351 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode The input/output mode of port 1 is set by port mode register 1 (PM1). The control mode is set by port mode control register 1 (PMC1). Port 1 mode register (PM1) This register can be read/written in 8- or 1-bit units. Address After reset PM17...
Page 352: Port 2
CHAPTER 12 PORT FUNCTION 12.3.3 Port 2 Port 2 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. P20, however, always operates as the NMI input when an edge is input. Address After reset –...
Page 353 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 2 is set by port mode register 2 (PM2). The control mode is set by port mode control register 2 (PMC2). P20 is fixed to NMI input. Port 2 mode register (PM2) This register can be read/written in 8- or 1-bit units.
Page 354: Port 3
CHAPTER 12 PORT FUNCTION 12.3.4 Port 3 Port 3 is a 7-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset – FFFFF006H Undefined Bit Position Bit Name Function 6 to 0 Port 3 (n = 6 to 0) I/O port...
Page 355 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 3 is set by port mode register 3 (PM3). The control mode is set by port mode control register 3 (PMC3). Port 3 mode register (PM3) This register can be read/written in 8- or 1-bit units.
Page 356 CHAPTER 12 PORT FUNCTION Port 3 mode control register (PMC3) This register can be read/written in 8- or 1-bit units. However, the higher 2 bits are fixed to “0” by hardware, and ignored when “1 “ is written in. Address After reset PMC3 PMC35...
Page 357: Port 4
CHAPTER 12 PORT FUNCTION 12.3.5 Port 4 Port 4 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset FFFFF008H Undefined Bit Position Bit Name Function 7 to 0 Port 4 (n = 7 to 0) I/O port...
Page 358 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 4 is set by port mode register 4 (PM4). The control mode (external expansion mode) is set by mode specification pins MODE and memory expansion mode register (MM: refer to 3.4.6 (1)) (n = 0 to 2).
Page 359: Port 5
CHAPTER 12 PORT FUNCTION 12.3.6 Port 5 Port 5 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset FFFFF00AH Undefined Bit Position Bit Name Function 7 to 0 Port 5 (n = 7 to 0) I/O port...
Page 360 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 5 is set by port mode register 5 (PM5). The control mode (external expansion mode) is set by mode specification pins MODEn and memory expansion mode register (MM: refer to 3.4.6 (1)) (n = 0 to 2).
Page 361: Port 6
CHAPTER 12 PORT FUNCTION 12.3.7 Port 6 Port 6 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset FFFFF00CH Undefined Bit Position Bit Name Function 7 to 0 Port 6 (n = 7 to 0) I/O port...
Page 362 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 6 is set by port mode register 6 (PM6). The control mode (external expansion mode) is set by mode specification pins MODEn and memory expansion mode register (MM: refer to 3.4.6 (1)) (n = 0 to 2).
Page 363: Port 7, Port 8
CHAPTER 12 PORT FUNCTION 12.3.8 Port 7, port 8 Port 7 and port 8 are 8-bit input only ports and all pins of port 7 and port 8 are fixed in the input mode. Address After reset FFFFF00EH Undefined Address After reset FFFFF010H Undefined...
Page 364: Port 9
CHAPTER 12 PORT FUNCTION 12.3.9 Port 9 Port 9 is a 7-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset – FFFFF012H Undefined Bit Position Bit Name Function 6 to 0 Port 9 (n = 6 to 0) I/O port...
Page 365 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 9 is set by port mode register 9 (PM9). The control mode (external expansion mode) is set by the mode specification pin MODEn and the memory expansion mode register (MM: refer to 3.4.6 (1)) (n = 0 to 2).
Page 366: Port 10
CHAPTER 12 PORT FUNCTION 12.3.10 Port 10 Port 10 is a 4-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset – – – – P103 P102 P101 P100 FFFFF014H Undefined Bit Position Bit Name Function...
Page 367 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 10 is set by port mode register 10 (PM10). The control mode is set by port mode control register 10 (PMC10). Port 10 mode register (PM10) This register can be read/written in 8- or 1-bit units.
Page 368: Port 11
CHAPTER 12 PORT FUNCTION 12.3.11 Port 11 Port 11 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset P117 P116 P115 P114 P113 P112 P111 P110 FFFFF016H Undefined Bit Position Bit Name Function...
Page 369 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 11 is set by port mode register 11 (PM11). The control mode is set by port mode control register 11 (PMC11). Port 11 mode register (PM11) This register can be read/written in 8- or 1-bit units.
Page 370 CHAPTER 12 PORT FUNCTION Port 11 mode control register (PMC11) This register can be read/written in 8- or 1-bit units. Address After reset PMC11 PMC117 PMC116 PMC115 PMC114 PMC113 PMC112 PMC111 PMC110 FFFFF056H Bit Position Bit Name Function PMC117 Port Mode Control Sets P117 pin in input/output mode.
Page 371: Port 12
CHAPTER 12 PORT FUNCTION 12.3.12 Port 12 Port 12 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset P127 P126 P125 P124 P123 P122 P121 P120 FFFFF018H Undefined Bit Position Bit Name Function...
Page 372 CHAPTER 12 PORT FUNCTION Port 12 mode control register (PMC12) Port 12 can be read/written in 8- or 1-bit units. However, bit 6 is fixed to “0” by hardware and ignored if “1” is written in. Address After reset PMC12 PMC127 PMC125 PMC124...
Page 373: Port 13
CHAPTER 12 PORT FUNCTION 12.3.13 Port 13 Port 13 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset P137 P136 P135 P134 P133 P132 P131 P130 FFFFF01AH Undefined Bit Position Bit Name Function...
Page 374 CHAPTER 12 PORT FUNCTION (2) Setting input/output mode and control mode The input/output mode of port 13 is set by port mode register 13 (PM13). The control mode is set by port mode control register 13 (PMC13). Port 13 mode register (PM13) This register can be read/written in 8- or 1-bit units.
Page 375: Port 14
CHAPTER 12 PORT FUNCTION 12.3.14 Port 14 Port 14 is an 8-bit input/output port that can be set in the input or output mode in 1-bit units. Address After reset P147 P146 P145 P144 P143 P142 P141 P140 FFFFF01CH Undefined Bit Position Bit Name Function...
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Page 377: Chapter 13 Reset Function
CHAPTER 13 RESET FUNCTION When the low-level is input to the RESET pin, the system is reset and each on-chip hardware is initialized to the initial state. When the RESET pin changes from low-level to high-level, the reset state is released and the CPU starts executing the program.
Page 378 CHAPTER 13 RESET FUNCTION Table 13-1. Operating Status of I/O and Output Pins During Reset Period I/O or Output Pin Pin Status In Single-Chip In Single-Chip In ROM-less In ROM-less In Flash Memory Mode 1 Mode 2 Mode 1 Mode 2 Programming Mode P00 to P07, P10 to P17, P21 to P26, P30 to (Input) Hi-Z...
Page 379: Initialize
CHAPTER 13 RESET FUNCTION (2) Power-ON reset For the reset operations at power-on it is necessary to secure an oscillation stabilization time of 10 ms or more from when the power supply starts until reset is accepted by the low-level width of the RESET pin. Furthermore, it is also necessary to secure oscillation stabilization time when an external clock is used in the direct mode.
Page 380 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values after Reset of Each Register (1/2) Register Initial Value after Reset 00000000H r1 to r31 Undefined 00000000H 00000020H EIPC Undefined EIPSW Undefined FEPC Undefined FEPSW Undefined 00000000H Internal RAM Undefined Port Output latch (P0 to P6, P9 to P14) Undefined Mode register (PM0 to PM6, PM9 to PM14) Mode control register (PMC0, PMC1, PMC3, PMC10 to PMC13)
Page 381 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values after Reset of Each Register (2/2) Register Initial Value after Reset Real-time output function Port 13 buffer register (PB) Undefined Output latch register (RTP) Undefined Serial interface Asynchronous serial interface mode register (ASIM0) Asynchronous serial interface mode register (ASIM1) Asynchronous serial interface status register (ASIS) Receive buffer (RXB, RXBL)
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Page 383: Chapter 14 Flash Memory ( Μ Pd70F3008 And 70F3008Y Only)
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) The µ PD70F3008 and 70F3008Y of the V854 are provided with a 128-Kbyte flash memory. In the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock as well as the mask ROM version. Writing to a flash memory can be performed with memory mounted on the target system (on board).
Page 384: Programming Environment
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V854. RS-232C RESET UART/CSI0 Dedicated flash writer Host machine V854 A host machine is required for controlling the dedicated flash writer. UART or CSI is used as the interface between the dedicated flash writer and the V854 to perform writing, erasing, etc.
Page 385: Communication System
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.4 Communication System The communication between the dedicated flash writer and the V854 is performed by serial communication using UART or CSI0. (1) UART Transfer rate: 1200 to 76800 bps (LSB first) RESET Dedicated flash writer V854...
Page 386 CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) Measurement FlashproII V854 when connected Signal Name Pin Function Pin Name CSIn UART Output Writing voltage voltage generation/ voltage monitoring – Ground Output Clock output to V854 Note RESET Output Reset signal RESET SI/R...
Page 387: Pin Handling
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.5 Pin Handling When performing on-board writing, install a connector on the target system to connect to the dedicated flash writer. Also, install the function on-board to switch from the normal operation mode to the flash memory programming mode. When switched to the flash memory programming mode, all the pins not used for the flash memory programming become the same status as that immediately after reset of single-chip mode 1.
Page 388: Serial Interface Pin
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.5.2 Serial interface pin The following shows the pins used by each serial interface. Serial Interface Pins Used CSI0 SO0, SI0, SCK0 UART TXD, RXD When connecting a dedicated flash writer to a serial interface pin which is connected to other devices on-board, care should be taken to the conflict of signals and the malfunction of other devices, etc.
Page 389 CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) (2) Malfunction of the other device When connecting a dedicated flash writer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored.
Page 390: Reset Pin
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.5.3 Reset pin When connecting the reset signals of the dedicated flash writer to the RESET pin which is connected to the reset signal generation circuit on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generation circuit.
Page 391: Programming Method
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.6 Programming Method 14.6.1 Flash memory control The following shows the procedure that this firmware manipulates the flash memory. Starts Switches to flash memory programming mode Supplies RESET pulse Selects communication system Manipulates flash memory Ends ? Ends...
Page 392: Flash Memory Programming Mode
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.6.2 Flash memory programming mode When rewriting the contents of a flash memory using the dedicated flash writer, set the V854 in the flash memory programming mode. When switching to modes, set MODE0 through MODE2 and V pin before releasing reset.
Page 393: Communication Command
CHAPTER 14 FLASH MEMORY ( µ PD70F3008 AND 70F3008Y ONLY) 14.6.4 Communication command The V854 communicates with the dedicated flash writer by means of commands. The command sent from the dedicated flash writer to the V854 is called a “command”. The response signal sent from the V854 to the dedicated flash writer is called a “response command”.
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Page 395: Chapter 15 Differences Between Versions
CHAPTER 15 DIFFERENCES BETWEEN VERSIONS 15.1 Differences between Versions with I C Function and Versions without I C Function C function are µ PD703008Y and 70F3008Y. They are identified by The product names of the versions with the I the letter “Y” in the product names. µ...
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Page 397 APPENDIX A REGISTER INDEX (1/6) Symbol Name Unit Page ADCR0 A/D conversion result register 0 ADCR1 A/D conversion result register 1 ADCR2 A/D conversion result register 2 ADCR3 A/D conversion result register 3 ADCR4 A/D conversion result register 4 ADCR5 A/D conversion result register 5 ADCR6 A/D conversion result register 6...
Page 398 APPENDIX A REGISTER INDEX (2/6) Symbol Name Unit Page CM10 Compare register 10 CM10L Compare register 10L CM11 Compare register 11 CM11L Compare register 11L CM20 Compare register 20 CM21 Compare register 21 CM22 Compare register 22 CM23 Compare register 23 CM24 Compare register 24 CM1IC0...
Page 399 APPENDIX A REGISTER INDEX (3/6) Symbol Name Unit Page EDV1 Event divide counter 1 INTC EDV2 Event divide counter 2 INTC EIPC Interrupt status save register EIPSW Interrupt status save register Event selection register INTC FEPC NMI status save register FEPSW NMI status save register IICC...
Page 400 APPENDIX A REGISTER INDEX (4/6) Symbol Name Unit Page P1IC0 Interrupt control register INTC P1IC1 Interrupt control register INTC P1IC2 Interrupt control register INTC P1IC3 Interrupt control register INTC P5IC0 Interrupt control register INTC P5IC1 Interrupt control register INTC P5IC2 Interrupt control register INTC P5IC3...
Page 401 APPENDIX A REGISTER INDEX (5/6) Symbol Name Unit Page PWMC3 PWM control register 3 PWPR0 PWM prescaler register 0 PWPR1 PWM prescaler register 1 PWPR2 PWM prescaler register 2 PWPR3 PWM prescaler register 3 Output latch register Receive buffer (9 bits) UART RXBL Receive buffer L (lower 8 bits)
Page 402 APPENDIX A REGISTER INDEX (6/6) Symbol Name Unit Page TOVS Timer overflow status register Transmit shift register (9 bits) UART TXSL Transmit shift register L (lower 8 bits) UART User’s Manual U11969EJ3V0UM00...
Page 403 APPENDIX B INSTRUCTION SET LIST Legend (1) Symbols used for operand description Symbol Description reg1 General register (r0 to r31): Used as source register reg2 General register (r0 to r31): Mainly used as destination register immx x-bit immediate dispx x-bit displacement reglD System register number bit#3...
Page 404 APPENDIX B INSTRUCTION SET LIST Symbol Description Exclusive logical sum Logical negate logically shift left by Logical left shift logically shift right by Logical right shift arithmetically shift right by Arithmetic right shift (3) Symbols used for execution clock description Symbol Description i : issue...
Page 405 APPENDIX B INSTRUCTION SET LIST Instruction Set (alphabetical order) (1/4) Execution Flag Clock Operand Code Operation Mnemonic l CY OV S Z SAT reg1, reg2 GR[reg2]←GR[reg2]+GR[reg1] r r r r r 0 0 1 1 1 0RRRRR imm5, reg2 r r r r r 0 1 0 0 1 0 i i i i i GR[reg2]←GR[reg2]+sign-extend(imm5) ADDI imm16, reg1, reg2...
Page 406 APPENDIX B INSTRUCTION SET LIST Instruction Set (alphabetical order) (2/4) Execution Flag Clock Mnemonic Operand Code Operation l CY OV S Z SAT r r r r r 1 1 1 1 1 1RRRRR LDSR reg2, regID SR[regID]←GR[reg2] regID = EIPC, FEPC 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 regID = EIPSW, FEPSW Note 1...
Page 407 APPENDIX B INSTRUCTION SET LIST Instruction Set (alphabetical order) (3/4) Execution Flag Clock Mnemonic Operand Code Operation l CY OV S Z SAT SATADD reg1, reg2 r r r r r 0 0 0 1 1 0RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1]) r r r r r 0 1 0 0 0 1 i i i i i imm5, reg2 GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)) SATSUB...
Page 408 APPENDIX B INSTRUCTION SET LIST Instruction Set (alphabetical order) (4/4) Execution Flag Clock Mnemonic Operand Code Operation l CY OV S Z SAT r r r r r 1 1 1 0 1 1RRRRR ST.H reg2, disp16[reg1] adr←GR[reg1]+sign-extend(disp16) d d d d d d d d d d d d d d d 0 Store-memory(adr, GR[reg2], Halfword) Note ST.W...
Page 409 APPENDIX C INDEX baud rate generator 1-bit output port ............ 154 compare register 0 to 3 ........291 144-pin plastic LQFP ..........25 baud rate generator prescaler mode register 0 to 3 ......292 baud rate generators 0 to 3 set-up values ..289 A/D conversion result register ......
Page 410 APPENDIX C INDEX CC3PR00 to CC3PR02 ........116 communication command ........393 CCLR0 ..............168 communication reservation ........273 CE ................297 compare operation (timer 0) ........ 181 CE0 ............... 166 compare operation (timer 1) ........ 187 CE1 ............... 169 compare operation (timer 2) ........
Page 411 APPENDIX C INDEX DSTB ............... 41 flash memory programming mode ....54, 392 DWC ................ 86 FR0 to FR2 ............299 DWn0, DWn1 (n = 0 to 7) ........86 frequency divider ..........124 FS0 to FS2 ............154 function block configuration ........28 EBS ...............
Page 412 APPENDIX C INDEX INTC ................ 29 INTCM10, INTCM11 ..........100 maskable interrupt ..........107 INTCM20 to INTCM24 .......... 100 maskable interrupt status flag ......118 INTCP10 to INTCP13 ........... 100 measurement of cycle .......... 201 INTCSI0 to INTCSI3 ..........101 measurement of pulse width ........
Page 413 APPENDIX C INDEX overflow (timer 3) ..........192 PC ................51 OVFn (n = 0, 1, 20 to 24, 3) ........ 173 PE ................212 OVIC0, OVIC1 ............116 period in which interrupt is not acknowledged ..133 OVIF0, OVIF1 ............116 peripheral I/O area ..........
Page 414 APPENDIX C INDEX PMC130 to PMC137 ..........374 PRCMD ..............78 PMC2 ..............353 PRERR ............79, 139 PMC21 to PMC26 ..........353 PRM00 to PRM03 ..........166 PMC3 ..............356 PRM10 to PRM13 ..........169 PMC30 to PMC35 ..........356 PRM2n0 to PRM2n4 (n = 0 to 4) ......
Page 415 APPENDIX C INDEX RXB, RXBL ............213 SRIF0 ..............116 RXB0 to RXB7 ............213 SRMK0 ..............116 RXD ................. 38 SRPR00 to SRPR02 ..........116 RXE ............... 209 stack pointer ............51 RXEB ..............213 start condition ............243 status saving register for interrupt ......
Page 416 APPENDIX C INDEX timer output control register 0, 1 ......172 WRL ................ 42 timer overflow status register ....... 173 WTIM ..............238 timer trigger mode ........302, 311 Word access ............84 timer/counter function ........... 157 Wrap-around ............ 58, 69 timing of 3-wire serial I/O mode ..
Page 417 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

V854 upd703008 V854 upd70f3008 V854 upd703008y V854 upd70f3008y

NEC V854 UPD703006 User Manual

Chapter 1 Introduction

General

Features

Application Fields

Ordering Information

Pin Identification (Top View)

Function Block Configuration

Chapter 2 Pin Functions

Pin Function List

Pin Status

Pin Function

Pin I/O Circuit Type and Connection of Unused Pins

I/O Circuits of Pins

Chapter 3 Cpu Functions

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Bus Control Function

Features

Bus Control Pins and Control Register

Bus Access

Memory Block Function

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Timing

Bus Priority

Memory Boundary Operation Condition

Internal Peripheral I/O Interface

Chapter 5 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Multiple Interrupt Processing

Periods Where Interrupt Is Not Acknowledged

Interrupt Response Time

Chapter 6 Clock Generator Function

Features

Configuration

Selecting Input Clock

PLL Lock-Up

Power Save Control

Specifying Oscillation Stabilization Time

Clock Output Control

Chapter 7 Timer/Counter Function (Real-Time Pulse Unit)

Features

Basic Configuration

Control Register

Timer 0 Operation

Timer 1 Operation

Timer 2 Operation

Timer 3 Operation

Application Examples

Note

Chapter 8 Serial Interface Function

Features

Asynchronous Serial Interface (UART)

Clocked Serial Interface 0 to 3 (CSI0 to CSI3)

I 2 C Bus ( Μ PD703008Y and 70F3008Y Only)

Baud Rate Generator 0 to 3 (BRG0 to BRG3)

Selection of Operational Serial Interface

Chapter 9 A/D Converter

Features

Configuration

Control Register

A/D Converter Operation

Operation in the A/D Trigger Mode

Operation in the Timer Trigger Mode

Operation in the External Trigger Mode

Precautions Regarding Operations

Chapter 10 Real-Time Output Function

Configuration and Function

Control Register

Operation

Example

Chapter 11 Pwm Unit