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The OnCE controller and serial interface contain the following blocks: OnCE TAP con-
troller, the OnCE command register, OnCE decoder, and the OnCE control and status
registers.
The OnCE command register acts as the IR for the TAP controller. All other OnCE
resources are treated as data registers (DR) by the TAP controller. The command
register is loaded by serially shifting in commands during the TAP controller shift-IR
state, and is loaded during the update-IR state. The command register selects a
OnCE resource to be accessed as a data register (DR) during the TAP controller cap-
ture-DR, shift-DR and update-DR states.
16.5 OnCE Interface Signals
The following paragraphs describe the OnCE interface signals to other internal blocks
associated with the OnCE controller. These signals are not available externally, and
descriptions are provided to improve understanding of OnCE operation.
16.5.1 Internal Debug Request Input (IDR)
The internal debug request input is a hardware signal which is used in some imple-
mentations to force an immediate debug request to the CPU. If present and enabled,
it functions in an identical manner to the control function provided by the DR control
bit in the OnCE control register (OCR). This input is maskable by a control bit in OCR.
16.5.2 CPU Debug Request (DBGRQ)
The DBGRQ signal is asserted by the OnCE control logic to request the CPU to enter
the debug state. It may be asserted for a number of different conditions. Assertion of
this signal causes the CPU to finish the current instruction being executed, save the
instruction pipeline information, enter debug mode, and wait for further commands.
Asserting DBGRQ causes the device to exit stop, doze, or wait mode.
16.5.3 CPU Debug Acknowledge (DBGACK)
The CPU asserts the DBGACK signal upon entering the debug state. This signal is
part of the handshake mechanism between the OnCE control logic and the CPU.
16.5.4 CPU Breakpoint Request (BRKRQ)
The BRKRQ signal is asserted by the OnCE control logic to signal that a breakpoint
condition has occurred for the current CPU bus access.
16.5.5 CPU Address, Attributes (ADDR, ATTR)
The CPU address and attribute information may be used in the memory breakpoint
logic to qualify memory breakpoints with access address and cycle type information.
16.5.6 CPU Status (PSTAT)
The trace logic uses the CPU PSTAT signals to qualify trace count decrements with
specific CPU activity.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
16-5
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