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Principle analysis of single chip in voltage domain（Figure 5 Figure 6 below）：
Signal Description
Active
Name
I/O
Level
NRSTO
O
L
1
BO
O
H
2
RI_A
I
N/A
3
Re
I
N/A
4
5、BM1387 Circuit diagram
6、BM1387 Chip Pin
Description
Output to the chip of next level, for the loop
Respond Busy Output
Auxiliary Respond Input add diode and pulldown
Respond Input. Schmitt input and internal pullup
4
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