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Sony DCR-PC115 Service Manual page 12

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DCR-PC115/PC115E/PC120BT/PC120E
For Schematic Diagram
• Refer to page 4-19 for printed wiring board.
1
2
3
VC-270 BOARD(7/18)
DV INTERFACE(JC BLOCK)
A
-REF.NO.:20,000 SERIES-
XX MARK:NO MOUNT
:Voltage measurement is impossible
for the CSP ICs and the Transistors
that are shown with the
mark.
MCDA7
B
MCDA7
MCDA6
MCDA6
MCDA5
MCDA5
MCDA4
MCDA4
MCDA3
MCDA3
MCDA2
MCDA2
TO(6/18,
48
MCDA1
14/18)
MCDA1
MCDA0
MCDA0
MCCE
C
MCCE
RDX
RDX
WRX
WRX
ALE
ALE
XRST_LINK
XRST_LINK
XDVCN
XDVCN
XRST_PHY
XRST_PHY
60
LIP_SLEEP
TO(14/18)
LIP_SLEEP
D
LPS
LPS
OFR
OFR
FRL
FRL
XENA
XENA
LBUS0
LBUS0
LBUS1
LBUS1
LBUS2
LBUS2
LBUS3
E
LBUS3
50
TO(6/18)
FCLR
FCLR
XACC
XACC
DIR
DIR
TRCK
LCKO
F
FB5601
0uH
D_1.9V
61
TO(18/18)
D_2.8V
C5601
G
REG_GND
16
DV INTERFACE
VC-270 (7/18)
4
5
40
39
38
37
(D_1.9-2)
VDD2
LBUS3
ID3
LBUS2
ID2
LBUS1
ID1
LBUS0
ID0
VSS
ICLK
VSS
/(GND)
XENA
XINEN
FRL
FR
OFR
OFR
FCLR
IFCLEAR
VDD3
(D_2.8-3)
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
L5601
10uH
FB5602
0uH
0.1u
B
C5607
C5608
0.01u
10u
B
6.3V
4-35
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
CNA
XRESETP
PWD
(D_2.8-3)
VDD3
(D_1.9-2)
VDD2
AVS
IC5603
(D_2.8-2)
AVD3
(D_2.8-2)
AVD3
DV INTERFACE
(GND)/
R1
IC5603
R0
SN104266BGGM-TEB
TPA+
CSP(CHIP SIZE PACKAGE)IC
TPA-
TPB+
TPB-
(D_2.8-2)
AVD3
TPBIAS
AVS
(D_2.8-2)
AVD3
AVS
C5614
0.1u
B
C5613
C5609
0.01u
0.01u
B
B
P
9
10
11
SIGNAL PATH
VIDEO SIGNAL
XDVCN
CHROMA
Y
Y/CHROMA
XRST_PHY
REC
LIP_SLEEP
PB
R5752
12k
± 0.5%
R5755
12k
± 0.5%
CN5601
TPA+
4
TPA
TPA-
NTPA
3
TPB+
TPB
2
TPB-
NTPB
1
R5759
R5761
R5763
56
56
56
± 0.5%
± 0.5%
± 0.5%
R5758
56
R5760
R5762
± 0.5%
C5617
10k
10k
± 0.5%
220p
± 0.5%
B
C5616
1u
B
4-36
12
13
AUDIO
SIGNAL
4P
DV

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