Dsp56F801Evm Architecture; Block Diagram Of The Dsp56F801Evm - Motorola DSP56F801 Hardware User Manual

1.1 DSP56F801EVM Architecture

The DSP56F801EVM facilitates the evaluation of various features present in the
DSP56F801 part. The DSP56F801EVM can be used to develop real-time software and
hardware products based on the DSP56F801. The DSP56F801EVM provides the features
necessary for a user to write and debug software, demonstrate the functionality of that
software and interface with the customer's application-specific device(s). The
DSP56F801EVM is flexible enough to allow a user to fully exploit the DSP56F801's
features to optimize the performance of their product, as shown in
RESET
LOGIC
MODE/IRQ
LOGIC
JTAG
Connector
Parallel
DSub
JTAG
25-Pin
Interface
Low Freq
Crystal
Figure 1-1. Block Diagram of the DSP56F801EVM
1-2
DSP56F801
RESET SCI
SPI
MODE/IRQ
TIMER
PWM
JTAG/OnCE
A/D
XTAL/EXTAL +3.3V & GND
DSP56F801EVM Hardware User's Manual
Figure 1-1.
RS-232
DSub
Interface
9-Pin
Debug LEDs
Peripheral
Expansion
PWM LEDs
Connector(s)
Over V Sense
Over I Sense
Zero Crossing
Detect
UNI-3
Power Supply
+3.3V, +5.0V & +3.3VA