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ARM MPS3 Technical Reference Manual

Fpga prototyping board
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Arm
MPS3 FPGA Prototyping Board
®
Technical Reference Manual
Copyright © 2017–2020 Arm Limited or its affiliates. All rights reserved.
100765_0000_04_en

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  • Page 1 MPS3 FPGA Prototyping Board ® Technical Reference Manual Copyright © 2017–2020 Arm Limited or its affiliates. All rights reserved. 100765_0000_04_en...
  • Page 2 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

  • Page 4: Table Of Contents

    Feedback ........................10 Chapter 1 Introduction Precautions ......................1-12 About the MPS3 board .................... 1-13 Location of components on the MPS3 board ............1-15 Chapter 2 Hardware description Overview of the board hardware ................2-17 Example Cortex -M33 IoT Kit subsystem design ............ 2-21 ®...
  • Page 5 Audio connectors, stacked stereo jacks ............Appx-A-86 12V power connector ..................Appx-A-87 Appendix B Specifications Available power for expansion boards ............Appx-B-89 Appendix C Revisions Revisions ...................... Appx-C-91 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 6 This preface introduces the Arm MPS3 FPGA Prototyping Board Technical Reference Manual. ® It contains the following: • About this book on page • Feedback on page 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 7: About This Book

    Glossary is a list of terms used in Arm documentation, together with definitions for those ® terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Glossary for more information.
  • Page 8 • Application Note AN524 Example SSE ‑ 200 Subsystem for MPS3 (DAI 0524). • Application Note AN533 Blinky example FPGA image for the MPS3 Prototyping Board (DAI 0533) • CoreLink ‑ 200 System IP for Embedded Technical Reference Manual (DDI 0571).
  • Page 9 Preface About this book Other publications • See the Xilinx website https://www.xilinx.com for information about the Xilinx Kintex Ultrascale XCKU115‑1FLVB1760C FPGA. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 10: Feedback

    A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. 100765_0000_04_en Copyright ©...
  • Page 11 1.1 Precautions on page 1-12. • 1.2 About the MPS3 board on page 1-13. • 1.3 Location of components on the MPS3 board on page 1-15. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 1-11 reserved. Non-Confidential...

  • Page 12: Chapter 1 Introduction

    1 Introduction 1.1 Precautions Precautions You can take certain precautions to ensure safety and to prevent damage to your MPS3 board. This section contains the following subsections: • 1.1.1 Ensuring safety on page 1-12. • 1.1.2 Operating temperature on page 1-12.

  • Page 13: About The Mps3 Board

    1.2 About the MPS3 board About the MPS3 board The MPS3 board is an FPGA Internet of Things (IoT) development platform. The board is designed to support Arm Cortex‑M class and small to medium Arm Cortex‑A and Cortex‑R class processors, or dedicated custom designs.
  • Page 14 — P‑JTAG processor debug. — F‑JTAG (FPGA) debug. — Serial Wire Debug (SWD). — 16‑bit trace. — 4‑bit trace. — On‑board CMSIS‑DAP. — Four serial ports over USB. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 1-14 reserved. Non-Confidential...

  • Page 15: Location Of Components On The Mps3 Board

    1 Introduction 1.3 Location of components on the MPS3 board Location of components on the MPS3 board The following figure shows the physical layout of the MPS3 board. active Debug Hardware On/Off Soft Reset FPGA Audio Reset push button Shield and Pmod...
  • Page 16 2.17 FMC-HPC interface on page 2-46. • 2.18 System debug on page 2-50. • 2.19 Design settings for correct board operation with a minimal design on page 2-53. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-16 reserved. Non-Confidential...

  • Page 17: Overview Of The Board Hardware

    2.1 Overview of the board hardware Overview of the board hardware The MPS3 board provides access to the Kintex XCKU115 FPGA and peripherals to enable FPGA prototyping and software development. The following figure shows the hardware infrastructure of the MPS3 board.
  • Page 18 MPS3 FPGA Prototyping Board Figure 2-1 Hardware infrastructure of the MPS3 board The MPS3 board contains the following components: • One Xilinx Kintex Ultrascale XCKU115‑1FLVB1760C FPGA: 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-18 reserved. Non-Confidential...
  • Page 19 — 8MB external QSPI flash. — 4GB, 64‑bit external DDR4 SODIMM. — 16GB, 8‑bit external eMMC. • Motherboard Configuration Controller (MCC) that controls the MPS3 board, and supports board configuration at powerup or reset: — FPGA configuration. — Board configuration.
  • Page 20 — Yellow LED. Ethernet link and activity indicator‑incorporated into combined Ethernet and dual‑USB connector. Related information 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-20 reserved.

  • Page 21: Example Cortex

    -M33 IoT Kit subsystem design ® The MPS3 board is an FPGA Internet of Things (IoT) development platform. The board is designed to support Arm Cortex‑M class and small to medium Arm Cortex‑A and Cortex‑R class processors, or dedicated customs designs.
  • Page 22 C×2 Audio QSPI QSPI BRAM MIG7 HDLCD write QVGA CLCD and DDR4 QSPI eMMC µSD HDMI touchscreen Figure 2-2 Example IoT Kit subsystem design for MPS3 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-22 reserved. Non-Confidential...

  • Page 23: Clocks

    The MPS3 board provides fixed and programmable clocks to drive the FPGA and board interfaces. The following figure shows a functional overview of the clock systems of the MPS3 board. In this figure, the image implements OSC4 as the audio clock and OSC5 as the HDLCD clock.
  • Page 24 The system register interface can implement runtime control of the OSCs. PLLs within the FPGA can use the reference 24MHz to generate other fixed internal frequencies. The following table lists the MPS3 board clocks and their characteristics. Table 2-1 MPS3 board clocks Clock name:...

  • Page 25: Reset, Powerup, And Configuration

    There are two On/Off soft reset buttons. Both are labeled PBON. Pressing one of them performs a software reset, or if the board is already in the standby state, powers up the system. The following figure shows the MPS3 board reset system, where the FPGA contains a user image. FPGA...
  • Page 26 The reset signal for the serial interface of the Serial Configuration Controller (SCC). CPUWAIT Core register that is used to release processor core or cores from reset. Reset sequence The following figure shows the MPS3 board reset and powerup timing cycle including board configuration. Board FPGA...

  • Page 27: Power

    Arm supplies with the board. Arm supplies an external power supply unit that converts mains power to 12V 5A DC and connects to the 12V jack on the board. The unit accepts mains power in the range 110V AC to 240V AC.

  • Page 28: Serial Configuration Controller Interface

    The following figures show the read and write cycle timing of the SCC interface. Load Write Read address reset address data CB_CFGnRST CFGCLK CFGDATA CFGDATAOUT CFGLOAD CFGWnR Figure 2-7 Serial Configuration Controller interface read cycle timing 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-28 reserved. Non-Confidential...
  • Page 29 2.6 Serial Configuration Controller interface Load Write Write address reset address data and data CB_CFGnRST CFGCLK CFGDATA CFGLOAD CFGWnR Figure 2-8 Serial Configuration Controller interface write cycle timing 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-29 reserved. Non-Confidential...

  • Page 30: Mcc-Smc Interface

    SMBM_nE[4:1] functions as a Chip‑Select, providing four active‑low Chip‑Selects: • : No Chip Select. • : Chip‑Select 0. • : Chip‑Select 1. • : Chip‑Select 2. • : Chip‑Select 3. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-30 reserved. Non-Confidential...
  • Page 31 • The MCC-SMC interface supports only 32‑bit data read and write transfers. • To meet the timing requirements for address and data transfer, Arm recommends that you use the MCC‑SMC interface decoder in the file , provided by Arm. microToAhb.v 100765_0000_04_en Copyright ©...
  • Page 32 SMBM_A[24:16],SMBM_D[15:0] User bits generated LSB generated by FPGA design from by FPGA design Chip-Selects and user defined offsets Figure 2-11 Formation of 32-bit address in FPGA 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-32 reserved. Non-Confidential...
  • Page 33 0x05000000 address of in the FPGA user memory. The firmware sets SMBM_nE[4:1] to 0x0D000000 select Chip‑Select 1 which maps to the correct area of user memory. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-33 reserved. Non-Confidential...
  • Page 34 If the design does not implement the MCC‑SMC interface, you must set the variable FPGA_SMB to FALSE in the board file. See 3.5.2 config.txt generic board configuration file config.txt on page 3-64. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-34 reserved. Non-Confidential...

  • Page 35: Usb 2.0 And Ethernet Static Memory Interface

    OSC4 25MHZ MPS3 FPGA Prototyping Board Figure 2-13 MPS3 board USB 2.0 and Ethernet static memory interface Related information A.6 Combined Ethernet and dual USB-A connector on page Appx-A-84 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright ©...

  • Page 36: Video Hdlcd Interface

    2.9 Video HDLCD interface Video HDLCD interface The HDMI controller and HDMI connector on the MPS3 board enable you to implement an HDLCD interface. The external controller is a frame buffer device that can display up to 1920 × 1080p resolution at 60fps.

  • Page 37: Audio Codec Interface

    2.10 Audio codec interface An AACI audio codec on the MPS3 board provides a stereo audio interface with Line In, Line Out, and Microphone In. The AACI audio codec and the stereo audio interface enable you to implement an audio codec interface.

  • Page 38: Qvga Video Clcd Display

    2.11 QVGA video CLCD display 2.11 QVGA video CLCD display The MPS3 board provides QVGA, 320 × 240, CLCD video display. The CLCD video display system provides an on‑board CLCD display panel that includes: • An 8‑bit parallel bus between the FPGA and the display panel.

  • Page 39: On-Board User Components

    2.12 On-board user components 2.12 On-board user components The MPS3 board provides ten user LEDs, eight user switches, and two user push buttons. The LEDs, switches, and push buttons connect directly to the FPGA, meaning they can be used for debug.

  • Page 40: Interrupts

    2.13 Interrupts Interrupt signals from peripherals on the MPS3 board connect to external pins on the FPGA. The image that you implement connects the peripheral interrupts to systems in the FPGA. The following table shows the peripheral interrupt signals that connect to external pins on the FPGA.

  • Page 41: Fpga Ddr4 Memory Interface

    2.14 FPGA DDR4 memory interface The MPS3 board provides 4GB of DDR4 SODIMM and a DDR4 interface to the FPGA. The DDR4 controller and PHY interface uses the Xilinx Memory Interface Generator (MIG). The interface is 64‑bit and uses 10 byte lanes.

  • Page 42: User Non-Volatile Memory

    2.15 User non-volatile memory The MPS3 board provides on‑board user non‑volatile memory, 8MB QSPI flash (SST26VF064B), 16GB eMMC16G_M525, and a microSD card interface. A typical use of the QSPI flash is as boot memory. The microSD card or eMMC memory can be used for storing the Linux file system.

  • Page 43: Arduino Shield And Pmod Interfaces

    2.16 Arduino Shield and Pmod interfaces 2.16 Arduino Shield and Pmod interfaces The MPS3 board supports peripheral development by providing two Arduino Shield interfaces and, as an alternative, four Peripheral Module (Pmod) interfaces (Type 2A/3/4 support). Overview of Shield and Pmod interfaces The following figure shows the two Shield interfaces, and the four Pmod interfaces where the FPGA design implements an SPI controller that drives the 12‑bit ADC.
  • Page 44 The following figure shows the user‑links that select I/O voltage level and power inputs to the Shield and Pmod interfaces. The figure shows the user‑links that select 12V or 5V power, and 5V or 3V3 I/O references, for the Shields. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-44 reserved. Non-Confidential...
  • Page 45 5V/IOREF 1A maximum available for both Shields and all four Pmod interfaces. 0.5A maximum available for both Shields. 1.3 Location of components on the MPS3 board on page 1-15 for the location of the user‑links. Related information A.2 Arduino Shield connectors on page Appx-A-76 A.3 Peripheral Module (Pmod) connectors on page Appx-A-80...

  • Page 46: Fmc-Hpc Interface

    2 Hardware description 2.17 FMC-HPC interface 2.17 FMC-HPC interface The MPS3 board supports high speed, high pin count expansion using the FPGA Mezzanine Card (FMC) standard. Overview of the FMC-HPC interface The MPS3 board uses the FMC ‑ High Pin Count (FMC‑HPC) variant and provides: •...
  • Page 47 .ebf the MPS3 microSD card to run the AN533 blinky design on the MPS3 board. Example FMC board layout The following figure shows an MPS3 board with an FMC board that is fitted to the FMC‑HPC expansion connector. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-47 reserved.
  • Page 48 Arm Versatile Express boards that use the signals on the HDRY headers. Arm FMC expansion boards provide a daughterboard EEPROM and a Daughterboard Configuration Controller (DCC). The DCC and the MCC on the MPS3 board configure the Arm FMC expansion board using the configuration information in the daughterboard EEPROM.
  • Page 49 WHZ‑FMC XM‑107. Related information A.4 FMC-HPC connector on page Appx-A-82 A.5 FMC configuration connector on page Appx-A-83 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-49 reserved.

  • Page 50: System Debug

    2.18 System debug 2.18 System debug The MPS3 board provides several methods of performing debug. CoreSight debug ™ The following figure shows the MPS3 board debug and trace system. device JTAG 14 CMSIS-DAP Debug USB CMSIS-DAP F-JTAG controller SWD only...
  • Page 51 Arm CMSIS‑DAP controller. Setting up host software for the hub and serial ports The MPS3 board does not require software drivers for Windows 7 or later versions of Windows. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 2-51 reserved.
  • Page 52 2 Hardware description 2.18 System debug The following figure shows the USB devices that the MPS3 board adds when you connect a workstation to the USB debug connector. Figure 2-26 MPS3 board software drivers Related information A.1.1 20-pin IDC connector on page Appx-A-71 A.1.2 10-pin IDC connector on page Appx-A-72...

  • Page 53: Design Settings For Correct Board Operation With A Minimal Design

    2.19 Design settings for correct board operation with a minimal design 2.19 Design settings for correct board operation with a minimal design For correct operation with a minimal design, the MPS3 board requires a minimum amount of RTL in the FPGA, and certain variable settings in the file.

  • Page 54: Configuration

    Chapter 3 Configuration This chapter describes the powerup and configuration processes of the MPS3 board. It contains the following sections: • 3.1 Overview of the configuration system on page 3-55. • 3.2 Remote USB operation on page 3-57. • 3.3 Powerup and configuration sequence on page 3-58.

  • Page 55: Overview Of The Configuration System

    (USBMSD). The MCC: • Reads the FPGA image from the configuration microSD card and loads it into the FPGA. • Sets the board oscillator frequencies using values from the MPS3 board configuration application note file. .txt • If enabled, configures the FPGA Serial Configuration Control (SCC) registers using values from the file.
  • Page 56 3.5.2 config.txt generic board configuration file on page 3-64 3.5.3 Contents of the MB directory on page 3-64 3.5.4 Contents of the SOFTWARE directory on page 3-66 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-56 reserved. Non-Confidential...

  • Page 57: Remote Usb Operation

    Note The contents of the files have no effect. They can be empty files. Related information 1.3 Location of components on the MPS3 board on page 1-15 A.1.6 Debug USB 2.0 connector on page Appx-A-75 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-57 reserved.

  • Page 58: Powerup And Configuration Sequence

    The power push buttons and configuration files control the sequence of events of the board powerup and configuration process. The following figure shows the powerup and configuration sequence. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-58 reserved. Non-Confidential...
  • Page 59 Hardware reset or On/Off soft reset button button pressed briefly pressed? Hardware reset button pressed or ON/OFF soft reset button pressed for 2 seconds Figure 3-2 MPS3 board powerup and configuration sequence 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-59 reserved. Non-Confidential...
  • Page 60 3.5.2 config.txt generic board configuration file on page 3-64 3.5.3 Contents of the MB directory on page 3-64 3.5.4 Contents of the SOFTWARE directory on page 3-66 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-60 reserved. Non-Confidential...

  • Page 61: Reset Push Buttons

    3 Configuration 3.4 Reset push buttons Reset push buttons The MPS3 board provides push buttons that initiate reset and configuration. You can initiate a software reset, or a hardware reset, of the system. Software reset push buttons The MPS3 board provides two On/Off soft reset buttons, both labeled PBON. Pressing either one...
  • Page 62 If you then press one of the software reset buttons, the system performs a full configuration and enters the run state. Related information 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-62 reserved.

  • Page 63: Configuration Files

    Because the board microSD card is non-volatile memory, it is only necessary to load new configuration files if you change the system configuration. The microSD card that is supplied with the MPS3 board contains default configuration files.
  • Page 64 3.1 Overview of the configuration system on page 3-55 3.3 Powerup and configuration sequence on page 3-58 3.5.3 Contents of the MB directory The MPS3 board MB directory contains a configuration HBI subdirectory that matches the HBI code of the board. The HBI subdirectory contains: •...
  • Page 65 ;MB BIOS IMAGE [APPLICATION NOTE] ;Please select the required processor APPFILE: AN524\an524_v1.txt ;AN524 Cortex M33 SSE200 Subsystem for MPS3 The following example shows a typical MPS3 board configuration application note file. .txt BOARD: HBI0309 TITLE: AN524 application note configuration file...
  • Page 66 MCC from attempting to configure that peripheral. The following example shows a typical MPS3 board file. images.txt TITLE: Arm MPS3 FPGA prototyping board Images Configuration File [IMAGES] TOTALIMAGES: 1 ;Number of Images (Max : 32) IMAGE0ADDRESS: 0x05000000 ;Please select the required executable program...

  • Page 67: Mcc Command-Line Interface

    3 Configuration 3.6 MCC command-line interface MCC command-line interface The MPS3 board command‑line interface supports system command‑line input to the MCC. This section contains the following subsections: • 3.6.1 Overview of the MCC command-line interface on page 3-67. • 3.6.2 MCC main command menu on page 3-67.
  • Page 68 DEPOSIT address_data Write word to system memory address. EXAM address [nnnn] Examine system memory address at address. nnnn is number, in hex, of words to read. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights 3-68 reserved. Non-Confidential...
  • Page 69 MCC EEPROM menu (Reserved for factory use only) To switch to the EEPROM menu, enter EEPROM at the MCC main menu. The contents of the MPS3 board EEPROMs identify the specific board variant and might contain data to load to other devices on the board.

  • Page 70: Appendix A Signal Descriptions

    Appendix A Signal descriptions This appendix lists the signals at the interface connectors of the MPS3 board. It contains the following sections: • A.1 Debug connectors on page Appx-A-71. • A.2 Arduino Shield connectors on page Appx-A-76. • A.3 Peripheral Module (Pmod) connectors on page Appx-A-80.

  • Page 71: Debug Connectors

    Appx-A-75. A.1.1 20-pin IDC connector The MPS3 board provides one 1V8 20‑pin IDC connector that supports P‑JTAG processor debug to enable connection of DSTREAM, or a compatible third‑party debugger. The connector also supports Serial Wire Debug (SWD). The 20‑pin IDC connector connects to general‑purpose pins on the FPGA. The availability of P‑JTAG or SWD depends on the design that you implement in the FPGA.
  • Page 72 1.3 Location of components on the MPS3 board on page 1-15 A.1.2 10-pin IDC connector The MPS3 board provides one 1V8 10‑pin IDC connector that supports P‑JTAG processor debug to enable connection of DSTREAM or a compatible third‑party debugger. The connector also supports Serial Wire Debug (SWD).
  • Page 73 A.1.4 38-pin MICTOR connector The MPS3 board provides one 1V8 38‑pin MICTOR connector. The connector supports P‑JTAG processor debug to enable connection of DSTREAM, or a compatible third‑party debugger. The connector also supports Serial Wire Debug (SWD) and 16‑bit trace.
  • Page 74 14-pin F-JTAG ILA connector The MPS3 board provides one 3V3 14‑pin F‑JTAG ILA connector that supports FPGA debug. It enables you to connect an ILA device, such as SignalTap II, to a hard FPGA JTAG chain in the FPGA and debug your design.
  • Page 75 A.1.6 Debug USB 2.0 connector The MPS3 board provides one USB 2.0 connector that supports configuration file editing in the microSD, UART access to the FPGA, and CMSIS‑DAP FPGA debug using SWD only. The following figure shows the USB type B connector, J8.

  • Page 76: Arduino Shield Connectors

    Interface Pmod0/1 shares some signals with Shield 0 interface, and Pmod2/3 shares some signals with Shield 1 interface. Caution The MPS3 board supports simultaneous use of Pmod and Shield expansion but you must take care when driving the shared signals. Shield 0 and Shield 1 interface connectors The following figure shows a combined diagram of the Arduino Shield 0 and Arduino Shield 1 interfaces on the MPS3 board.
  • Page 77 • FPGA pin SH1_IO17 connects to Shield pin SH1_IO15. Arm recommends that you set FPGA pins SH[1:0]_IO[17:16] to high impedance to prevent any possibility of interference with connector pins SH[1:0]_IO[15:14]. Connector J30 provides Shield 0 I/O[7:0] and connector J36 provides Shield 1 I/O[7:0]. The following table shows the pin mapping for connectors J30 and J36.
  • Page 78 Connector J27 provides a subset of the Shield 0 signals and connector J37 provides a subset of the Shield 1 signals. The following table shows the pin mapping for connectors J27 and J37. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-A-78 reserved.
  • Page 79 SH0/SH1__IO12 SH0/SH1_IO13 SH0/SH1_IO11 SHO/SH1_nRST Related information 2.16 Arduino Shield and Pmod interfaces on page 2-43 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-A-79 reserved. Non-Confidential...

  • Page 80: Peripheral Module (Pmod) Connectors

    A.3 Peripheral Module (Pmod) connectors Peripheral Module (Pmod) connectors The Pmod connectors on the MPS3 board provide digital I/O expansion capability, an alternative to the Shield interfaces. The four Pmod connectors enable fitting of TYPE 2A (J24/J34) and TYPE 1 (J28/J38) boards.
  • Page 81 SH0_5V_IO1 10 SH1_5V_IO14 SH1_REF SH1_REF Related information 2.16 Arduino Shield and Pmod interfaces on page 2-43 1.3 Location of components on the MPS3 board on page 1-15 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-A-81 reserved. Non-Confidential...

  • Page 82: Fmc-Hpc Connector

    A Signal descriptions A.4 FMC-HPC connector FMC-HPC connector The MPS3 board provides a 400‑way Samtec SEARAY connector to support the FPGA Mezzanine Card standard, high pin count variant, FMC‑HPC. The following figure shows the FMC‑HPC connector, J9. Figure A-9 FMC-HPC connector The pin mapping of the FMC‑HPC connector conforms to the FPGA Mezzanine Card (FMC) Standard...

  • Page 83: Fmc Configuration Connector

    A.5 FMC configuration connector FMC configuration connector The MPS3 board provides a custom 14‑pin connector to enable configuration of Arm FMC boards. The FMC configuration connector is reserved for Arm FMC boards only. The following figure shows the FMC‑HPC configuration connector, J61.

  • Page 84: Combined Ethernet And Dual Usb-A Connector

    A.6 Combined Ethernet and dual USB-A connector Combined Ethernet and dual USB-A connector The MPS3 board provides a combined Ethernet and dual USB-A connector that connects to the Ethernet 10/100 controller and to the USB 2.0 controller. The following figure shows the combined Ethernet and dual USB-A connector, J2.

  • Page 85: Hdmi Type A Female Connector

    A Signal descriptions A.7 HDMI Type A female connector HDMI Type A female connector The female HDMI connector on the MPS3 board provides digital video and digital audio to external displays. The following figure shows the HDMI connector, J3. Figure A-12 HDMI connector...

  • Page 86: Audio Connectors, Stacked Stereo Jacks

    A.8 Audio connectors, stacked stereo jacks Audio connectors, stacked stereo jacks The MPS3 board provides three stacked 3.5mm stereo jack connectors that connect to a stereo audio codec. The connectors provide line‑level stereo input, line‑level stereo output, and microphone‑level stereo input.

  • Page 87: Power Connector

    12V power connector The MPS3 board provides a Thru‑hole DC power jack for connecting external power to the board. Connect the external mains power supply unit, that Arm supplies with the MPS3 board, to the power jack. Alternatively, you can connect an external 12V 5A, +/-10%, power supply to the power jack.

  • Page 88: Appendix B Specifications

    Appendix B Specifications This appendix contains electrical specifications of the MPS3 board. It contains the following section: • B.1 Available power for expansion boards on page Appx-B-89. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-B-88 reserved.

  • Page 89: Available Power For Expansion Boards

    The MPS3 board supplies power to the expansion boards through the expansion connectors. FMC-HPC power The MPS3 board supplies power, through the FMC‑HPC connector, to a fitted FMC‑HPC board. The following table shows the maximum current that the board can supply from each power rail.

  • Page 90: Appendix C Revisions

    Appendix C Revisions This appendix describes the technical changes between released issues of this book. It contains the following section: • C.1 Revisions on page Appx-C-91. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-C-90 reserved. Non-Confidential...
  • Page 91 No changes, first release. - Table C-2 Differences between issue 100765_0000_00 and issue 100765_0000_01 Change Location Affects Removed mention of JTAG mode from description of MPS3 All versions 2.18 System debug on page 2-50 DAP-Link interface. A.1.6 Debug USB 2.0 connector on page Appx-A-75 Removed statement that availability of P-JTAG or SWD A.1.5 14-pin F-JTAG ILA connector on page Appx-A-74...
  • Page 92 Additional reading on page 8 All versions image for the MPS3 Prototyping Board to Additional Reading list. Conformance Notices on page 3 All versions Updated CE Conformance Notice. 100765_0000_04_en Copyright © 2017–2020 Arm Limited or its affiliates. All rights Appx-C-92 reserved. Non-Confidential...

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