Control Registers; Uart3 Ch.n Clock Control Register; Uart3 Ch.n Mode Register - Epson S1C31D50 Technical Manual

13.9 Control Registers

UART3 Ch.n Clock Control Register

Register name Bit
UART3_nCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the UART3 operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the UART3 operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the UART3.
UART3_nCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The UART3_nCLK register settings can be altered only when the UART3_nCTL.MODEN bit = 0.

UART3 Ch.n Mode Register

Register name Bit
UART3_nMOD 15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 13.9.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/8
1/4
1/2
1/1
Bit name Initial
0x0
PECAR 0
CAREN 0
BRDIV 0
INVRX 0
INVTX 0
– 0
PUEN 0
OUTMD 0
IRMD 0
CHLN 0
PREN 0
PRMD 0
STPB 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
UART3_nCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
13 UART (UART3)
Remarks
0x3
EXOSC
1/1
Remarks
13-11