NXP Semiconductors LPC29 Series User Manual page 429

NXP Semiconductors
The PWM_sync and trans_enable_in of PWM 0 are connected to the 4th match output of
MSCSS timer 0 to start the PWM after a pre-programmed delay. This sync signal is
cascaded through all PWMs, allowing a programmable delay offset between subsequent
PWMs. The sync delay of each PWM can be programmed synchronously or with a
different phase for spreading the power load.
The match outputs of MSCSS timer 1 (PWM control) are connected to the corresponding
carrier inputs of the PWM modules. The carrier signal is modulated with the PWM-
generated waveforms.
The pause input of MSCSS timer 1 (PWM Control) is connected to an external input pin.
Generation of the carrier signal is stopped by asserting the pause of this timer.
The pause input of MSCSS timer 0 (ADC Control) is connected to a 'NOR' of the
PWM_sync outputs (start 2 input on the ADCs). If the pause feature of this timer is
enabled the timer only counts when one of the PWM_sync outputs is active HIGH. This
feature can be used to start the ADC once every x PWM cycles, where x corresponds to
the value in the match register of the timer. In this case the start 3 input of the ADC should
be enabled (start on match output of MSCSS timer 0).
The signals connected to the capture inputs of the timers (both MSCSS timer 0 and
MSCSS timer 1) are intended for debugging.
UM10316
User manual
Chapter 24: LPC29xx Modulation and Sampling Control Subsystem
Rev. 3 — 19 October 2010
UM10316
© NXP B.V. 2010. All rights reserved.
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