Operation As Input Signal High-/Low-Level Width Measurement - Renesas 78K0R/KE3 User Manual

6.7.5 Operation as input signal high-/low-level width measurement

By starting counting at one edge of TI0k and capturing the number of counts at another edge, the signal width
(high-level width/low-level width) of TI0k can be measured. The signal width of TI0k can be calculated by the
following expression.
Signal width of TI0k input = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDR0n + 1))
Caution The TI0k pin input is sampled using the operating clock selected with the CKS0n bit of the
TMR0n register, so an error equal to the number of operating clocks occurs.
TCR0n operates as an up counter in the capture & one-count mode.
When the channel start trigger (TS0n) is set to 1, TE0n is set to 1 and the TI0k pin start edge detection wait status
is set.
When the TI0k start valid edge (rising edge of TI0k when the high-level width is to be measured) is detected, the
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TI0k when the
high-level width is to be measured) is detected later, the count value is transferred to TDR0n and, at the same time,
INTTM0n is output. If the counter overflows at this time, the OVF bit of the TSR0n register is set to 1. If the counter
does not overflow, the OVF bit is cleared. TCR0n stops at the value "value transferred to TDR0n + 1", and the TI0k
pin start edge detection wait status is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSR0n register is set to 1. However, the OVF bit is configured as an integral flag, and the correct interval
value cannot be measured if an overflow occurs more than once.
Whether the high-level width or low-level width of the TI0k pin is to be measured can be selected by using the
CIS0n1 and CIS0n0 bits of the TMR0n register.
Because this function is used to measure the signal width of the TI0k pin input, TS0n cannot be set to 1 while TE0n
is 1.
CIS0n1, CIS0n0 of TMR0n = 10B: Low-level width is measured.
CIS0n1, CIS0n0 of TMR0n = 11B: High-level width is measured.
Figure 6-51. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
CK01
Operation clock
CK00
TI0k pin
detection
Remark n = 0 to 7, k = 0 to 6
236
CHAPTER 6 TIMER ARRAY UNIT
Edge
User's Manual U17854EJ9V0UD
Timer counter
(TCR0n)
Data register
(TDR0n)
Interrupt
Interrupt signal
controller
(INTTM0n)