Clock Forwarding - Xilinx SelectIO 7 Series User Manual

Chapter 2: SelectIO Logic Resources
OPPOSITE_EDGE Mode
In OPPOSITE_EDGE mode, both the edges of the clock (CLK) are used to capture the data
from the FPGA logic at twice the throughput. This structure is similar to the Virtex-6 FPGA
implementation. Both outputs are presented to the data input or 3-state control input of the
IOB. The timing diagram of the output DDR using the OPPOSITE_EDGE mode is shown
in
X-Ref Target - Figure 2-18
SAME_EDGE Mode
In SAME_EDGE mode, data can be presented to the IOB on the same clock edge.
Presenting the data to the IOB on the same clock edge avoids setup time violations and
allows the user to perform higher DDR frequency with minimal register to register delay,
as opposed to using the CLB registers.
DDR using the SAME_EDGE mode.
X-Ref Target - Figure 2-19

Clock Forwarding

Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to
forward clocks from the FPGA logic to the output pins.
128
Send Feedback
Figure 2-18.
CLK
OCE
D1 D1A
D2
OQ
Figure 2-18: Output DDR Timing in OPPOSITE_EDGE Mode
CLK
OCE
D1 D1A
D2 D2A
OQ
Figure 2-19: Output DDR Timing in SAME_EDGE Mode
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D1B D1C
D2A D2B
D1A D2A D1B D2B D1C D2C D1D
Figure 2-19 shows the timing diagram of the output
D1B D1C
D2B D2C
D1A D2A D1B D2B D1C D2C D1D
7 Series FPGAs SelectIO Resources User Guide
D1D
D2C D2D
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D1D
D2D
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UG471 (v1.10) May 8, 2018