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Astronics OMNIBUS II NI PXIe User Manual

Interface card to avionics databuses
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  • Page 1 Astronics Ballard Technology/National Instruments LV-222-511-442 Manual Get Pricing & Availability at ApexWaves.com Call Today: 1-800-915-6216 Email: sales@apexwaves.com https://www.apexwaves.com/modular-systems/national-instruments/pxi-avionics-multiprotocol-interface-modules/LV-222-511-442...
  • Page 2 OMNIBUS II NI PXIe USER MANUAL Interface Card To Avionics Databuses February 1, 2018 Rev. C.1 Copyright  2018 Ballard Technology, Inc. Astronics Ballard Technology www.astronics.com MA223-20180201 Rev. C.1...
  • Page 4 COPYRIGHT NOTICE  Copyright 2018 by Ballard Technology, Inc.—hereafter referred to as Ballard. Ballard’s permission to copy and distribute this manual is for the purchaser's private use only and is conditioned upon the purchaser's use and application with the OmniBus II hardware that was shipped with this manual.
  • Page 5 PRODUCT CERTIFICATION RESPONSIBLE PARTY Astronics Ballard Technology, Inc. 11400 Airport Road, Suite 201 Everett, WA 98204, USA Web: www.astronics.com PRODUCTS OmniBus II PXIe versions LV-222-xxx-xxx (NI P/N 784xxx-xx) (where x is any numeric character or blank). This device complies with Part 15 of the FCC Rules. Operation is subject to the following two...

  • Page 6: Table Of Contents

    4.5.2 Shunt Input Considerations ..............4-10 4.5.3 Shunt Outputs ..................4-10 4.5.4 Shunt Output Considerations .............. 4-10 4.5.5 Shunt Discrete Input/Output Usage ............. 4-12 5. OMNIBUS II PXIE SPECIFIC FEATURES ..........5-1 5.1 Clock Switch (CLK SEL) ................... 5-1 OmniBus II NI PXIe User Manual...
  • Page 7 A.2 Transformer versus Direct Coupling ..............A-1 APPENDIX B: SPECIFICATIONS ..............B-1 B.1 General ....................... B-1 B.2 Interfaces (Model Dependent) ................B-1 B.3 Environmental/Physical ..................B-3 APPENDIX C: ERRATA SHEET ..............C-1 APPENDIX D: REVISION HISTORY ............. D-1 OmniBus II NI PXIe User Manual...
  • Page 8 Figure 5.1—PXIe Onboard Clock Switch ..............5-1 Figure 5.2—PXIe Chassis Slot Glyphs ..............5-5 Figure A.1—Transformer Coupling to a Dual-Redundant Databus ......A-2 Figure A.2—Direct Connection to a Dual-Redundant Databus....... A-3 Figure B.1—Dimensions of OmniBus II PXIe Card ..........B-3 OmniBus II NI PXIe User Manual...
  • Page 9 Table 7.4—Wiring Chart for 16036 Cable Assembly (See next page for “*” note) . 7-5 Table 7.5—MIL-STD-1553 Cable Assembly Configurations ........7-6 Table 7.6—Twinax Wiring on MIL-STD-1553 Cable Assemblies ......7-6 Table 7.7—D-sub Connector Pinout for Cable Assemblies 16037 and 16039 ..7-7 OmniBus II NI PXIe User Manual...

  • Page 10: Introduction

    1. INTRODUCTION This manual is the user guide for PXI™ Express (PXIe) models of Astronics ® ® Ballard Technology ’s (Ballard) OmniBus II family of products. Throughout this manual any reference to the PXIe card applies to the OmniBus II PXIe card, and references to OmniBus and OmniBus II apply generically to all the products in the designated family.

  • Page 11: Figure 1.2-The Two-Core Architecture Of Omnibus Ii Pxie Card

    Avionics Databuses Databuses Protocol Protocol Module Module Core A Core B SDRAM SDRAM FPGA FPGA Flash Flash 1:2 PCIe Switch 1 Lane PCIe PCIe Connector Figure 1.2—The Two-Core Architecture of OmniBus II PXIe Card OmniBus II NI PXIe User Manual...

  • Page 12: Omnibus Ii Configurations

    Core A position, and the third group is the part number of the module in the Core B position. You can find a more detailed description of the individual part numbers in Chapter 6 OmniBus II NI PXIe User Manual...

  • Page 13: Avionics Databus Protocols

    These and other standards are not limited to use in aircraft. They are used in many other military and industrial applications such as surface and space vehi- cles, process control, nuclear research, and oil exploration. OmniBus II NI PXIe User Manual...

  • Page 14: Other Documentation

    1.7 Mean Time Between Failure Product PN Analyzed Published MTBFs PXIe 222-442-442 PXIe (all configurations): 2.8+ million hours (Calculated, Telcordia SR-332 Issue 3, Ground Benign, 25°C, 60% CL) OmniBus II NI PXIe User Manual...
  • Page 15 INTRODUCTION This page intentionally blank. OmniBus II NI PXIe User Manual...

  • Page 16: Installation

    With the injector handle in the down position, insert the card into an empty chassis slot marked with one of the following PXIe Chassis Glyphs: * replaced with chassis slot number Figure 2.1—PXIe Compatible Chassis Glyphs OmniBus II NI PXIe User Manual...

  • Page 17: Step 2: Install The Driver Software

    Running the test sequence verifies both the device hardware and the interface between the OmniBus II NI PXIe User Manual...

  • Page 18: Step 4: Connect To Databus(S) I/O

    This program is installed automatically with the Avionics Instrument Driver library. It can be found at the start menu: Astronics Ballard Technology > LabVIEW Instrument Driver > BTITST32 Note: You can use the Windows test program at any time to determine or reassign the card number.
  • Page 19 INSTALLATION This page intentionally blank. OmniBus II NI PXIe User Manual...

  • Page 20: Operation

    The Strip View graphically illustrates the history of the selected data values. You can also enter data and view it as virtual instruments (knobs, dials, gauges, etc.). The user creates this data or the user automatically OmniBus II NI PXIe User Manual...

  • Page 21: User-Developed Software

    Avionics Instrument Driver VI and the instructions on programming for the OB2 in context-sensitive VI help for each protocol as well as well-documented and extensive example VIs. Contact Customer Support (see Section 1.5) for additional information. OmniBus II NI PXIe User Manual...

  • Page 22: Omnibus Ii Features

    PBIT, IBIT verifies a range of internal hardware and host communication. Initiated test resets the card and is not intended to be performed while the card is configured or running. OmniBus II NI PXIe User Manual...

  • Page 23: Continuous Built-In Test (Cbit)

    OB2 and the external reference. Use of the drift control functionality can help increase synchronization between the OB2 core timer and the external reference during the gap between timing samples. OmniBus II NI PXIe User Manual...

  • Page 24: Core Timer

    This system timer is also the source for the IRIG interface when configured as a master. The system timer has a resolution down to one ns, but a precision of 10 ns. You cannot change the resolution from one ns, however, OmniBus II NI PXIe User Manual...
  • Page 25 BTICard_CardReset does not reset the core timer. A user must call BTICard_TSMReset to reset the TSM configuration and timer. This prevents a call to BTICard_CardReset on one core from interfering with the time-stamps used by a different core on the same device. OmniBus II NI PXIe User Manual...

  • Page 26: Irig

    Output mark amplitude (V 2.5 V to 3.5 V pk-pk Output space amplitude (V 0.75 V to 1.25 V pk-pk 45 Ω Max output resistive load Table 4.4—Electrical Characteristics of the AM IRIG Signals OmniBus II NI PXIe User Manual...

  • Page 27: Pps

    Input impedance (min) Input voltage (max) -7.5 V to 12.5 V Input level threshold API Controlled (0-5 V) 0-5 V Output level Output drive capability 20 mA Table 4.7—Electrical Characteristics of the PPS Signal OmniBus II NI PXIe User Manual...

  • Page 28: 10Mhz

    TTL level discretes per core that can be used as either inputs or outputs. Each discrete output line has a 5-V TTL driver that can source or sink up to 8 mA and has an individual tristate control; the discrete input receiver is a 5 V OmniBus II NI PXIe User Manual...

  • Page 29: Table 4.11-Hardware Versus Software Designation Of Core Discretes

    CDIO (e.g., CDIO2). Trigger/Sync Name dionum Usage CDIO0 Trigger A CDIO1 Trigger B CDIO2 Trigger C CDIO3 CDIO4 Sync A CDIO5 Sync B CDIO6 Sync C CDIO7 Table 4.11—Hardware Versus Software Designation of Core Discretes OmniBus II NI PXIe User Manual...

  • Page 30: 1553 Avionics Discretes

    This results in a 3.25-V switching voltage. 9 kΩ 9 kΩ 5 kΩ 3.25V 5 kΩ Figure 4.2—OmniBus II Discrete Shunt Input Circuit OmniBus II NI PXIe User Manual...

  • Page 31: Shunt Input Considerations

    If a user attempts to sink too much current through an output discrete circuit, the output will begin current limiting. You can accomplish this by increasing the resistance through the output, 4-10 OmniBus II NI PXIe User Manual...
  • Page 32 However, the user can wire multiple outputs in parallel to increase the maximum current sinking capability. Power-On: After power-on, the 1553 shunt discrete I/O is in its default state with outputs open (high impedance). OmniBus II NI PXIe User Manual 4-11...

  • Page 33: Shunt Discrete Input/Output Usage

    Avionics DIO 10 BUS13P ADIO11 Avionics DIO 11 BUS13N ADIO12 Avionics DIO 12 BUS14P ADIO13 Avionics DIO 13 BUS14N ADIO14 Avionics DIO 14 BUS15P ADIO15 Avionics DIO 15 BUS15N Table 4.12—1553 Discrete I/O Designations 4-12 OmniBus II NI PXIe User Manual...

  • Page 34: Omnibus Ii Pxie Specific Features

    Table 5.1. You can also monitor these signals using BTICard_ExtDIOMonConfig with banknum and rise_edge/fall_edge bits as per Table 5.1. For more information on these functions, refer to the API manuals (e.g., MIL-STD-1553 Programming Manual for BTIDriver-Compliant Devices). OmniBus II NI PXIe User Manual...

  • Page 35: Table 5.1-Pxie Trigger Signals

    50% duty-cycle on this trigger. The PXIe_DSTARC 10MHz output can be enabled by calling BTICard_ExtDIOEnWr on dionum 44 with dioen set to TRUE, and disable it by calling BTICard_ExtDIOEnWr on dionum 44 with dioen set to FALSE. Note that this signal cannot be tristated. OmniBus II NI PXIe User Manual...

  • Page 36: Protocol Sync And Trigger Support

    (A-C). To use this feature, pass the respective parameter found in Table 5.4 to the pinpolarity argument of the TriggerDefine function (e.g. BTI1553_BCTriggerDefine). OmniBus II NI PXIe User Manual...

  • Page 37: Pxie Status

    1 = Onboard 100 MHz Oscillator PXITYPE_TRIGVERS Version of the BTI PXIe trigger engine PXITYPE_OUTEN Bitmask of output enables for dionums 33 to 48 (Refer to Section 5.3 for more information) Table 5.5—PXIe Status Parameters OmniBus II NI PXIe User Manual...

  • Page 38: Chassis Slot Glyph

    Glyphs from Figure 5.2. Note: While the PXIe card will operate normally in the System Timing Slot, it will not function as a System Timing Module. * replaced with chassis slot number Figure 5.2—PXIe Chassis Slot Glyphs OmniBus II NI PXIe User Manual...
  • Page 39 OMNIBUS II PXIE SPECIFIC FEATURES This page intentionally blank OmniBus II NI PXIe User Manual...

  • Page 40: Module Configurations

    RT response time. Advanced features include multi-terminal simulation (up to 32) with concurrent monitoring and protocol error injection (word, gap, and message errors). Level P MIL-STD-1553 modules provide variable transmit amplitude and zero-crossing distortion. OmniBus II NI PXIe User Manual...

  • Page 41: Software-Selectable Bus Termination

    6.2.3 Variable Transmit Amplitude For OB2 MIL-STD-1553 level P channels, the amplitude of the transmitted databus signal can be varied under software control. Using BTI1553_Param- AmplitudeConfig, the OB2 has extended functionality from the OmniBus OmniBus II NI PXIe User Manual...

  • Page 42: Zero-Crossing Distortion

    Note: If a zero crossing is delayed, such that the subsequent zero crossing occurs less than 400 ns later, the timing of the subsequent zero crossing may also be distorted. OmniBus II NI PXIe User Manual...

  • Page 43: Arinc 429 Modules

    The amplitude, offset and null voltages are controlled by specifying the high, null, and low voltages of the differential waveform. These parameters can be individually set in software for each channel as shown in the following Table 6.7. OmniBus II NI PXIe User Manual...

  • Page 44: Configurable Frequency

    ARINC 429 modules with output state functionality have the capability under software control to: • Open either output leg of a transmit channel • Short either output leg of a transmit channel to ground OmniBus II NI PXIe User Manual...

  • Page 45: Part Number Cross Reference

    16037 LFH to (4) PL75 MIL-STD- 1553 stub connections and (1) DB25 connector. Two channels of dual-redundant MIL-STD- 1553 (Bus A and Bus B) on the PL75’s with IRIG and core discretes d-sub connector. OmniBus II NI PXIe User Manual...
  • Page 46 784803-01 784808-01 LV-222-442-442 784804-01 784808-01 784808-01 LV-222-510-000 784796-01 784807-01 LV-222-511-000 784797-01 784807-01 LV-222-511-511 784798-01 784807-01 784807-01 LV-222-550-000 784799-01 784807-01 LV-222-555-000 784800-01 784807-01 LV-222-555-555 784801-01 784807-01 784807-01 LV-222-511-442 784805-01 784807-01 784808-01 LV-222-555-442 784806-01 784807-01 784808-01 OmniBus II NI PXIe User Manual...
  • Page 47 MODULE CONFIGURATIONS This page intentionally blank. OmniBus II NI PXIe User Manual...

  • Page 48: Connector Pinouts

    The LFH is a high-density connector about the size of a 15-pin D-subminiature connector. For proper clearance from adjacent connectors, the overall length of each LFH connector (including any backshell molding) must not exceed 1.64 inches. OmniBus II NI PXIe User Manual...

  • Page 49: General Pinout

    **NOTE: The IRIG pins on cores A and B share common resources. This means that only one can be used at a time. There are additional IRIG configurations that are pin and core specific. Please refer to Table 4.6, Table 4.8, and Table 4.10 for details. OmniBus II NI PXIe User Manual...

  • Page 50: Module-Specific Wiring

    Avionics DIO 11 P3-19 BUS13N ADIO12 Avionics DIO 12 P3-9 BUS14P ADIO13 Avionics DIO 13 P3-20 BUS14N ADIO14 Avionics DIO 14 P3-10 BUS15P ADIO15 Avionics DIO 15 P3-21 BUS15N Table 7.2—Pinouts for MIL-STD-1553 Modules OmniBus II NI PXIe User Manual...

  • Page 51: Arinc 429

    CH13N – P3-19 BUS13N ϯ CH14P P3-9 BUS14P CH14 ϯ ϯ CH30 CH14N – P3-20 BUS14N ϯ CH15P P3-10 BUS15P CH15 ϯ ϯ CH31 CH15N – P3-21 BUS15N Table 7.3—Pinouts for ARINC 429 modules OmniBus II NI PXIe User Manual...

  • Page 52: Standard Cables

    BUS7N BUS15N CDIO0 CDIO3 IRIG* IRIG*/10MHZ CDIO5 CDIO6 CDIO4 CDIO7 NC/5V NC/5V CDIO1 CDIO2 CGND CGND Braids connected shell to shell Table 7.4—Wiring Chart for 16036 Cable Assembly (See next page for “*” note) OmniBus II NI PXIe User Manual...

  • Page 53: Mil-Std-1553 Cable Assemblies

    BUS3N CH1AX Center BUS8P BUS A CH1AXR Outer BUS8N CH1BX Center BUS11P BUS B CH1BXR Outer BUS11N Braids connected between the LFH shell and the PL-75 shell Table 7.6—Twinax Wiring on MIL-STD-1553 Cable Assemblies OmniBus II NI PXIe User Manual...

  • Page 54: Table 7.7-D-Sub Connector Pinout For Cable Assemblies 16037 And 16039

    From Pair Name LFH Pin DB25S Pin CDIO0 CDIO1 CDIO2 CDIO3 CDIO7 CDIO4 CDIO5 CDIO6 IRIG IRIG/10MHZ NC/5V CGND Braids connected shell to shell Table 7.7—D-sub Connector Pinout for Cable Assemblies 16037 and 16039 OmniBus II NI PXIe User Manual...
  • Page 55 CONNECTOR PINOUTS This page intentionally blank. OmniBus II NI PXIe User Manual...

  • Page 56: Appendix A: Coupling And Termination

    The direct-coupled terminal has a higher turns ratio and has isolation resistors that you can connect directly to the main databus. Keep direct-coupled stubs should as short as possible (see Figure A.2—Direct Connection to a Dual-Redundant Databus). OmniBus II NI PXIe User Manual...

  • Page 57: Figure A.1-Transformer Coupling To A Dual-Redundant Databus

    COUPLING AND TERMINATION Figure A.1—Transformer Coupling to a Dual-Redundant Databus OmniBus II NI PXIe User Manual...

  • Page 58: Figure A.2-Direct Connection To A Dual-Redundant Databus

    T EE ADAPT ERS BT P/N 17002 Bus A 78Ω 78Ω S T UB S T UB UNIT UNDER T ES T T RANS CEIVER T RANS CEIVER T erminal Figure A.2—Direct Connection to a Dual-Redundant Databus OmniBus II NI PXIe User Manual...
  • Page 59 COUPLING AND TERMINATION This page intentionally blank. OmniBus II NI PXIe User Manual...

  • Page 60: Appendix B: Specifications

    APPENDIX B: SPECIFICATIONS B.1 General • 2 Core I/O sites • 8 bidirectional TTL discrete I/O per core • 2 user controlled LED indicators per core • 64 MB memory per core (ECC) • RoHS B.2 Interfaces (Model Dependent) MIL-STD-1553 •...
  • Page 61 SPECIFICATIONS ARINC 429 (Advanced Module) All features of the standard module plus: • Control of each bus leg as open, ground, or normal • Parametric waveform control (0-40 V differential pk-pk) Advanced Timing (IRIG) • 64-bit hardware time-tag (1 ns resolution) •...

  • Page 62: Environmental/Physical

    SPECIFICATIONS B.3 Environmental/Physical Physical • Size: PXIe: Standard 3U (100 x 160 mm) • Weight: 3.5 lbs. (1.6 kg) Physical Dimensions See the following diagrams for the dimensions of the OB2 PXIe Card. Figure B.1—Dimensions of OmniBus II PXIe Card Environmental •...
  • Page 63 SPECIFICATIONS Power PXIe ARINC 429 (Model 222-442-442) Typical Maximum Core A Idle Active Active Idle Active Active Idle Idle Active Idle Idle Active Core B 5.6 W 5.7 W 5.7 W 5.6 W 5.7 W 5.7 W 3.3V 3.8 W 5.1 W 6.3 W 3.8 W...

  • Page 64: Appendix C: Errata Sheet

    APPENDIX C: ERRATA SHEET This errata sheet describes the known functional problems and any deviations from the technical specifications known at the release date of this manual. Deviations Applies to: Errata Section Description Status Hardware Software Number Revision Revision Standard ARINC 429 Modules (42x/44x) present a low impedance on the 429 databus when...
  • Page 65 ERRATA SHEET This page intentionally blank. OmniBus II PCIe/PXIe User Manual...

  • Page 66: Appendix D: Revision History

    Appendix C Errata Sheet with information regarding performance of 42x/44x Modules Rev B and earlier. Rev. C.1 Date: February 1, 2018 Corrected cable cross reference errors in both tables in Section 6.4. OmniBus II NI PXIe User Manual...
  • Page 67 REVISION HISTORY This page intentionally blank. OmniBus II NI PXIe User Manual...

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