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Holtek HT66F002 Manual

Cost-effective a/d flash mcu with eeprom
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Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Revision: V1.71
Date: April 11, 2017

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  • Page 1 Cost-Effective A/D Flash MCU with EEPROM HT66F002/HT66F0025/HT66F003/HT66F004 Revision: V1.71 Date: April 11, 2017...

  • Page 2: Table Of Contents

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Table of Contents Features ......................6 CPU Features ......................... 6 Peripheral Features ......................... 6 General Description ..................7 Selection Table ....................7 Block Diagram ....................8 Pin Assignment ....................8 Pin Description ....................10 Absolute Maximum Ratings ................
  • Page 3 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM EEPROM Data Memory .................. 32 EEPROM Data Memory Structure ..................32 EEPROM Registers ......................33 Reading Data from the EEPROM ..................34 Writing Data to the EEPROM ....................35 Write Protection ........................35 EEPROM Interrupt ........................
  • Page 4 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Timer Modules – TM ..................66 Introduction ........................... 66 TM Operation ........................66 TM Clock Source ........................66 TM Interrupts ......................... 67 TM External Pins ........................67 TM Input/Output Pin Control Register ................... 67 Programming Considerations ....................
  • Page 5 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Interrupts ...................... 108 Interrupt Registers ....................... 108 Interrupt Operation .......................114 External Interrupt ........................116 Multi-function Interrupt ......................116 A/D Converter Interrupt ......................116 Time Base Interrupts ......................117 EEPROM Interrupt .......................118 TM Interrupts ........................118 Interrupt Wake-up Function ....................118 Programming Considerations ....................118...

  • Page 6: Features

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Features CPU Features • Operating Voltage = 8MHz: 2.2V~5.5V ♦ SYS • Up to 0.5μs instruction cycle with 8MHz system clock at V • Power down and wake-up functions to reduce power consumption • Two Oscillators Internal RC -- HIRC ♦ Internal 32kHz -- LIRC ♦ • Fully intergrated internal 8MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 4-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 1K×14/2K×15...

  • Page 7: General Description

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM General Description The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter function. Multiple and extremely flexible Timer Modules provide timing, pulse generation, capture input, compare match output, single pulse output and PWM generation functions. Protective features such as an internal Watchdog Timer and Low Voltage Reset coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation.

  • Page 8: Block Diagram

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Block Diagram Watchdog Flash/EEPROM Low Voltage Timer Programming Circuitry Reset Reset Circuit 8-bit EEPROM Flash Time RISC Data Program Bases Memory Memory Interrupt Core Controller Internal RC Oscillators RAM Data Timer Memory Modules...
  • Page 9 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM VDD/AVDD VSS/AVSS PA6/STP0I/[STCK0] PA0/[STP0]/[STP0I]/AN0/ICPDA PA5/INT/STP0B/AN3 PA1/[STP0B]/AN1/VREF PA2/[INT]/STP0/AN2/VREFO PA7/[INT]/STCK0/RES/ICPCK PA3/[INT] OCDSCK OCDSDA HT66V002/HT66V0025 16 NSOP-A PB2/PTP1B PB3/[PTP1] PB4/[PTP1B] PB1/[PTCK1]/STP0B PB0/[PTP1I]/VREFO PB5/PTP1 PA3/INT/STCK0/AN3 PA4/[INT]/PTCK1/STP0 PA2/[INT]/[STCK0]/AN2/OCDSCK/ICPCK PA5/[INT]/PTP1I PA1/AN1/VREF PA6/[PTCK1]/STP0I/[STP0] PA0/[STP0I]/AN0/OCDSDA/ICPDA PA7/[PTCK1]/[STP0B]/RES VSS/AVSS VDD/AVDD HT66F003/HT66V003 16 NSOP-A...

  • Page 10: Pin Description

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Pin Description With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. HT66F002/HT66F0025 Pin Name Function Description PAWU General purpose I/O. Register enabled pull-up and PAPU CMOS wake-up PASR PA0/[STP0]/ STP0 PASR — CMOS TM0 (STM) output [STP0I]/AN0/...
  • Page 11 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Pin Name Function Description PAWU General purpose I/O. Register enabled pull-up and CMOS PAPU wake-up PA7/[INT]/ IFS0 — External interrupt input STCK0/RES/ STCK0 IFS0 — TM0 (STM) clock input ICPCK RSTC — External reset input ICPCK —...
  • Page 12 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Pin Name Function Description PAWU General purpose I/O. Register enabled pull-up and CMOS PAPU wake-up PA5/[INT]/ PASR PTP1I — External interrupt input IFS0 PTP1I IFS0 — TM1 (PTM) input PAWU General purpose I/O. Register enabled pull-up and...
  • Page 13 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM HT66F004 Pin Name Function Description PAWU General purpose I/O. Register enabled pull-up and PAPU CMOS wake-up PA0/PTP0/ PASR OCDSDA/ PTP0 PASR — CMOS PT0 output ICPDA OCDSDA — CMOS On Chip Debug System Data Line (OCDS EV only) ICPDA —...

  • Page 14: Absolute Maximum Ratings

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Pin Name Function Description PBPU CMOS General purpose I/O. Register enabled pull-up PBSR PB3/SCOM3/ SCOM3 SCOMC — SCOM LCD driver output for LCD panel common PBSR — ADC input channel 7 PBPU CMOS General purpose I/O.

  • Page 15: D.c. Characteristics

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM D.C. Characteristics Ta = 25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage (HIRC) — =8MHz — — Operating Current, No load, f =8MHz, ADC off, Normal Mode, f (HIRC) WDT enable, LVR enable —...

  • Page 16: Characteristics

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM A.C. Characteristics Ta = 25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Condition Operating Clock 2.2~5.5V — — 3V/5V Ta = 25°C 3V/5V Ta = 0°C to 70°C System Clock (HIRC) HIRC 2.2V~5.5V Ta = 0°C to 70°C...

  • Page 17: Adc Electrical Characteristics

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM ADC Electrical Characteristics Ta = 25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions A/D Converter Operating Voltage — — — A/D Converter Input Voltage — — — A/D Converter Reference Voltage —...

  • Page 18: Lvr Electrical Characteristics

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM LVR Electrical Characteristics Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage — — — Low Voltage Reset Voltage — LVR Enable, 2.1V option 2.10 Reference Output with Buffer — = +25°C @3.15V 1.04...

  • Page 19: System Architecture

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the...

  • Page 20: Program Counter

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. F e t c h I n s t . 1 E x e c u t e I n s t . 1...

  • Page 21: Stack

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P r o g r a m C o u n t e r T o p o f S t a c k...

  • Page 22: Flash Program Memory

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity HT66F002/HT66F003 1K×14 HT66F0025 2K×14 HT66F004 2K×15 Structure The Program Memory has a capacity of 1K×14, 2K×14 or 2K×15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. HT66F002 HT66F0025 HT66F003 HT66F004 000H Initialisation Vector Initialisation Vector Initialisation Vector Initialisation Vector...
  • Page 23 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM The accompanying diagram illustrates the addressing data flow of the look-up table. L a s t p a g e o r p r e s e n t p a g e P C 9 ~ P C 8 P r o g r a m...

  • Page 24: In Circuit Programming - Icp

    Writer_VDD ICPDA ICPDA ICPCK ICPCK Writer_VSS Writer_VSS To other Circuit To other Circuit HT66F002/HT66F0025 HT66F003/HT66F004 Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip which is used to emulate the HT66F00x device series. This EV chip device also provides an “On-Chip Debug” function to debug the device during the development process. The EV chip and the actual MCU devices are almost functionally compatible except for the “On- Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Rev. 1.71 April 11, 2017...

  • Page 25: Ram Data Memory

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input Power Supply Ground RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General...
  • Page 26 Unused STM0C1 STATUS STM0DL SMOD STM0DH Unused STM0AL INTEG STM0AH INTC0 INTC1 Unused Unused MFI0 Unused Unused PAPU PAWU IFS0 WDTC Unused SMOD1 Unused : Unused, read as “00” HT66F002/HT66F0025 Special Purpose Data Memory Structure Rev. 1.71 April 11, 2017...
  • Page 27 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Bank0 & Bank1 Bank0 & Bank1 IAR0 SADOL SADOH IAR1 SADC0 SADC1 SADC2 RSTC PASR TBLP PBSR TBLH STM0C0 Unused STM0C1 STATUS STM0DL SMOD STM0DH Unused STM0AL INTEG STM0AH INTC0 Unused INTC1 Unused...
  • Page 28 WDTC PTM1RPH Unused SMOD1 PBPU SCOMC PCPU : Unused, read as “00” HT66F004 Special Purpose Data Memory Structure HT66F002/HT66F0025/HT66F003 HT66F004 General General Purpose Purpose Data Memory Data Memory Unused Unused HT66F002/HT66F0025/HT66F003 General Purpose Data Memory Rev. 1.71 April 11, 2017...

  • Page 29: Special Function Register Description

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are...

  • Page 30: Bank Pointer - Bp

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Bank Pointer – BP For this series of devices, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank1 must be implemented using Indirect Addressing. BP Register Name — — — — — — — DMBP0 — — — — — — — — —...

  • Page 31: Status Register - Status

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if...

  • Page 32: Eeprom Data Memory

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM STATUS Register Name — — — — — — × × × × "×" unknown Bit 7~6 Unimplemented, read as "0" TO: Watchdog Time-Out flag Bit 5 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest- order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero...

  • Page 33: Eeprom Registers

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address registers, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Function Register. The EEC register however, being located in Bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Control Registers List Name — — — — — — — WREN RDEN EEA Register Name — — — — — —...

  • Page 34: Reading Data From The Eeprom

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM EEC Register Name — — — — WREN RDEN — — — — — — — — Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.

  • Page 35: Writing Data To The Eeprom

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the devices are powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data...

  • Page 36: Programming Considerations

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES ;...

  • Page 37: Oscillator

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiring...

  • Page 38: Internal Rc Oscillator - Hirc

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at temperature of 25°C degrees, the fixed oscillation frequency of the HIRC will have a tolerance within 2%. Internal 32kHz Oscillator – LIRC The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal...

  • Page 39: System Operation Modes

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM High Speed Oscillation HIRC Prescaler HLCLK Low Speed Oscillation CKS2~CKS0 bits LIRC LIRC IDLEN Time Base 0 Time Base 1 TBCK System Clock Configurations Note: When the system clock source f is switched to f from f , the high speed oscillation will stop to conserve the power. Thus there is no f /64 for peripheral circuit to use. System Operation Modes...

  • Page 40: Control Register

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the f is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the f clock will be LIRC stopped too, and the Watchdog Timer function is disabled. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the f clocks will LIRC continue to operate if the Watchdog Timer function is enabled.
  • Page 41 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Bit 4 Unimplemented, read as "0" Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 mode, but after a wake-up has occurred the flag will change to a high level after 1~2 cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: System Clock Selection 0: f /2 ~ f /64 or f...

  • Page 42: Operating Mode Switching

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Bit 0 WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Operating Mode Switching The devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1 register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the...

  • Page 43: Normal Mode To Slow Mode Switching

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by setting the HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register.This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. N O R M A L M o d e C K S 2 ~ C K S 0 = 0 0 x B &...

  • Page 44: Slow Mode To Normal Mode Switching

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. S L O W M o d e C K S 2 ~ C K S 0 ¹...

  • Page 45: Entering The Sleep1 Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Entering the SLEEP1 Mode There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction, but the WDT will remain with the clock source coming from the f LIRC clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in SMOD1 register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruc- tion, but the Time Base clock will be on.

  • Page 46: Standby Current Considerations

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.

  • Page 47: Watchdog Timer

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal f clock which is supplied by the LIRC LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 2 to 2 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with V , temperature and process variations. The WDT can be enabled/disabled using the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the SMOD1 register. These registers...

  • Page 48: Watchdog Timer Operation

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM SMOD1 Register Name FSYSON — — — LVRF — — — — — — — — — “x” unknown FSYSON: f Bit 7 Control in IDLE Mode 0: Disable 1: Enable Bit 6~4 Unimplemented, read as 0 Bit 3 D3: Reserved bit Bit 2 LVRF: LVR function reset flag 0: Not active 1: Active This bit can be clear to “0”, but can not be set to “1”.

  • Page 49: Reset And Initialisation

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM The maximum time-out period is when the 2 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. WDTC Register WE4~WE0 bits Reset MCU RES pin reset “CLR WDT”Instruction “HALT”Instruction LIRC LIRC 11-stage Divider 7-stage Divider 8-to-1 MUX WDT Time-out LIRC LIRC WS2~WS0 LIRC LIRC...

  • Page 50: Reset Functions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. V D D 0 . 9 V R E S R S T D +...
  • Page 51 R S T D + S S T I n t e r n a l R e s e t Note: t is power-on delay, typical time=16.7ms RSTD RES Reset Timing Chart • RSTC External Reset Register – HT66F002/HT66F003 Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3...
  • Page 52 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • SMOD1 Register Name FSYSON — — — LVRF — — — — — — — — — “x” unknown Bit 7 FSYSON: f Control in IDLE Mode Describe elsewhere Bit 6~4 Unimplemented, read as 0 Bit 3 D3: Reserved bit Bit 2 LVRF: LVR function reset flag 0: Not active 1: Active This bit can be clear to “0”, but can not be set to “1”.

  • Page 53: Reset Initial Conditions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: RESET Conditions Power-on reset LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged...
  • Page 54 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. WDT Time-out RES Reset Reset RES Reset WDT Time-out Register (Normal (Normal (Power On) (HALT) (HALT)* Operation) Operation) Program ● ● ● ● Counter ● ● ● ●...
  • Page 55 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM WDT Time-out RES Reset Reset RES Reset WDT Time-out Register (Normal (Normal (Power On) (HALT) (HALT)* Operation) Operation) ● ● ● 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0...

  • Page 56: Input/Output Ports

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The devices provide bidirectional input/output lines labeled with port names PA~PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Control Register List • HT66F002/HT66F0025 Register Name PAPU PAWU PASR PAS7 PAS6 PAS5 PAS4 PAS3 PAS2 PAS1 PAS0 IFS0 —...

  • Page 57: Pull-High Resistors

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • HT66F004 Register Name PAPU PAWU — — PBPU — — — — — — — — — — — PCPU — — — — — PASR PAS7 PAS6 PAS5 PAS4 PAS3 PAS2...

  • Page 58: Port A Wake-Up

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM PCPU Register – HT66F004 Name — — — — — — — — — — — — — — — Bit 7~3 Unimplemented, read as 0 Bit 2~0 I/O Port C bit 2~ bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature...

  • Page 59: Pin-Shared Functions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM PBC Register – HT66F003 Name — — — — — — Bit 7 ~ 6 Unimplemented, read as 0 Bit 5 ~ 0 I/O Port B bit 5 ~ bit 0 Input/Output Control 0: Output 1: Input PBC Register – HT66F004 Name — — — Bit 7 Unimplemented, read as 0 Bit 6~0 I/O Port B bit 6 ~ bit 0 Input/Output Control 0: Output 1: Input PCC Register – HT66F004 Name —...
  • Page 60 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Pin-shared Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. • PASR Register – HT66F002/HT66F0025 Name PAS7 PAS6 PAS5 PAS4 PAS3 PAS2 PAS1 PAS0 Bit 7~6 PAS7~PAS6: Pin-Shared Control Bits 00: PA5/INT 01: STP0B 10: PA5/INT 11: AN3 Bit 5~4 PAS5~PAS4: Pin-Shared Control Bits 00: PA2/INT 01: STP0 10: VREFO 11: AN2...
  • Page 61 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • PASR Register – HT66F003 Name PAS7 PAS6 PAS5 PAS4 PAS3 PAS2 PAS1 PAS0 Bit 7 PAS7: Pin-Shared Control Bit 0: PA7/PTCK1 1: STP0B Note: PAS7 is valid when RSTC=55H Bit 6 PAS6: Pin-Shared Control Bit 0: PA6/PTCK1/STP0I 1: STP0 PAS5: Pin-Shared Control Bit Bit 5 0: PA4/INT/PTCK1 1: STP0 Bit 4 PAS4: Pin-Shared Control Bit...
  • Page 62 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • PBSR Register – HT66F003 Name — — PBS5 PBS4 PBS3 PBS2 PBS1 PBS0 — — — — Bit 7~6 Unimplemented, read as “0” Bit 5 PBS5: Pin-Shared Control Bit 0: PB5 1: PTP1 Bit 4 PBS4: Pin-Shared Control Bit 0: PB4 1: PTP1B Bit 3 PBS3: Pin-Shared Control Bit...
  • Page 63 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • IFS0 Register – HT66F002/HT66F0025 Name — — STCK0PS STP0IPS — — INTPS1 INTPS0 — — — — — — — — Bit 7~6 Unimplemented, read as "0" STCK0PS: STCK0 Pin Remapping Control Bit 5 0: STCK0 on PA7 (default) 1: STCK0 on PA6 STP0IPS: STP0I Pin Remapping Control Bit 4 0: STP0I on PA6 (default) 1: STP0I on PA0 Bit 3~2 Unimplemented, read as "0"...

  • Page 64: I/O Pin Structures

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P u l l - H i g h R e g i s t e r C o n t r o l B i t...

  • Page 65: System Clock Output Pin Clo

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM System Clock output pin CLO The device HT66F004 provides a system clock output pin CLO. MCU system clock can output to the CLO pin by setting pin-shared control register bit PBS4 to 1. The highest output frequency is 8MHz in this device. Please note that when the noise problem is an important issue, it is better not to use CLO output function. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull- high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.71 April 11, 2017...

  • Page 66: Timer Modules - Tm

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the devices include several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Standard and Periodic TM sections.

  • Page 67: Tm Interrupts

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM TM Interrupts The Standard and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn and xTPnI. The TM input pin xTCKn, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the xTnCK2~xTnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The other TM input pin, xTPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the xTnIO1 and xTnIO0 bits in the xTMnC1 register. The TMs each have two output pins with the label xTPn and xTPnB. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the...

  • Page 68: Programming Considerations

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM PTPnB Inverting Output PTPn Output Capture Input PTPnI PTCKn TCK Input PTM Function Pin Control Block Diagram Programming Considerations The TM Counter Registers and the Capture/Compare CCRA register, and CCRP register pair for Periodic Timer Module, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA register and CCRP registers are implemented in the way shown in the following diagram and accessing the register is carried out CCRP low byte register using the following access procedures. Accessing the CCRA or CCRP low byte register without following these access...

  • Page 69: Standard Type Tm - Stm

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can be controlled with two external input pins and can drive two external output pins. Device TM Type TM Name TM Input Pin TM Output Pin HT66F002 HT66F0025 10-bit STM STCK0, STP0I STP0, STP0B HT66F003 C C R P C o m p a r a t o r P M a t c h...

  • Page 70: Standard Type Tm Register Description

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as three CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0 STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC...
  • Page 71 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM bit 2~0 ST0RP2~ ST0RP0: STM CCRP 3-bit register, compared with the STM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 STM0 clocks 001: 128 STM0 clocks 010: 256 STM0 clocks 011: 384 STM0 clocks 100: 512 STM0 clocks 101: 640 STM0 clocks 110: 768 STM0 clocks 111: 896 STM0 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the ST0CCLR bit is set to zero. Setting the ST0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. STM0C1 Register Name ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR bit 7~6 ST0M1~ ST0M0: Select STM0 Operating Mode...
  • Page 72 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM In the Compare Match Output Mode, the ST0IO1~ST0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the ST0IO1~ST0IO0 bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the ST0OC bit. Note that the output level requested by the ST0IO1~ST0IO0 bits must be different from the initial value setup using the ST0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the ST0ON bit from low to high. In the PWM Mode, the ST0IO1 and ST0IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the ST0IO1 and ST0IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the ST0IO1 and ST0IO0 bits are changed when the TM is running. bit 3 ST0OC: STM0 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM output Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM output Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM output Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the STM output pin when the ST0ON bit changes from low to high. bit 2 ST0POL: STM0 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the STM0 output pin. When the bit is set high the STM output pin...
  • Page 73 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM STM0DL Register Name Bit 7 ~ 0 STM0 Counter Low Byte Register bit 7 ~ bit 0 STM0 10-bit Counter bit 7 ~ bit 0 STM0DH Register Name — — — — — — — — — — — — — — — — — — bit 7~2 Unimplemented, read as "0" bit 1~0 STM0 Counter High Byte Register bit 1 ~ bit 0 STM0 10-bit Counter bit 9 ~ bit 8 STM0AL Register...

  • Page 74: Standard Type Tm Operating Modes

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the ST0M1 and ST0M0 bits in the STM0C1 register. Compare Output Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match...
  • Page 75 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM ST0CCLR = 0; ST0M[1:0] = 00 Counter Counter Value overflow CCRP > 0 Counter cleared by CCRP value CCRP = 0 0x3FF Counter Resume Reset CCRP > 0 CCRP Pause Stop CCRA Time...
  • Page 76 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM ST0CCLR = 1; ST0M[1:0] = 00 Counter Value CCRA > 0 Counter cleared by CCRA value CCRA = 0 Counter overflow 0x3FF Resume CCRA = 0 CCRA Counter Reset Pause Stop CCRP Time...

  • Page 77: Timer/Counter Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function by setting pin-share function register. PWM Output Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively and also the ST0IO1 and ST0IO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
  • Page 78 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter ST0DPX=0;ST0M[1:0]=10 Value Counter Clearedby CCRP Counter reset when ST0ON returns high CCRP Counter Stop If Resume ST0ON bit low Pause CCRA Time ST0ON ST0PAU ST0POL CCRA Int. Flag STMA0F CCRP Int. Flag STMP0F...
  • Page 79 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter ST0DPX=1;ST0M[1:0]=10 Value Counter Cleared by CCRA Counter reset when ST0ON returns high CCRA Counter Stop If Resume ST0ON bit low Pause CCRP Time ST0ON ST0PAU ST0POL CCRP Int. Flag STMP0F CCRA Int.

  • Page 80: Single Pulse Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Single Pulse Mode To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively and also the ST0IO1 and ST0IO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the ST0ON bit, which can be implemented using the application program. However in the Single Pulse Mode, the ST0ON bit can also be made to automatically change from low to high using the external STCK0 pin, which will in turn initiate the Single Pulse output. When the ST0ON bit transitions to a high level,...
  • Page 81 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter Value ST0M [1:0] = 10 ; ST0IO [1:0] = 11 Counter stopped by CCRA Counter Reset when ST0ON returns high CCRA Counter Stops Resume Pause by software CCRP Time ST0ON Auto. set by...

  • Page 82: Capture Input Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits ST0M1 and ST0M0 in the STM0C1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STP0I, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the ST0IO1 and ST0IO0 bits in the STM0C1 register. The counter is started when the ST0ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STP0I the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STP0I the counter will continue to free run until the ST0ON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The ST0IO1 and ST0IO0 bits can select the active trigger edge on the STP0I to be a rising edge, falling edge or both edge types. If the ST0IO1 and ST0IO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STP0I, however it must be noted that the counter will continue to run. The ST0CCLR and ST0DPX bits are not used in this Mode. Counter Value ST0M [1:0] = 01 Counter cleared by CCRP Counter Counter...

  • Page 83: Periodic Type Tm - Ptm

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pins. Device Name TM Input Pin TM Output Pin HT66F003 10-bit PTM PTCK1, PTP1I PTP1,PTP1B PTCK0, PTP0I PTP0,PTP0B HT66F004 10-bit PTM PTCK1, PTP1I PTP1,PTP1B Periodic TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are two internal comparators with the names, Comparator A and Comparator P. These...

  • Page 84: Periodic Type Tm Register Description

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name PTMnC0 PTnPAU PTnCK2 PTnCKn PTnCK0 PTnON — — — PTMnCn PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCKS PTnCCLR PTMnDL PTMnDH — —...
  • Page 85 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Bit 3 PTnON: PTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TM Output control bit, when the bit changes from low to high. Bit 2~0 Unimplemented, read as “0” PTMnC1 Register Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCKS PTnCCLR Bit 7~6 PTnM1~ PTnM0: Select PTM Operation Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/ Counter Mode, the PTM output pin state is undefined.
  • Page 86 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When these bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the PTnOC bit. Note that the output level requested by the PT1IO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the PTnIO1 and PTnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the TM is running. Bit 3 PTnOC: PTPn/PTPnB Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. PTnPOL: PTPn/PTPnB Output polarity Control Bit 2 0: non-invert 1: invert This bit controls the polarity of the PTPn/PTPnB output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode.
  • Page 87 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM PTMnDL Register Name PTMnDL: PTM Counter Low Byte Register bit 7 ~ bit 0 Bit 7~0 PTM 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Name — — — — — — — — — — — — — — — — — — Bit 7~2 Unimplemented, read as “0” Bit 1~0 PTMnDH: PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 PTMnAL Register...

  • Page 88: Periodic Type Tm Operating Modes

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM PTMnRPH Register Name — — — — — — — — — — — — — — — — — — Bit 7~2 Unimplemented, read as "0" PTMnRPH: PTM CCRP High Byte Register bit 1 ~ bit 0 Bit 1~0 PTM 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register.
  • Page 89 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter overflow Counter Value PTnCCLR = 0; PTnM [1:0] = 00 CCRP > 0 CCRP=0 Counter cleared by CCRP value 0x3FF CCRP > 0 Counter Resume Restart CCRP Pause Stop CCRA Time PTnON...
  • Page 90 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter Value PTnCCLR = 1; PTnM [1:0] = 00 CCRA = 0 CCRA > 0 Counter cleared by CCRA value Counter overflow 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTnON...

  • Page 91: Timer/Counter Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should all be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values.
  • Page 92 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter Value PTnDPX = 0; PTnM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTnON returns high CCRP Counter Stop if Pause Resume PTnON bit low CCRA Time PTnON PTnPAU PTnPOL CCRA Int.

  • Page 93: Single Pulse Output Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Single Pulse Output Mode To select this mode, the required bit pairs, PTnM1 and PTnM0 should be set to 10 respectively and also the corresponding PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter...
  • Page 94 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter Value PTnM [1:0] = 10 ; PTnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTnON returns high CCRA Counter Stops Resume Pause by software CCRP Time PTnON Auto. set by...

  • Page 95: Capture Input Mode

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPnI or PTCKn pin, selected by the PTnCKS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPnI or PTCKn pin the present value in the counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.71 April 11, 2017...
  • Page 96 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Counter Value PTnM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP Resume Pause Time PTnON PTnPAU Active Active Active edge edge edge PTM capture pin PTPnI or PTCKn CCRA Int. Flag PTMAnF CCRP Int.

  • Page 97: Analog To Digital Converter

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. The external or internal analog signal to be converted is...

  • Page 98: A/D Converter Register Description

    SACS0 SADC1 SAINS2 SAINS1 SAINS0 — — SACK2 SACK1 SACK0 SADC2 ENOPA VBGEN — — SAVRS3 SAVRS2 SAVRS1 SAVRS0 A/D Converter Register List – HT66F002/HT66F0025/HT66F003 Name SADOL — — — — (ADRFS=0) SADOL (ADRFS=1) SADOH (ADRFS=0) SADOH — — —...

  • Page 99: A/D Converter Control Registers - Sadc0, Sadc1, Sadc2, Pasr, Pbsr

    Note that when the programs select external signal and internal signal as an ADC input signal simultaneously, then the hardware will only choose the internal signal as an ADC input. In addition, if the programs select external reference voltage V and the internal reference voltage V as ADC reference voltage, then the hardware will only choose the internal reference voltage V as an ADC reference voltage input. The pin-shared function control registers, named PASR and PBSR, contain the corresponding pin- shared selection bits which determine which pins on Port A and Port B are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. • SADC0 Register – HT66F002/HT66F0025/HT66F003 Name START ADBZ ENADC ADRFS — — SACS1 SACS0 — — — — START: Start the A/D conversion Bit 7 0→1→0: Start A/D conversion 0→1: Reset the A/D converter and set ADBZ to 0 1→0: Start A/D conversion and set ADBZ to 1...
  • Page 100 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • SADC0 Register – HT66F004 Name START ADBZ ENADC ADRFS — SACS2 SACS1 SACS0 — — Bit 7 START: Start the A/D conversion 0→1→0: Start A/D conversion 0→1: Reset the A/D converter and set ADBZ to 0 1→0: Start A/D conversion and set ADBZ to 1 Bit 6 ADBZ: ADC busy flag 0: A/D conversion ended or no conversion 1: A/D is busy ENADC: ADC enable/disable control register Bit 5 0: ADC disable 1: ADC enable Bit 4 ADRFS: A/D output data format selection bit 0: ADC output data format → SADOH=D[11:4]; SADOL=D[3:0] 1: ADC output data format → SADOH=D[11:8]; SADOL=D[7:0] Bit 3~2 Unimplemented, read as “0”...

  • Page 101: A/D Operation

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM • SADC2 Register Name ENOPA VBGEN — — SAVRS3 SAVRS2 SAVRS1 SAVRS0 — — — — Bit 7 ENOPA: OPA enable/disable control register 0: OPA disable 1: OPA enable Bit 6 VBGEN: Bandgap buffer disable/enable control bit 0: Bandgap buffer disable 1: Bandgap buffer enable Bit 5~4 Unimplemented, read as "0" SAVRS3~SAVRS0: ADC reference voltage selection bit Bit 3~0 0000: ADC reference voltage comes from AV 0001: ADC reference voltage comes from V 0010: ADC reference voltage comes from V × 2 0011: ADC reference voltage comes from V × 3...

  • Page 102: A/D Converter Input Signal

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Although the A/D clock source is determined by the system clock f , and by bits SACK2~SACK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended value of permissible A/D clock period, t , is from 0.5μs to 10μs, care must be ADCK taken for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the SACK2~SACK0 bits should not be set to 000B or 11xB. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Controlling the power on/off function of the A/D converter circuitry is implemented using the ENADC bit in the SADC0 register. This bit must be set high to power on the A/D converter. When the ENADC bit is set high to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no...

  • Page 103: Conversion Rate And Timing Diagram

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as t takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an A/D conversion which is defined as t are necessary. Maximum single A/D conversion rate = A/D clock period / 16 However, there is a usage limitation on the next A/D conversion after the current conversion is complete. When the current A/D conversion is complete, the converted digital data will be stored in the A/D data register pair and then latched after half an A/D clock cycle. If the START bit is set to 1 in half an A/D clock cycle after the end of A/D conversion, the converted digital data stored in the A/D data register pair will be changed. Therefore, it is recommended to initiate the next A/D conversion after a certain period greater than half an A/D clock cycle at the end of current A/D conversion. O N 2 S T...

  • Page 104: Summary Of A/D Conversion Steps

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion frequency by SACKS2~ SACKS0 • Step 2 Enable the ADC by set ENADC=1 • Step 3 Select which pins will be configure as ADC analog inputs • Step 4 If input comes from I/O, set SAINS[2:0]=000 and then set SACS bit fields to corresponding PAD input If input comes from internal input, set SAINS[2:0] to corresponding internal input source • Step 5 Select reference voltage comes from external V , AV or V by SAVRS[3:0] Note: (1) If select V as reference voltage, (PAS3, PAS2) = (1, 0) for HT66F002/HT66F004 (2) If select V as reference voltage, (PAS2, PAS1) = (1, 0) for HT66F003 • Step 6 Select ADC output data format by ADRFS • Step 7...

  • Page 105: Programming Considerations

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by clearing the ENADC bit in the SADC0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the V or V voltage, this gives a single bit analog input value of V or V divided by 4096. 1 LSB= (AV or V ) / 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (AV or V ) / 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the...

  • Page 106: A/D Programming Examples

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,0BH mov SADC1,a ; select f /8 as A/D clock and switch off the bandgap reference voltage...
  • Page 107 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,0BH mov SADC1,a ; select f /8 as A/D clock and switch off the bandgap reference voltage...

  • Page 108: Interrupts

    MF0F — Time Base TBnE TBnF n=0 or 1 EEPROM — STMA0E STMA0F — STMP0E STMP0F Interrupt Register Bit Naming Conventions – HT66F002/HT66F0025 Function Enable Bit Request Flag Notes Global — — INT Pin INTE INTF — A/D Converter —...
  • Page 109 TB1F TB0F INT0F TB1E TB0E INT0E INTC1 INT1F MF0F INT1E MF0E MFI0 PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0E INTEG Register – HT66F002/HT66F0025/HT66F003 Name — — — — — — INT0S1 INT0S0 — — — — — — —...
  • Page 110 — — — Bit 7 ~ 4 Unimplemented, read as “0” Bit 3 ~ 2 INT1S1, INT1S0: Defines INT1 interrupt active edge 00: Disable Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt Bit 1 ~ 0 INT0S1, INT0S0: Defines INT0 interrupt active edge 00: Disable Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTC0 Register – HT66F002/HT66F0025/T66F003 Name — TB1F TB0F INTF TB1E TB0E INTE — — Bit 7 Unimplemented, read as "0" Bit 6 TB1F : Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request...
  • Page 111 0: No request 1: Interrupt request TB1E : Time Base 1 Interrupt Control Bit 3 0: Disable 1: Enable Bit 2 TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 1 INT0E: INT0 Interrupt Control 0: Disable 1: Enable Bit 0 EMI: Global Interrupt Control 0: Disable 1: Enable INTC1 Register – HT66F002/HT66F0025 Name — MF0F — MF0E — — — — Bit 7 Unimplemented, read as "0" ADF: A/D Converter Interrupt Request Flag Bit 6 0: No request 1: Interrupt request Bit 5 DEF: Data EEPROM Interrupt Request Flag...
  • Page 112 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM INTC1 Register – HT66F003 Name MF1F MF0F MF1E MF0E MF1F: Multi-function 1 Interrupt Request Flag Bit 7 0: No request 1: Interrupt request Bit 6 ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request DEF: Data EEPROM Interrupt Request Flag Bit 5 0: No request 1: Interrupt request Bit 4 MF0F: Multi-function 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 MF1E: Multi-function 1 Interrupt Control 0: Disable 1: Enable Bit 2 ADE: A/D Converter Interrupt Control 0: Disable 1: Enable...
  • Page 113 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM MFI0 Register – HT66F002/HT66F0025/HT66F003 Name — — STMA0F STMP0F — — STMA0E STMP0E — — — — — — — — Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 STMA0F: STM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 STMP0F: STM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0"...

  • Page 114: Interrupt Operation

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM MFI1 Register – HT66F003 only Name — — PTMA1F PTMP1F — — PTMA1E PTMP1E — — — — — — — — Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 PTMA1F: PTM Comparator A match interrupt request flag 0: No request 1: Interrupt request PTMP1F: PTM Comparator P match interrupt request flag Bit 4 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0"...
  • Page 115 PTMP1E M. Funct. 1 MF1F MF1E PTM A PTMA1F PTMA1E Interrupts contained within Multi-Function Interrupts HT66F003 only Interrupt Structure – HT66F002/HT66F0025/HT66F003 EMI auto disabled in ISR Legend Request Flag, no auto reset in ISR Interrupt Request Enable Master Vector Priority...

  • Page 116: External Interrupt

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM External Interrupt The external interrupt is controlled by signal transitions on the pins INT and INT0~INT1. An external interrupt request will take place when the external interrupt request flag, INTnF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to the interrupt vector address, the global interrupt enable bit, EMI, and the external interrupt enable bit, INTnE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins by setting the pin-shared registers. The pin must also be setup as an input by setting the corresponding bit in the port control...

  • Page 117: Time Base Interrupts

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source f . This f input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates f which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. TBC Register Name TBON...

  • Page 118: Eeprom Interrupt

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the EEPROM interrupt request flag, DEF, will also be automatically cleared. TM Interrupts The TMs each has two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the TMs there are two interrupt request flags xTMPnF and xTMAnF and two enable bits xTMPnE and xTMAnE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up...

  • Page 119: Scom Function For Lcd - Ht66F004

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. SCOM Function for LCD – HT66F004 The HT66F004 device has the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pin on the I/O ports. The LCD signals are generated using the application program. LCD peration An external LCD panel can be driven using this device by configuring the I/O pins as common pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary V /2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation.

  • Page 120: Lcd Bias Current Control

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM LCD Bias Current Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Name — ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN — — Bit 7 Unimplemented, read as “0” Bit 6~5 ISEL1~ISEL0: Select resistor for R type LCD bias current(V =5V) 00: 2×100kΩ (1/2 Bias), I = 25μA BIAS 01: 2×50 kΩ (1/2 Bias), I = 50μA BIAS 10: 2×25 kΩ (1/2 Bias), I = 100μA BIAS 11: 2×12.5 kΩ (1/2 Bias), I...

  • Page 121: Application Circuits

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Application Circuits 0.01µF** 1N4148* 10kΩ~ Reset 100kΩ AN0~AN3 Circuit 0.1µF PA0~PA7 300Ω* 0.1µF~1µF HT66F002/HT66F0025 0.01µF** 1N4148* 10kΩ~ Reset AN0~AN3 100kΩ Circuit 0.1µF PA0~PA7 300Ω* PB0~PB5 0.1µF~1µF HT66F003 0.01µF** AN0~AN8 1N4148* 10kΩ~ Reset 100kΩ...

  • Page 122: Instruction Set

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to...

  • Page 123: Logical And Rotate Operation

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such...

  • Page 124: Instruction Set Summary

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A,[m] Add Data Memory to ACC Z, C, AC, OV ADDM A,[m] Add ACC to Data Memory...
  • Page 125 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] Move Data Memory to ACC None MOV [m],A Move ACC to Data Memory Note None MOV A,x Move immediate data to ACC None Bit Operation CLR [m].i...

  • Page 126: Instruction Definition

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Instruction Definition Add Data Memory to ACC with Carry ADC A,[m] Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ← ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ← ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x...
  • Page 127 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ← Program Counter + 1 Program Counter ← addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ← 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ← 0 Affected flag(s) None CLR WDT...
  • Page 128 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ← [m] Affected flag(s) DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H Affected flag(s) DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1.
  • Page 129 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ← addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ← [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ← x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory.
  • Page 130 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ← Stack ACC ← x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ← Stack EMI ← 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 Affected flag(s) None...
  • Page 131 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 Affected flag(s) None Rotate Data Memory right through Carry RRC [m] Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 Affected flag(s) RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0...
  • Page 132 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ← [m] − 1 Skip if ACC=0 Affected flag(s) None Set Data Memory SET [m] Description Each bit of the specified Data Memory is set to 1. Operation [m] ← FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ← 1 Affected flag(s) None Skip if increment Data Memory is 0...
  • Page 133 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ← ACC − [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ← ACC − x Affected flag(s) OV, Z, AC, C SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 ↔ [m].7~[m].4 Affected flag(s) None SWAPA [m]...
  • Page 134 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM TABRD [m] Read table (specific page) to TBLH and Data Memory Description The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None...

  • Page 135: Package Information

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.71 April 11, 2017...

  • Page 136: 8-Pin Sop (150Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 8-pin SOP (150mil) Outline Dimensions & " Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.154 BSC — 0.012 — 0.020 C’ — 0.193 BSC — — — 0.069 —...

  • Page 137: 10-Pin Sop (150Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 10-pin SOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.154 BSC — 0.012 — 0.018 C′ — 0.193 BSC — — — 0.069 — 0.039 BSC —...

  • Page 138: 10-Pin Msop Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 10-pin MSOP Outline Dimensions R 0 . 1 0 ( 4 C O R N E R S ) Dimensions in inch Symbol Min. Nom. Max. — — 0.043 0.000 — 0.006 0.030 0.033...

  • Page 139: 16-Pin Nsop (150Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 16-pin NSOP (150mil) Outline Dimensions & Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.154 BSC — 0.012 — 0.020 C’ — 0.390 BSC — — — 0.069 —...

  • Page 140: 20-Pin Dip (300Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 20-pin DIP (300mil) Outline Dimensions Fig 1. Full Lead Packages Fig 2. 1/2 Lead Packages See Fig 1 Dimensions in inch Symbol Min. Nom. Max. 0.980 1.030 1.060 0.240 0.250 0.280 0.115 0.130 0.195...
  • Page 141 HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM See Fig2 Dimensions in inch Symbol Min. Nom. Max. 0.945 0.965 0.985 0.275 0.285 0.295 0.120 0.135 0.150 0.110 0.130 0.150 0.014 0.018 0.022 0.045 0.050 0.060 — 0.1BSC — 0.300 0.310 0.325 —...

  • Page 142: 20-Pin Sop (300Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 20-pin SOP (300mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.406 BSC — — 0.406 BSC — 0.012 — 0.020 C’ — 0.504 BSC — — — 0.104 — 0.050 BSC —...

  • Page 143: 20-Pin Ssop (150Mil) Outline Dimensions

    HT66F002/HT66F0025/HT66F003/HT66F004 Cost-Effective A/D Flash MCU with EEPROM 20-pin SSOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. — 0.236 BSC — — 0.155 BSC — 0.008 — 0.012 C’ — 0.341 BSC — — — 0.069 — 0.025 BSC —...
  • Page 144 However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.

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