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6.3.6 NMI
An NMI is generated when the #NMI input on the processor is asserted low. When an NMI occurs, the processor
performs exception handling after it has finished executing the instruction currently underway. The PC value saved
to the stack in exception handling is the address of the instruction that was being executed.
During an NMI exception, other new NMI exceptions are disabled and not accepted (multiple NMI exceptions
prohibited). To prevent another NMI from being serviced during a current NMI exception, the processor masks
NMIs before it starts executing the NMI exception handler routine. NMIs are unmasked by executing the reti
instruction, so that it is possible that if another exception occurs in an NMI handler routine and reti is executed
in that routine, NMIs will be unmasked. In such a case, the NMI handler routine may not be executed correctly.
Therefore, make sure that no other exceptions will occur during an NMI handler routine.
NMIs are nonmaskable interrupts, but because if an NMI occurs before SP is set after the processor is reset (either
cold start or hot start), the program may run out of control, the #NMI input on the processor is therefore masked in
the hardware until the SP is set by the ld.w %sp,%rs instruction.
6.3.7 Software Exceptions
A software exception is generated by executing the int imm2 instruction. The PC value saved to the stack in this
exception handling is the address of the next instruction. The operand imm2 in the int instruction specifies the
vector address for one of four distinct software exceptions. The processor reads the vector for the exception from
the address that is equal to TTBR + 48 (vector address for software exception 0) plus 4 × imm2, before branching to
the handler routine.
6.3.8 Maskable External Interrupts
The C33 PE Core can accept up to 240 types of maskable external interrupts. It is only when the IE (interrupt
enable) flag in the PSR is set that the processor accepts a maskable external interrupt. Furthermore, their acceptable
interrupt levels are limited by the IL (interrupt level) field in the PSR. The interrupt levels (0–15) in the IL field
dictate the interrupt levels that can be accepted by the processor, and only interrupts with priority levels higher than
that are accepted.
The IE flag and the IL field can be set in the software. When an exception occurs, the IE flag is cleared to 0 (interrupts
disabled) after the PSR is saved to the stack, and the maskable interrupts remain disabled until the IE flag is set
in the handler routine or the handler routine is terminated by the reti instruction that restores the PSR from the
stack. The IL field is set to the priority level of the interrupt that occurred.
Multiple interrupts or the ability to accept another interrupt during exception handling if its priority is higher than
that of the currently serviced interrupt can easily be realized by setting the IE flag in the interrupt handler routine.
When the processor is reset, the PSR is initialized to 0 and the maskable interrupts are therefore disabled, and the
interrupt level is set to 0 (interrupts with priority levels 1–15 enabled).
The following describes how the maskable interrupts are accepted and processed by the processor.
(1) Suspends the instruction currently being executed.
The interrupt is accepted synchronously with the rising edge of the system clock at the end of the cycle of the
currently executed instruction.
(2) Saves the contents of the PC and PSR to the stack (SP), in that order.
(3) Clears the IE flag in the PSR and copy the priority level of the accepted interrupt to the IL field.
(4) Reads the vector for the interrupt from the vector address in the vector table, and sets it in the PC. The processor
then branches to the interrupt handler routine.
In the interrupt handler routine, the reti instruction should be executed at the end of processing. In the reti
instruction, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the
suspended instruction.
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
6 FUNCTIONS
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