Receiver Back-End - Motorola GP Series Service Information

2-4 THEORY OF OPERATION
Both the pre and post-RF amplifier varactor tuned filters have similar responses. The 3 dB
bandwidth of the filter is about 12 MHz. This enables the filters to be electronically controlled by
using a single control voltage which is DACRx.
The output of the post-RF amplifier filter is connected to the passive double balanced mixer which
consists of T3301, T3302, and CR3301. Matching of the filter to the mixer is provided by C3317,
C3318 and L3308. After mixing with the first LO signal from the voltage controlled oscillator (VCO)
using high side injection, the RF signal is down-converted to the 45.1 MHz IF signal.
The IF signal coming out of the mixer is transferred to the crystal filter (Y3200) through a resistor
pad (R3321 - R3323) and a diplexer (C3320 and L3309). Matching to the input of the crystal filter is
provided by C3200 and L3200. The crystal filter provides the necessary selectivity and
intermodulation protection.
3.2

Receiver Back-End

( Refer to Figure 2-2 and the VHF Receiver Back End schematic diagram )
The output of crystal filter Y3200 is matched to the input of IF amplifier transistor Q3200 by
capacitor C3203. Voltage supply to the IF amplifier is taken from the receive 5 volts (R5). The gain
controlled IF amplifier provides a maximum gain of about 10dB. The amplified IF signal is then
coupled into U3220 pin 3 via L3202, C3207, and C3230 which provides impedance matching for the
IF amplifier and U3220.
The IF signal applied to pin 3 of U3220 is amplified, down-converted, filtered, then demodulated to
produce the recovered audio at pin 27 of U3220. This IF IC is electronically programmable, and the
amount of filtering, which is dependent on the radio channel spacing, is controlled by the
microprocessor. Additional filtering, once externally provided by the conventional ceramic filters, is
replaced by internal filters in the IF module (U3220).
The IF IC uses a type of direct conversion process, whereby the externally generated second LO
frequency is divided by two in U3220 so that it is very close to the first IF frequency. The IF IC
(U3220) synthesizes the second LO and phase-locks the VCO to track the first IF frequency. The
second LO is designed to oscillate at twice the first IF frequency because of the divide-by-two
function in the IF IC.
In the absence of an IF signal, the VCO "searches" for a frequency, or its frequency will vary close to
twice the IF frequency. When an IF signal is received, the VCO will lock onto the IF signal. The
second LO/VCO is a Colpitts oscillator built around transistor Q3270. The VCO has a varactor
diode, D3270, to adjust the VCO frequency. The control signal for the varactor is derived from a loop
filter consisting of C3278 to C3280, R3274 and R3275.
The IF IC (U3220) also provides a received signal-strength indicator (RSSI) and a squelch output.
The RSSI is a dc voltage monitored by the microprocessor and is used as a peak indicator during
the bench tuning of the receiver front-end varactor filter. The RSSI voltage is also used to control the
automatic gain control (AGC) circuit at the front-end.
The demodulated signal on pin 27 of U3220 is also used for squelch control. The signal is routed to
U404 (ASFIC) where squelch signal shaping and detection takes place. The demodulated audio
signal is also routed to U404 for processing before going to the audio amplifier for amplification.