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28
Service Information
Shared Memory Controller
Addressing
Communication between the card and mainframe is handled through a set of memory addres-
ses, some of which are handled as registers. Only alternate addresses from the mainframe are
used because the least-significant bit is not connected (shared address bit 0 is connected to
mainframe address bit 1, etc.). The upper 2 bits of the shared address bus (shared address bits
13 and 14, mainframe address bits 14 and 15) determine the data destination (write) or source
(read) as follows:
SA14
SA13
Source/Destination
a
a
Hardware Registers
a
1
RAM Lower Block (U25)
1
a
RAM Upper Block (U26)
1
1
Not used
Shared Memory addressing is accessed through a set of dual-input multiplexer/latch circuits
(U39-42). The Access Select flip-flop (U19 pin 9) selects the memory address from the main-
frame or interface CPU, then latches the address (U16 pin 3) to maintain proper signals during
the memory cycle.
Read/Write Control
The mainframe read/write control line is buffered through the same multiplexer/latch circuits
that handle memory addresses. U39 pin 15 carries mainframe read/write control (U39 pin 2)
during mainframe memory accesses, and is held inactive during Z-80A accesses (U39 pin 3).
The latched mainframe read/write signal controls the direction of the 8-bit bus transceiver (only
the lower 8 bits of the 16-bit bus are used), and drives the 28 (read/write) input of the memory
control multiplexer (U32).
The Z-80A read/write control line (ZRD) controls the direction of the shared data bus transceiv-
er (U45), and drives the 2A (read/write) input of the memory control multiplexer (U32 pin 5).
The Access Select flip-flop determines which input (2A or 28) is used to drive the shared read
(SRD) output which, when gated with shared memory timing clocks from U17, controls the
RAM write enable (SWR) line.
Clock Circuits
The 7.3728 MHz oscillator drives a pair of flip-flop frequency dividers (U19 pins 1-6 and U15
pins 1-6) to generate symmetrical timing pulses at 1/2 and 1/4 the clock frequency, respectively.
The 3.6864 MHz System Clock output (TP5) is also used to drive the Z-80A clock input after
being waveshaped by Q1, Q2, and their associated circuitry. The output of the second divider
(U15 pin 6) produces a 1.8432 MHz frequency reference for the CTC chip which generates
baud rate timing signals for the SIO chip. CTC timing signals are fed to the SIO chip through the
baud rate multiplexer (U11).
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