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Table 1-4.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Reserved
Input
DP0
Input/Output
EXT_BR2
Input
IRQ1
Input
DP1
Input/Output
EXT_BG2
Output
IRQ2
Input
DP2
Input/Output
EXT_DBG2
Output
IRQ3
Input
DP3
Input/Output
EXT_BR3
Input
System Bus, HDI16, and Interrupt Signals
The primary configuration is reserved.
1
Data Parity 0
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity zero pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 0 and D[0–7].
1,2
External Bus Request 2
An external master asserts this pin to request bus ownership from the internal
arbiter.
1
Interrupt Request 1
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
1
Data Parity 1
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity one pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 1 and D[8–15].
1,2
External Bus Grant 2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
1
Interrupt Request 2
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
1
Data Parity 2
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity two pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 2 and D[16–23].
1,2
External Data Bus Grant 2
The MSC8101 asserts this pin to grant data bus ownership to an external bus
master.
1
Interrupt Request 3
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
1
Data Parity 3
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity three pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 3 and D[24–31].
1,2
External Bus Request 3
An external master asserts this pin to request bus ownership from the internal
arbiter.
Description
1-13
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