Panasonic 3DO FZ-1 Service Manual page 17

FZ-1
FZ-1
Continued (IC120)
Continued (IC120)
Continued IC100
Pin 1/0 Pin Name
Comment
No.
82 1/0, TTL D8
83
1/0, TTL D9
84 1/0, TTL D10
85 1/0, TTL D11
86
1/0, TTL D12
87 1/0, TTL D13
88 1/0, TTL D14
89 1/0, TTL D15
90 1/0, TTL D16
91 1/O, TTL D17
92 1/O, TTL
D18
93 1/0, TTL D19
94 1/0, TTL D20
95 1/O, TTL D21 Data Bus
96 1/0,TTL D22 Data Bus
97 1/0, TTL D23 Data Bus
98 1/0, TTL D24 Data Bus
99 1/O, TTL D25 Data Bus
100 1/O,TTL
D26
Data Bus
1~120
Continued IIC1201
Pin 1/0 Pin Name
Comment
No.
18 Out, TTL CLC0
Device conlrol code
'1'
19 Out, TTL PBCLK Conlrol port serial clock
20
Out, TTL PBDOUT Conlrol port serial data output
21 In, TTL PBDIN
Control port serial data input
22 In, TTL, DIAGRQ- Olag. test request input
w/null-uo
23 In, TTL PCSC- Pixel sync signal
24 In, TTL DMAREQ DMArequest
25 Vss
26 In, X25MIN
Main clock input
CMOS
27 Vdd
28 In, XV25M Video clock input
CMOS
29 In, TTL CREADY- Device control hand shake signal
30 In, TTL, RESET- Master reset signal input
w/null-uo
31 Out, TTL PDCS3- Chip select for slow device 3
32 Vss
33
Out. TTL
PDCS2- Chip select tor slow device 2
34 Out, TTL SRAMW-
SRAM Write signal
35 Out, TTL SRAMR- SRAM Read signal
36 Out, TTL PDCSO- Chip select tor slow device 0
37 Out, TTL PDWR-
Write signal tor slow bus
38 Out, TTL PDRD- Read signal for slow bus
Svstem IC MADAM IP/N: DA1205FDBX0ZI
Pin 1/0 Pin Name Comment
Pin 1/0 Pin Name
Comment
No.
56 Out, XOUT
Crystal Oscillator input for X25M
s=ial
57 In, TTL A3 CPU address 2
3
58 Vss
59 Vdd
60 In, TTL A4 CPU address
2"
61 In, TTL AS
CPU address 2'
62 In, TTL A6
CPU address
i'
63 In, TTL A7
CPU address 2
7
64 In, TTL
A8
CPU address
i'
65 In, TTL A9 CPU address
'l"
66
In, TTL
A1O CPU address 2
1
"
67 In, TTL A11 CPU address 2
1
'
68 In, TTL A12 CPU address 2
12
69 In, TTL
A13 CPU address 2
13
70 In, TTL A14
CPU address 2
14
71 In, TTL A15
CPU address 2
10
72 In, TTL A16 CPU address 2
10
73 In, TTL AO CPU address
i'
74 In, TTL A1 CPU address 2
1
75 In, TTL A17 CPU address 2"
76 In, TTL A18
CPU address 2
1 •
77 In, TTL A19 CPU address 2
1
"
Pin
1/0
Pin Name Comment
No.
96 Vss
97 Vdd
98
Out, TTL
ABORT CPU
Abort
signal
99 In, TTL SEQ
CPU Sequential signal
100 In, TTL MREQ-
CPU Memory Request signal
101 In, TTL READ- CPU Read-/Wrile signal
102
Vss
103 In, TTL OPC- CPU OPC- signal
104 Out, TTL MCLK CPU clock
105
Vdd
106 In, TTL BYTE-
CPU Byle-/Word signal
107 Out, TTL DBE CPU Data Bus Enable signal
108 Vss
109 In, TTL CPI-
CPU CPI- signal
110 In, TTL LOCK CPU LOCK signal
111 Out, TTL CPA CPU CPA signal
112 Out, TTL MCLK2 CPU clock (copy of MCLK)
113 Vss
114 1/0, TTL
DO Main system data bus
115 1/0, TTL D1 Main system dala
bus
2
1
116 1/O, TTL D2 Main system dala bus
117 1/O, TTL D3 Main system dala bus 2
118 Vss
39 Vss
40 1/0, TTL PD0 Data bus
'1'
tor slow devices
41 1/0, TTL PD1 Data bus 2
1
for slow devices
42 1/0, TTL PD2 Data bus
'i'
for slow devices
43 1/0, TTL PD3 Data bus 2> for slow devices
44 Vdd
45 1/0, TTL
PD4 Data bus
2"
for slow devices
46
1/0, TTL
PD5 Data bus 2
5
for slow devices
47 1/0, TTL PD6 Data bus
i'
for slow devices
48 1/0, TTL PD7 Data bus 2 for slow devices
49 Vss
50 Out, TTL ROMCS- ROM Chip Select signal
51 Out. TTL SIPDEL Stalus output
52 A2 CPU address
'i'
53 Out, TTL X25M X25M clock output
54
Vss
55 In. XIN Cryslal Oscillator input for X25M
SnPrial
No.
1 Out, TTL RA10 Right pert
memory
address 210
2 Out, TTL RA9 Right
pert memory
address
'l9
3 Out, TTL RA8 Right pert memory address
;ii'
4 Out, TTL
RAO
Right part memory address
i'
5 Oul TTL RA7 Right
pert
memory address 2
7
6 Vss
7 Out, TTL RA1 Right part memory address 2
8 Out, TTL RA6 Right part memory address
i'
9
Oul TTL RA2
Right part memory address
'i'
10 Out, TTL RAS Right part memory address 2•
11
Vss
12 Out, TTL RA3 Right part memory address 2
3
13 Out, TTL RA4 Right part memory address
2"
14 Vdd
15 Oul TTL
CLC2
Device control code 2'
16 Out, TTL CLC1 Device control code
2 1
17 Vss
78 Vss
79 Vdd
80 In, TTL A20
CPU address
2""
81 In, TTL A21 CPU address
2"'
82 In, TTL A22 CPU address
2''
83 In, TTL A23 CPU address
2"'
84 In, TTL A24 CPU address
2''
85 In, TTL A25 CPU address
2''
86
In, TTL A26
CPU address
:12 6
87 In, TTL A27 CPU address
2"'
88
In, TTL A28 CPU address
2""
89 In, TTL A29 CPU address
2''
90 In, TTL A30 CPU address 2'°
91 In, TTL A31 CPU address 2"
92 In, TTL TRANS-
CPU TRANS signal
93 Out, TTL CPBUSY CPU BUSY signal
94 Out, TTL CPURES- CPU Reset signal
95 In, TTL
MIRO- lnlerrupt request input
119 1/0, TTL D4 Main SfSlem dala bus
120 1/0, TTL D5 Main system dala bus 2
121 Vdd
122 1/0, TTL D6 Main system dala bus
123 1/0, TTL D7
Main system dala bus 2
124 Vss
125 1/0, TTL DB Main system data bus
126 1/0, TTL 09 Main system data bus
127 1/0, TTL D10 Main system data bus 2
1 0
128 1/0, TTL D11 Main system dala bus 2
1 1
129 Vss
130 1/0, TTL D12
Main system dala bus 2
1
131 1/0, TTL D13 Main system data bus 2
1
132 1/0, TTL D14 Main system dala bus 2
14
133 1/0, TTL D15 Main system dala bus 2
1
134 Vss
135 110, TTL
D16
Main system dala bus 2
1
2-19
2-20