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Curtiss-Wright CHAMP-AV8 Hardware User Manual

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  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 K2V 1A6 (613) 599-9199 PROPRIETARY NOTICE: This document is the property of Curtiss-Wright Controls Inc. (CW Controls) and shall not be copied or used, in whole or in part, without prior written permission from CW Controls. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 Updated section, “General Description” on page 1-2. Updated section, “Feature Summary” on page 1-3. Updated Figure 1.2, “CHAMP-AV8 Functional Block Diagram,” on page 1-5. Updated “Quad-Core Intel Core i7 Processors” on page 1-6. Updated Figure 1.3, “CHAMP-AV8 PCI Express Distribution,” on page 1-7.
  • Page 4 Updated Table A.4, “P0 Utility Connector Signal Definitions,” on page A-15. Updated Table A.39, “RTM SW2–SW18 Functions,” on page A-57. Added two notes to Appendix A, "Rear Transition Module (RTM) Configuration Switches". Updated Table B.1, “Memory Devices Available On The CHAMP-AV8,” on page B-2. 826448 V 2015...
  • Page 5 The proprietary information contained in this document must not be disclosed to others for any purpose, nor used for manufacturing purposes, without written permission of Curtiss-Wright Controls, Inc. The acceptance of this document will be construed as an acceptance of the foregoing condition.

  • Page 6: Table Of Contents

    URTISS RIGHT ABLE OF ONTENTS ABLE OF ONTENTS Preface ............................xiii Purpose ........................... xiii Audience..........................xiii Scope ............................xiii Documentation Roadmap ......................xiv Related Software Documents ...................... xiv Reference Documentation ......................xv Conventions Used in this Manual ....................xvi Technical Support Information ..................... xx 1.
  • Page 7 CHAMP-AV8 P0 Utility Connector Pin Assignments ............... A-14 Corresponding VPX Backplane J0 Utility Connector Pin Assignments ..........A-16 CHAMP-AV8 P1 (SRIO Fabric) Connector Pin Assignments ............A-17 Corresponding VPX Backplane J1 (SRIO Fabric) Connector Pin Assignments........A-19 CHAMP-AV8 P2 (PCIe Expansion) Connector Pin Assignments ............A-20 Corresponding VPX Backplane J2 (PCIe Expansion) Connector Pin Assignments ......
  • Page 8 RIGHT ABLE OF ONTENTS CHAMP-AV8 P3 (XMC Site’s PMC User I/O) Connector Pin Assignments ...........A-23 Corresponding VPX Backplane J3 (XMC Site’s PMC User I/O) Connector Pin Assignments ....A-25 CHAMP-AV8 P4 (Basecard I/O) Connector Pin Assignments ............A-26 Corresponding VPX Backplane J4 (Basecard I/O) Connector Pin Assignments ........A-29 CHAMP-AV8 P5 (XMC User I/O) Connector Pin Assignments ............A-30...
  • Page 9 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT 826448 V 2015 VIII ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 10 VPX RT2 Wafer Routings ....................A-5 Figure A.4: CHAMP-AV8 Backplane P0-P6 Connector Orientation ............A-7 Figure A.5: I/O Mapping to the CHAMP-AV8 VITA 46 Connectors............A-8 Figure A.6: CHAMP-AV8 Pinout Configurator Main Window ..............A-11 Figure A.7: Sample P5 Pinout Table ....................A-12 Figure A.8:...
  • Page 11 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 12 CHAMP-AV8 Weight ......................1-33 Table 1.9: VPX6-462-A Air-Cooled Ruggedization Levels ............... 1-34 Table 1.10: VPX6-462-C Conduction-Cooled Ruggedization Levels ............1-34 Table 1.11: Summary of CHAMP-AV8 Connectors, Functions Supported ............ 1-39 Table 2.1: Voltage and Current Requirements ..................2-3 Table 2.2: Maximum Supply Current for XMC Site ..................2-5 Table 2.3:...
  • Page 13 Table A.43: RTM Geographical Address (P12) Pin Assignments ..............A-61 Table A.44: XMC Single Ended I/O (JB6) Pin Assignments ..............A-62 Table A.45: RTM XMC Differential User I/O (J7) Pin Assignments ............. A-63 Table B.1: Memory Devices Available On The CHAMP-AV8 ..............B-2 826448 V 2015 ROPRIETARY...

  • Page 14: Preface

    RIGHT REFACE URPOSE This manual describes the OpenVPX (VITA 65) based CHAMP-AV8 and applies to L0 (commercial) and L100/L200 (air-cooled and conduction-cooled) products. When differences exist between these versions of the product, the differences will be noted. After explaining the capabilities of the CHAMP-AV8, the manual provides the procedure for installing it and checking its operation.

  • Page 15: Documentation Roadmap

    ELATED OFTWARE OCUMENTS For information on installing the CHAMP-AV8 software, refer to the CHAMP-AV8 Linux BSP Software User’s Manual, Curtiss-Wright document number 826449. Alternatively, installation information can be found in the CHAMP-AV8 VxWorks BSP Software User’s Manual, Curtiss-Wright document number 826452.

  • Page 16: Reference Documentation

    URTISS RIGHT EFERENCE OCUMENTATION Refer to the following standards for information about the specifications the CHAMP-AV8 is designed for compliance with: • VITA 46.0-2007 - Advance Module Format, R1.2 • VITA 46.3 - 4x Serial RapidIO Signal Mapping for VITA 46, Revision 0.5 •...

  • Page 17: Conventions Used In This Manual

    These conventions cover typography for such elements as sample software code and keystrokes, signal meanings, and graphical elements for important information such as warnings or cautions. The generic product name “CHAMP-AV8” is used throughout this manual to represent the Product Naming following more specific product variants: Conventions •...
  • Page 18 Abbreviation Convention 1 Kbyte 1,024 bytes 1 Mbyte 1,024 Kbytes 1 Gbyte 1,024 Mbytes The following is a list of acronyms associated with the CHAMP-AV8 product: Acronyms Alternating Current ANSI American National Standards Institute Anti-Tamper Built-In Test Baseboard Management Controller...
  • Page 19 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface JTAG Joint Test Action Group Light Emitting Diode Local Processor Block Low Pin Count MBSC Multi-Board Synchronous Clock MTBF Mean Time Between Failures...
  • Page 20 The following icons are used throughout the documentation package: Icons Tips provide extra information on the subject matter. This could include hints about how to use your current Curtiss-Wright card to its maximum potential. This is a note. The note icon highlights exceptions and special information. Note This is a caution.

  • Page 21: Technical Support Information

    Once registered, you will have online access to additional or updated technical documentation, in addition to software components, etc. as these items become available. For Technical Support and Repair and Warranty services information, go to the Curtiss-Wright To Access web site:...

  • Page 22: Product Overview

    RODUCT VERVIEW HAPTER This chapter discusses the high-level features of the CHAMP-AV8 product. The following topics are discussed: • “General Description” on page 1-2 • “Feature Summary” on page 1-3 • “Technical Description” on page 1-5 – “Quad-Core Intel Core i7 Processors” on page 1-6 –...

  • Page 23: General Description

    SDRAM per node, the CHAMP-AV8 handles applications with demanding storage, data logging and sensor processing needs. The CHAMP-AV8 is supported with an extensive suite of software, including support for Linux and VxWorks. Under the VxWorks OS, the Continuum Interprocessor Communication (IPC) and Continuum Vector SSE optimized signal processing libraries are also available.

  • Page 24: Feature Summary

    URTISS RIGHT RODUCT VERVIEW Figure 1.1: Air-Cooled CHAMP-AV8 Isometric View REAR ISOMETRIC FRONT ISOMETRIC EATURE UMMARY • Two Intel® Core™ i7 second (i7-2715QE) or third (i7-3612QE) generation processors running at up to 2.1GHz • Hyper-threading technology • Up to 269 GFlops computing performance •...
  • Page 25 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT • 8GB NAND flash on SATA per processor • Protected backup boot flash • 256 KB NVRAM • Secure write-protection on all non-volatile memory • De-classify function to erase non-volatile memory •...

  • Page 26: Technical Description

    RIGHT RODUCT VERVIEW ECHNICAL ESCRIPTION With reference to the high level block diagram illustrated in Figure 1.2 below, the operation of the CHAMP-AV8 is described in the following sections. Figure 1.2: CHAMP-AV8 Functional Block Diagram NVRAM Power Sync Watchdog 256KB...

  • Page 27: Quad-Core Intel Core I7 Processors

    ORE I ROCESSORS The CHAMP-AV8 incorporates two second or third generation Intel Core i7 quad-core processors, which are a low power embedded implementation of micro-architecture code name Sandy Bridge. A major advancement for DSP applications is the introduction of the 256-bit AVX floating-point instructions.

  • Page 28: Pci Express Architecture

    XPRESS RCHITECTURE The CHAMP-AV8 makes use of the PCIe interfaces included in the CPU to share and transfer data between the processors, between cards via the P2 Expansion Plane connectors, and to communicate with the XMC site, as shown in Figure 1.3 below.
  • Page 29 URTISS RIGHT The standard XMC connector defined by VITA 42.0-2008, and used on the CHAMP-AV8, is rated for signalling rates of at least 3.125GHz. The CHAMP-AV8 is designed to maximize signal integrity; however, PCIe Gen 2 speeds (5GHz) are not guaranteed to properly function to the XMC site.

  • Page 30: Figure 1.4: Pcie Switch Partitions

    PCIe are mixed. For example, when mixing older hardware boards such as the VPX6-185 or the CHAMP-AV6 with the CHAMP-AV8, the off-board PCIe links can establish a common link speed in order to communicate. However, PCIe link speed and other off-board PCIe signal parameters can be set to discrete values using BIOS settings.

  • Page 31: Srio Fabric

    SRIO F ABRIC The CHAMP-AV8 provides PCIe-SRIO bridge devices and an SRIO Gen2 switch to connect the SRIO backplane fabric with the Intel Processors. Each processor connects to either one or two PCIe-SRIO bridges providing up to 8 GB/s total bandwidth on-board. An 8-port SRIO switch is connected to the processors and the four ports on the data plane connector via the PCIe-SRIO bridges.

  • Page 32: Figure 1.5: Champ-Av8 Srio Port Connections

    CHAMP-AV6 (which support Gen 1 speed, 3.125 Gbaud) with the CHAMP-AV8 (defaults to Gen 2, 5.00 Gbaud, but supports 3.125 Gbaud) the off-board SRIO link speed must be set to values supported on both boards. In this case the CHAMP-AV8 would be Note down-graded to the Gen 1 speed.

  • Page 33: Core Functions Fpga

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT FPGA UNCTIONS The Core Functions FPGA (CF-FPGA) is illustrated in block diagram format below in Figure 1.6. Figure 1.6: Core Functions FPGA Block Diagram Project Specific Block (PSB) Clock Gen CLKs IPMI ctrl/status...

  • Page 34: Double Data Rate (Ddr3) Sdram With Ecc

    OUBLE WITH Each processor node on the CHAMP-AV8 supports up to 4GB of DDR3 SDRAM for a total of 8GB on the board. Each processor features two DDR3 memory channels. With two channels of DDR3-1333, each processor achieves a peak memory bandwidth of over 21GB/s. The memory is protected with Error Checking and Correcting (ECC) circuitry that can detect and correct all single-bit errors and detect all double-bit errors.

  • Page 35: Protected Boot Flash Memory

    LASH EMORY The CHAMP-AV8 features 8 GB of NAND flash per processor (16 GB total per CHAMP-AV8) for storage of the operating system and user application software. A SATA interface connects the PCH to a NAND flash-based Solid State Drive (SSD). Software accesses the flash via the operating system file system.

  • Page 36: Non-Volatile Ram (Nvram)

    "Statement of Memory Volatility" for details of memory devices present on the CHAMP-AV8. XMC S The CHAMP-AV8 is equipped with one XMC site, as a build option, that provides additional user I/O on a P14 connector. This site complies with ANSI/VITA 42.0 and ANSI/VITA 42.3.

  • Page 37: Utility Features, Semaphores, Timers

    The CHAMP-AV8 provides six general purpose 32-bit timers. These may be configured for a timeout value between 20ns and 85 seconds, with a resolution of 20ns. Each timer may be configured to generate an interrupt to either processor.

  • Page 38: Multi-Board Synchronous Clock

    EIA-232/422/DDIO Control On the CHAMP-AV8, processor node A has access to four UARTs, and node B has access to three. Two UART ports on each node (A1/A0/B1/B0) are connected to on-board EIA-232/422 transceiver integrated circuits. The EIA-232/422 IC is a dual mode device which can be configured either as (4 x EIA-232) or (2 x EIA-422) transceivers.

  • Page 39: Figure 1.8: Champ-Av8 Serial Port Implementation

    EIA-422 differential pair, thus forming a DDIO (Differential DIO) port. Figure 1.9, “CHAMP-AV8 Serial Port Detail,” on page 1-19 illustrates how the control registers are used to control switching between the DIO registers, UART ports, and the EIA-232/422 dual-mode transceiver.

  • Page 40: 1000Base-T Ethernet

    THERNET Each processor on the CHAMP-AV8 is equipped with a 10/100/1000Base-T Gigabit Ethernet interface. On air-cooled versions of the CHAMP-AV8, the Ethernet ports are available at the front panel or backplane connector as a build-time option. For conduction-cooled versions, Ethernet is available via the backplane only.

  • Page 41: 1000Base-Bx Ethernet

    Redrivers are supplied on the CHAMP-AV8 to allow link tuning. SATA I NTERFACES The CHAMP-AV8 has a total of three USB 2.0 interfaces. Each processor has a USB interface USB Interfaces routed to the VPX P6 connector, which is available through the USB/eSATA connector on RTM6-462-000.

  • Page 42: Lvttl Discrete Digital I/O

    ISCRETE IGITAL The CHAMP-AV8 provides the capability to control the outputs of the two drivers on the dual-mode EIA-232/422 transceivers which are normally controlled by UARTs A0/B0. In a similar fashion, there are registers that can read the state of the EIA-232/422 receivers. In total there are two inputs and two outputs.

  • Page 43: Voltage, Current, And Temperature Sensors

    1-23 show the locations of the card edge and board center temperature sensors provided on the top and bottom of the CHAMP-AV8 board. The usage of these sensors is described in the BSP manuals. The internal temperature sensor monitoring channels are realized through the use of embedded sensors inside of ADT7461 sensing devices.

  • Page 44: Indicator Leds

    Channel 2 Internal NDICATOR The CHAMP-AV8 provides eight user-controllable green LEDs. These are visible on the front panel of air-cooled boards or on the back side of conduction-cooled boards. There is an additional red LED on the front panel of both versions that indicates a failure determined by the on-board diagnostic firmware.

  • Page 45: Cables And Rear Transition Modules

    RTM provides connectors for Gigabit Ethernet (2), EIA-232 (4), EIA-422/485 (2), and USB/eSATA (2). The RTM also features a number of switches and headers for access to other CHAMP-AV8 signals and I/O ports. The RTM is intended for development purposes and is not tested or warranted for deployment.

  • Page 46: Figure 1.12: Champ-Av8 Interrupt Controller Block Diagram

    URTISS RIGHT RODUCT VERVIEW Figure 1.12: CHAMP-AV8 Interrupt Controller Block Diagram Interrupt Controller To LPC Bus Addr/Data/Ctrl PIRQ To PCH SERIRQ SERIRQ SERIRQ I/F Mapping Bus I/F to LPC Block Interrupt Interrupt Queue 1 Queue 2 IRQ-0 IRQ-1 IRQ-2 IRQ-3 IRQ-4...
  • Page 47 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT The incoming interrupts consist of two different types: • Unlatched Interrupts - Status is visible in "Read-Only" interrupt status registers. These interrupts are cleared at the source function. • Latched Interrupts - Status is visible in and also cleared with "Read / Write-Clear" reg- isters.
  • Page 48 URTISS RIGHT RODUCT VERVIEW Each interrupt line within a source group is routed to a status register, but first passes through Interrupt Routing test assertion and enabling logic. If latching is enabled for that bit, the status register latches the edge of the interrupt pulse and holds the condition until cleared by a write to the status register.

  • Page 49: Figure 1.13: Interrupt Routing Block (Part A)

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Figure 1.13: Interrupt Routing Block (Part A) Source Enable Test Reg Stat Reg Mask Reg INT_SRC0[0] GROUP_INT0 Latch INT_SRC0[n] Source Enable Test Reg Stat Reg Mask Reg INT_SRC7[0] GROUP_INT7 Latch INT_SRC7[n] Source...

  • Page 50: Figure 1.14: Interrupt Routing Block (Part B)

    URTISS RIGHT RODUCT VERVIEW Figure 1.14 below shows how each GROUP_INTx line feeds to each of the 13 IRQ outputs. Each of the 16 GROUP_INTx lines can be individually enabled to feed into a particular IRQ via a MST Enable Register. After the enable register, each bit status is sampled and fed to a MST Status Register.
  • Page 51 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Each enabled interrupt event for IRQ0-1 will generate a message vector which will be stored Interrupt in the interrupt message FIFO. There is a separate FIFO for each IRQ. Only edge-mode Messaging FIFO interrupts are supported, and software must ensure that only edge-mode interrupts are routed to these IRQs.

  • Page 52: Specifications

    URTISS RIGHT RODUCT VERVIEW PECIFICATIONS The CHAMP-AV8 board meets the specifications outlined in the following sections. VPX C OMPLIANCE ANSI/VITA 46.0-2007, VITA 46.3, ANSI/VITA 46.9-2010, ANSI/VITA 65-2010. Table 1.4: VPX Compliance Summary Mode Profile Supported Module profile (pinout) MOD6-PAY-4F1Q2U2T-12.2.1-11/12 Slot profile SLT6-PAY-4F1Q2U2T-12.2.1...

  • Page 53: Power Requirements

    Notes: 1. Power consumption (Watts) will vary depending on processor frequency, application usage, and ambient temperature. 2. ±12VAux for XMC only (not used by CHAMP-AV8 basecard). 3. Vs3 (+5.0 VDC) is not used by the CHAMP-AV8. 4. VBAT is optional. VBAT sources current only when the board is shutdown or main power is “off”.

  • Page 54: Dimensions

    URTISS RIGHT RODUCT VERVIEW IMENSIONS Table 1.7 lists the physical dimensions of the CHAMP-AV8. Table 1.7: CHAMP-AV8 Dimensions Parameter Dimensions Height 233.2 mm (9.181 in.) Depth 159.8 mm (6.293 in.) Notes: 1. Front panel hardware on air-cooled modules includes: injector/extractor handles, EMC strip, alignment pin, and keying provisions in accordance with ANSI/VITA 1.1, American...

  • Page 55: Ruggedization Levels

    ’ ARDWARE ANUAL URTISS RIGHT UGGEDIZATION EVELS Listed below are the Curtiss-Wright ruggedization levels available for the CHAMP-AV8. Table 1.9: VPX6-462-A Air-Cooled Ruggedization Levels Level 0 Level 100 0 °C to 50 °C -40 °C to 71 °C Operating Inlet Air Temperature -40 °C to 85 °C...

  • Page 56: Physical Characteristics

    HARACTERISTICS Figure 1.15 shows the location of the major components and the mating connectors on the top side of the CHAMP-AV8 (some hardware has been removed from this drawing to make all of the components visible). All ruggedization levels of the CHAMP-AV8 board have a thermal shunt that covers some of the components.

  • Page 57: Figure 1.16: Champ-Av8 Board Layout-Secondary Side

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Figure 1.16: CHAMP-AV8 Board Layout—Secondary Side Node A NAND Flash PABS 1000 Node B Base-X NAND 1-36 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 58: Vpx6-462-A Front Panel

    VERVIEW An illustration showing the front panel that is mounted on the air-cooled version of the VPX6-462-A CHAMP-AV8 (also known as the VPX6-462-A) is provided below, along with a brief description Front Panel of the indicators and connectors it provides.

  • Page 59: Location Of Status Leds On Conduction-Cooled Variant

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT LEDS OCATION OF TATUS ONDUCTION OOLED ARIANT For conduction-cooled variants, the Processor Status LEDS, the Fail LED and the Thermal Failure LED, are all mounted on the top-side of the board assembly, as shown in Figure 1.17 below.

  • Page 60: Mating Connectors

    VERVIEW ATING ONNECTORS Table 1.11 summarizes these connectors, providing a brief description and an indication of what functions/interfaces are supported by each. Table 1.11: Summary of CHAMP-AV8 Connectors, Functions Supported Connector Description Supported I/O Configurations Designation 26-pin front panel The J1 connector provides two serial interfaces, one to each processor node, desig- connector nated A0 and B0.

  • Page 61: Overview Of Available Software

    YSTEM OFTWARE The CHAMP-AV8 is supported with an extensive array of software items, which cover all facets of developing application code for the board. Users have the option of choosing to develop with a variety of operating systems and development tools. The following operating systems are supported on the CHAMP-AV8.

  • Page 62: Continuum Vector™ Library

    ECTOR IBRARY The CHAMP-AV8 derives its floating-point performance from the Intel AVX vector processing unit. Available for both Linux and VxWorks OS platforms, the Continuum Vector Library provides over 200 functions optimized for the SSE unit, providing the foundation for most signal processing applications.
  • Page 63 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT 1-42 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 64: Pre-Installation Tasks

    NSTALLATION ASKS HAPTER This chapter discusses the following topics: • “Unpacking the Card” on page 2-2 • “Checking Hardware Requirements” on page 2-2 – “Chassis Requirements” on page 2-2 – “Backplane Requirements” on page 2-2 – “Detailed Power Requirements” on page 2-3 –...

  • Page 65: Unpacking The Card

    2. Find the packing list. Make sure all the items on the list are present. 3. Save the packing material for storing or reshipping the card. 4. If your CHAMP-AV8 was shipped with an XMC module installed, make sure it is firmly attached to the basecard.

  • Page 66: Detailed Power Requirements

    NSTALLATION ASKS ETAILED OWER EQUIREMENTS The CHAMP-AV8 requires +12 V and +3.3 V power supplies in order to operate. Table 2.1 shows the voltage and current requirements for the CHAMP-AV8. Table 2.1: Voltage and Current Requirements Power Supply Requirements Mnemonic...

  • Page 67: Bios Configuration Parameters

    NSTALLATION EQUIREMENTS The CHAMP-AV8 provides one XMC only site. This site is located on the on the top of the card and is supported by connectors J14, J15 and J16. See Figure 1.6, “Core Functions FPGA Block Diagram,” on page 1-12 for an illustration of the CHAMP-AV8 board layout.
  • Page 68 Table 2.2, along with their maximum supply currents. These maximum supply Power Considerations currents are specified by VITA 42 at 1 Ampere per XMC connector pin. The CHAMP-AV8 is capable of providing these currents. Performance of the CHAMP-AV8 may be impacted by a specific XMC card installed on the XMC site.

  • Page 69: Cable Requirements

    RIGHT ABLE EQUIREMENTS A Front Panel interface cable is available to support the CHAMP-AV8. This cable is identified as: • CBL-462-FPL-000 (CHAMP-AV8 Standard Front Panel Cable Assembly - see Figure 2.1) Figure 2.1 shows a cable drawing of the CHAMP-AV8 Standard Front Panel Cable Assembly CBL-462-FPL-000 (CBL-462-FPL-000).

  • Page 70: Configuring Jumpers

    ONFIGURING UMPERS Table 2.3 defines the jumpers (JB1 - JB11) on the CHAMP-AV8 that reside at the front of the board near the LEDs (see Figure 2.2 on page 2-8). Jumpers are available for selecting various board operational modes. Jumpers identified as Reserved must be left in the default setting and only changed under the direction of Customer Support.

  • Page 71: Figure 2.2: Configuration Jumper Locations

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Figure 2.2: Configuration Jumper Locations MMB2 MMB1 XMC SITE 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 72: Hardware Installation

    ARDWARE NSTALLATION HAPTER This chapter provides the following information and procedures: • “Installation Prerequisites” on page 3-3 – “Installation Checklist” on page 3-3 – “Unpack and Configure the Card” on page 3-3 – “Install the XMC Module on the Basecard” on page 3-3 –...

  • Page 73: Introduction

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT NTRODUCTION This chapter provides the following information and procedures: • summary of installation prerequisites • quick installation and power-up procedure • detailed installation procedure • displaying the initial screen message; and •...

  • Page 74: Installation Prerequisites

    URTISS RIGHT ARDWARE NSTALLATION NSTALLATION REREQUISITES Before installing the CHAMP-AV8 in your chassis, please take a moment to review the following items and planning considerations: NSTALLATION HECKLIST Make sure you have the following items before proceeding with the installation: •...

  • Page 75: Choose A Vpx Slot Location

    HOOSE A OCATION If you want the CHAMP-AV8 to be the System Controller (SYSCON), install it in a slot that has a jumper allowing it to be the System Controller slot. If you are using another card as the SYSCON, the CHAMP-AV8 may be installed in any unoccupied slot.

  • Page 76: Connect A Terminal

    In order to access the features available within the embedded firmware on the CHAMP-AV8, you’ll need to attach a terminal or PC-emulated equivalent to the Node A Serial Port 0 interface on the card. You can connect a terminal to the CHAMP-AV8 in one of the following ways: •...

  • Page 77: Connect Ethernet Ports

    • by wiring directly to the appropriate VPX P4 backplane connector pins. The CHAMP-AV8 provides twelve LEDs on the bottom side of the PWB that provide link status Ethernet LEDs and activity information for the Ethernet 1000 Base-T and 1000 Base-X ports. See Figure 3.1 on page 3-7 for details.

  • Page 78: Figure 3.1: Location Of Champ-Av8 Ethernet Activity Leds

    URTISS RIGHT ARDWARE NSTALLATION Figure 3.1: Location of CHAMP-AV8 Ethernet Activity LEDs Node A Node B Node A Node B 1000Base-T 1000Base-T 1000Base-BX 1000Base-BX SOLDER SIDE (SECONDARY) SHOWN 826448 V 2015 ERSION ARCH ROPRIETARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 79: Cbl-462-Fpl-000 Front Panel Cable Connections

    (as well as the VPX P0 through P6 interfaces). The CHAMP-AV8 front panel cable is different than that used on the CHAMP-AV6, even though the physical front panel connector is the same. To use the CHAMP-AV8 front panel, the user must employ CBL-462-FPL-000. Caution...
  • Page 80 Comments RS232_B0_TX RS232_B0_RX RS232-GND The CHAMP-AV8 serial ports do not provide access to the CTS and RTS signals. Therefore, software handshaking (XON/XOFF) must be used. Note The CHAMP-AV8 EIA-232 serial channels are configured as DCE (Data Communications Equipment). The EIA-232 serial channels on personal computers and terminals are configured as DTE, therefore a null modem is NOT required for communication between the CHAMP-AV8 and a PC terminal.
  • Page 81 Twisted pair 4 ENET_B_TRD_N3 Twisted pair 4 When connected to the front panel of the CHAMP-AV8, CBL-462-FPL-000 provides access to a Front Panel Cable reset function via the SW1 Pushbutton on the cable. The pin assignments of SW1 pushbutton SW1 Reset...

  • Page 82: Booting: Entering The Bios Setup Utility

    Because the CHAMP-AV8 does not contain a video port, a serial terminal is required for communication during the board boot process. See “Connect a Terminal” on page 3-5 for details.

  • Page 83: Initiate The Power-Up Sequence

    Enter Boot Manager – Press F12 function key (USB keyboard only). Refer to the CHAMP-AV8 BIOS Setup Utility Software User’s Manual (document 826450) for more information on the BIOS Setup Utility and Boot Manager. An example of the initial screen message you will see once BIOS has completed is shown in Cross Reference “Display the Initial Screen Message”...

  • Page 84: Figure 3.3: Grub Loading Message

    URTISS RIGHT ARDWARE NSTALLATION ISPLAY THE NITIAL CREEN ESSAGE After power on, you have the option (available for about three seconds) to press the F2 key to activate the BIOS setup utility. If you don’t press the F2 key, then you will see the following GRUB (GRand Unified Bootloader) loading message as follows: Figure 3.3: GRUB Loading Message After a couple of seconds, you will see Linux start loading, ultimately concluding with the login...

  • Page 85: Troubleshooting

    LED D IAGNOSTICS The CHAMP-AV8 has a front panel red Fail LED, eight front panel green Processor Status LEDs (air-cooled boards only), and eight green surface-mount LEDs. During the board power-up and reset sequences, the LEDs provide board diagnostic information.
  • Page 86 URTISS RIGHT ARDWARE NSTALLATION Table 3.7: Summary of LED Behavior Location Reference Color Behavior during Behavior during Designator Purpose/ Normal Operation or Abnormal Operation Function Feature in Use or Feature Not in Use Front Panel – A0 (DS28-1) Green Processor status ON –...
  • Page 87 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Table 3.7: Summary of LED Behavior (Continued) Location Reference Color Behavior during Behavior during Designator Purpose/ Normal Operation or Abnormal Operation Function Feature in Use or Feature Not in Use Top of PWB...
  • Page 88 URTISS RIGHT ARDWARE NSTALLATION Table 3.7: Summary of LED Behavior (Continued) Location Reference Color Behavior during Behavior during Designator Purpose/ Normal Operation or Abnormal Operation Function Feature in Use or Feature Not in Use Bottom of Green PCIe switch port 16 ON –...
  • Page 89 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Table 3.7: Summary of LED Behavior (Continued) Location Reference Color Behavior during Behavior during Designator Purpose/ Normal Operation or Abnormal Operation Function Feature in Use or Feature Not in Use Bottom of...

  • Page 90: Led Start-Up Sequence (Power On)

    URTISS RIGHT ARDWARE NSTALLATION Table 3.7: Summary of LED Behavior (Continued) Location Reference Color Behavior during Behavior during Designator Purpose/ Normal Operation or Abnormal Operation Function Feature in Use or Feature Not in Use Bottom of Green 1000Base-BX Reserved Reserved Bottom of Green 1000Base-BX...

  • Page 91: Led Start-Up Sequence (Reset)

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Recovery Boot Mode: flashing Boot Inhibit Mode: flashing LED S TART EQUENCE ESET The reset LED start-up sequence is a follows: 1. Front panel red Fail LED, front panel green Processor Status LEDs, and surface mount Status LEDs all illuminated: –...

  • Page 92: Connector Pin Assignments

    – “CHAMP-AV8 P2 (PCIe Expansion) Connector Pin Assignments” on page A-20 – “Corresponding VPX Backplane J2 (PCIe Expansion) Connector Pin Assignments” on page A-22 – “CHAMP-AV8 P3 (XMC Site’s PMC User I/O) Connector Pin Assignments” on page A-23 – “Corresponding VPX Backplane J3 (XMC Site’s PMC User I/O) Connector Pin Assignments”...
  • Page 93 ARDWARE ANUAL URTISS RIGHT – “CHAMP-AV8 P5 (XMC User I/O) Connector Pin Assignments” on page A-30 – “Corresponding VPX Backplane J5 (XMC User I/O) Connector Pin Assignments” on page A-32 – “CHAMP-AV8 P6 (XMC/DIO/SATA/USB) Connector Pin Assignments” on page A-33 –...

  • Page 94: Connector Overview

    This appendix provides the interface pinout information for each of the connectors on the CHAMP-AV8, and explains how you can use the Pinout Configurator utility to generate custom pinout tables based on the type and location of any XMC modules you choose to install on the basecard.

  • Page 95: Figure A.2: Vpx Rt2 Type Connector

    6.25Gbaud. By default, the CHAMP-AV8 is configured for 5Gbaud SRIO backplane interfaces. The wafer converts a 7-row interface on the “P” (CHAMP-AV8 PWB) side of the connector, to a 9-row interface on the “J” (backplane) side of the connector. Tables for both sides of the connector are provided starting on page A-15 of this appendix.

  • Page 96: Figure A.3: Vpx Rt2 Wafer Routings

    With reference to Figure A.3 below, four types of wafers are used, including power, single ended, or differential (with odd or even routing configurations). The P0 through P6 connectors on the CHAMP-AV8 employ these different wafer types in specific combinations to meet the requirements of the interface.
  • Page 97 RIGHT The backplane P0 provides power supplies, testing, clock, and I2C utilities, etc, for the VPX VPX P0 Utility system. With reference to Figure A.3 on page A-5, the CHAMP-AV8 P0 connector uses the Connector following combination of wafers: Table A.1:...

  • Page 98: Figure A.4: Champ-Av8 Backplane P0-P6 Connector Orientation

    URTISS RIGHT The layout of the VPX P0 through P6 connectors is shown in Figure A.4 below: Figure A.4: CHAMP-AV8 Backplane P0-P6 Connector Orientation VITA 46 Connector Orientation : i h g f e d c b a P0 Wafer 1...

  • Page 99: Champ-Av8 I/O Mapping

    With reference to Figure A.5, the I/O mapping of the various CHAMP-AV8 connectors is summarized in the following sections. Figure A.5: I/O Mapping to the CHAMP-AV8 VITA 46 Connectors The CHAMP-AV8 incorporates one XMC site that populates both the PMC (J14) and the XMC XMC I/O Mapping (J16) I/O connectors.
  • Page 100 XMC Site Single Ended User I/O (38 signals) from XMC J16 connector (XMC_C[19:01] and XMC_F[19:01]) • XMC Site Differential User I/O (8 of the 20 pairs) from XMC J16 connector (XMC_DP[03:00] and XMC_DP[13:10]) See “CHAMP-AV8 P5 (XMC User I/O) Connector Pin Assignments” on page A-30 for additional details. 826448 V 2015 ERSION...

  • Page 101: Using The Champ-Av8 Pinout Configurator

    CHAMP-AV8 P SING THE INOUT ONFIGURATOR The backplane pinouts of the CHAMP-AV8 vary according to the XMC modules installed on the basecard. The Continuum Support Center website (http://csc.cwcdefense.com) provides a Windows utility that generates the pinout configuration based on the modules installed. This utility lets you choose from existing Curtiss-Wright XMC modules, or describe pinouts for third-party or future Curtiss-Wright modules.

  • Page 102: Selecting The Xmc Module

    From the drop-down list, choose the module you have installed (see Figure A.6 on page A-11). If your CHAMP-AV8 has an XMC module installed that is not listed in the drop-down list, refer to “Defining New XMC Modules” on page A-13.

  • Page 103: Generating Pinouts

    RIGHT ENERATING INOUTS 2. To generate a connector pinout table for your CHAMP-AV8, click a Generate Pinout button. The application displays the corresponding pinout table for your configuration, as shown in the example in Figure A.7 below. You may adjust the column widths of the table by dragging the column guides in the header row.

  • Page 104: Saving The Pinout Table

    URTISS RIGHT AVING THE INOUT ABLE 3. To save a pinout table to a text file, click the Save to File button. The Pinout Configura- tor saves the table as a comma-delimited file, in which table cells are separated by com- mas.

  • Page 105: Figure A.8: Champ-Av8 P0 Utility Connector

    —D ACKPLANE ONNECTORS ETAILED ESCRIPTION The tables in this section show the mapping of CHAMP-AV8 signals to the VPX backplane connectors. VPX is the name given to the family of VITA 46 standards available from: http://www.VITA.com/ Cross Reference For detailed information describing the mapping of the 7-row VPX board connectors to the 9 row VPX backplane connectors, refer to section 7.6 “Backplane Pin Mappings”...
  • Page 106 REF_CLK_N REF_CLK_P BP_AUX_CLK_N BP_AUX_CLK_P Table A.4: P0 Utility Connector Signal Definitions CHAMP-AV8 Signal Description Vs1_BP12V +12V Power; 12V ± 5%, Max Nominal Ripple ≤ 240 mV, up to 24 A - Vs1 Vs2_BP12V +12V Power; 12V ± 5%, Max Nominal Ripple ≤ 240 mV, up to 24 A - Vs2...
  • Page 107 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT VPX B J0 U ORRESPONDING ACKPLANE TILITY ONNECTOR SSIGNMENTS Backplane J0 Pin assignments are shown below in Table A.5: Table A.5: VPX Backplane J0 Pin Assignments Pin Row i Row h Row g...

  • Page 108: Figure A.9: Champ-Av8 P1 Srio Fabric Connector

    The P1 connector is a 16 wafer VPX RT2 type connector shown in Figure A.9. The connector provides access to the Serial RapidIO (SRIO) fabric interfaces of the CHAMP-AV8. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, i, h, g, f, e, d, c, b, a).
  • Page 109 SYSCON_L - VITA 46.0 signal that indicates which slot is the system controller. Open collector driven by backplane; pull-up to 3.3V is implemented on board. When driven low by the backplane, the CHAMP-AV8 will become the source of the SYSRST_L and REF_CLK_P/N signals. CF_ALT_BOOT_L Alternate Boot Enable Input - Maps the boot chip select on all of the processors to the Permanent Alternate Boot Site (PABS) PROM;...
  • Page 110 URTISS RIGHT VPX B J1 (SRIO F ORRESPONDING ACKPLANE ABRIC ONNECTOR SSIGNMENTS Backplane J1 pin assignments are shown below in Table A.8. Table A.8: VPX Backplane J1 Pin Assignments Row i Row h Row g Row f Row e Row d Row c Row b Row a...

  • Page 111: Champ-Av8 P2 (Pcie Expansion) Connector Pin Assignments

    The P2 connector is a 16 wafer VPX RT2 type connector shown in Figure A.10. The connector provides two (2) four-lane (x4) PCIe ports on the CHAMP-AV8. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, i, h, g, f, e, d, c, b, a).
  • Page 112 EP_14_PCIE_RX_N EP_14_PCIE_RX_P EP_15_PCIE_TX_N EP_15_PCIE_TX_P EP_15_PCIE_RX_N EP_15_PCIE_RX_P Table A.10: P2 PCIe Expansion Plane Connector Signal Definitions CHAMP-AV8 Signal Description EP_X_PCIE_RX_P VITA65 Expansion Plane PCI express lanes EP_X_PCIE_RX_N (X =0,1,2,3) P2-DPX+/- (X = 0,2,4,6) EP_X_PCIE_TX_P VITA65 Expansion Plane PCI express lanes EP_X_PCIE_TX_N (X =0,1,2,3)
  • Page 113 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT VPX B J2 (PCI ORRESPONDING ACKPLANE XPANSION ONNECTOR SSIGNMENTS Backplane J2 pin assignments are as shown below in Table A.11. Table A.11: VPX Backplane J2 Pin Assignments Pin Row i Row h...

  • Page 114: Figure A.11: P3 Xmc Site's Pmc User I/O Connector

    URTISS RIGHT CHAMP-AV8 P3 (XMC S ’ PMC U I/O) C ONNECTOR SSIGNMENTS The P3 connector is a 16 wafer VPX RT2 type connector shown in Figure A.11. The connector provides access to the differential PMC User I/O on the XMC site's J14 connector. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, i, h, g, f, e, d, c, b, a).
  • Page 115 Description PMC_[64:01] PMC/XMC Site's Differential User I/O Mapping from CHAMP-AV8 J14 connector mapped in accordance with the P64s pattern defined in VITA 46.9d0.25. The adjacent signals in a column (e.g. PMC_01 and PMC_03) are routed differentially. The electrical characteristics of the PMC I/O will depend on the PMC used.
  • Page 116 J3 (XMC S ’ PMC U I/O) ORRESPONDING ACKPLANE ONNECTOR SSIGNMENTS CHAMP-AV8 to backplane J3 pin assignments are shown below in Table A.14. Table A.14: VPX Backplane J3 Pin Assignments Row i Row h Row g Row f Row e...

  • Page 117: Figure A.12: P4 Basecard I/O Connector

    The P4 connector is a 16 wafer VPX RT2 type connector shown in Figure A.12. The connector provides access to the basecard I/O of the CHAMP-AV8. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, g, f, e, d, c, b, a).
  • Page 118 CHAMP-AV8 Signal Description JTSEL_L JTAG Select Signal; pulled up to 3.3V on-board. JPROC[3:0] Select JTAG Mode; pulled up to 3.3V on-board. PMI_TCK,PMI_TDO, Reserved for Curtiss-Wright use. PMI_TDI, PMI_TMS, PMI_TRST_L PMI_JTSEL_L Reserved for Curtiss-Wright use. PMBUS_SDA, C interface to power regulators only.
  • Page 119 1000Base-BX, Nodes A and B: Signals that are always present on the P4 connector. UTPA_RX_P/N Mapped in accordance with VITA 65 specification. UTPB_TX_P/N UTPB_RX_P/N BP_PORT80_EN_L PORT80 Enable – Reserved for Curtiss-Wright use PABS interface BP_PABS_[A/B]_CS0_L – Reserved for Curtiss-Wright use BP_PABS_[A/B]_CLK BP_PABS_[A/B]_S0...
  • Page 120 VPX B J4 (B I/O) C ORRESPONDING ACKPLANE ASECARD ONNECTOR SSIGNMENTS CHAMP-AV8 to backplane J4 pin assignments are shown below in Table A.17. Table A.17: VPX Backplane J4 Pin Assignments Pin Row i Row h Row g Row f Row e...

  • Page 121: Champ-Av8 P5 (Xmc User I/O) Connector Pin Assignments

    The P5 connector is a 16 wafer VPX RT2 type connector shown in Figure A.13. The connector provides access to the XMC User I/O of the CHAMP-AV8. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, i, h, g, f, e, d, c, b, a).
  • Page 122 XMC_E11 XMC_A13 XMC_B13 XMC_D13 XMC_E13 Table A.19: P5 XMC User I/O Connector Signal Definitions CHAMP-AV8 Signal Description XMC_C[19:01] XMC Single-Ended User I/O Mapping from XMC J16 connector (38 single ended signals). XMC_F[19:01] These connection supports high-speed single-ended signals. XMC_DP[3:0]_P XMC Differential User I/O Mapping from XMC J16 connector to V46 P5 connector (8 pairs).
  • Page 123 VPX B J5 (XMC U I/O) C ORRESPONDING ACKPLANE ONNECTOR SSIGNMENTS CHAMP-AV8 to backplane J5 pin assignments are shown below in Table A.20. Table A.20: VPX Backplane J5 Pin Assignments Pin Row i Row h Row g Row f Row e...

  • Page 124: Champ-Av8 P6 (Xmc/Dio/Sata/Usb) Connector Pin Assignments

    The P6 connector is a 16 wafer VPX RT2 type connector shown in Figure A.14. The connector provides access to the XMC/DIO/SATA/USB User I/O of the CHAMP-AV8. The pinout tables are presented in the order of the rows when looking from the backplane, (that is, i, h, g, f, e, d, c, b, a).
  • Page 125 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT See Table A.21 below for connector pin assignments and Table A.22 for signal definitions. Table A.21: P6 XMC/DIO/SATA/USB Connector Pin Assignments Wafer Row G Row F Row E Row D Row C...
  • Page 126 RIGHT VPX B J6 (XMC/DIO/SATA/USB) C ORRESPONDING ACKPLANE ONNECTOR SSIGNMENTS CHAMP-AV8 to backplane J6 pin assignments are shown below in Table A.23. Table A.23: VPX Backplane J6 Pin Assignments Pin Row i Row h Row g Row f Row e...
  • Page 127 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT J1 F RONT ANEL ONNECTOR The direction of the signals in the table describing the J1 front panel connector is from the point of view of the baseboard. Note Table A.24: J1 Front Panel Connector Description Pin No.

  • Page 128: J1 Front Panel Connector

    CHASSIS_GND CGND Chassis Ground CGND CHASSIS_GND CGND Chassis Ground CGND The CHAMP-AV8 J1 front panel connector is designed for use with the front panel cable described in “CBL-462-FPL-000 (903075-000)” on page 2-6. Note 826448 V 2015 A-37 ERSION ARCH ROPRIETARY...

  • Page 129: Figure A.15: J1 Contact Numbering Arrangement (Looking Into The Front Panel

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Figure A.15: J1 Contact Numbering Arrangement (Looking into the Front Panel) J1 Pin 26 J1 Pin 13 J1 Pin 14 J1 Pin 1 A-38 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 130: Xmc Site's Pmc J14 Connector

    XMC S PMC J14 C ONNECTOR The CHAMP-AV8 incorporates an XMC site that supports legacy PMC user I/O. The XMC's legacy PMC I/O connector location is shown in Figure A.16 and described in the following section. The direction of the signals in the table describing the PMC J14 connector is from the point of view of the baseboard.
  • Page 131 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Table A.25: J14 Connector Description (Pn4/Jn4 User Defined I/O) PMC J14 VITA 46/48 PMC Differential Direction Description Pin Number P3 Connector Routing Partner on P3 / Pin Number Corresponding J14 Pin Number...
  • Page 132 URTISS RIGHT Table A.25: J14 Connector Description (Pn4/Jn4 User Defined I/O) (Continued) P3-B8 P3-C8/J14-30 J14-32 connection to P3 connector P3-E9 P3-D9/J14-35 J14-33 connection to P3 connector P3-B9 P3-A9/J14-36 J14-34 connection to P3 connector P3-D9 P3-E9/J14-33 J14-35 connection to P3 connector P3-A9 P3-B9/J14-34 J14-36 connection to P3 connector...

  • Page 133: Xmc J15 And J16 Connectors

    J16 C ONNECTORS The CHAMP-AV8 incorporates a single width XMC site in accordance with VITA 42.0 and VITA 42.3. The XMC site includes the connectors designated J15 and J16 as shown in Figure A.17. Figure A.17: Location of CHAMP-AV8 XMC J15 and J16 Connectors...
  • Page 134 I2C serial data XMC_GA0:2 I2C channel select. These are inputs to the XMC and are driven as 011 on the CHAMP-AV8. XMC_MBIST_L XMC Built In Self Test. This signal is an output from the XMC and allows the carrier to determine whether an XMC has completed its built-in self test.
  • Page 135 XMC Write Prohibit. This signal is an input to the XMC. When this signal is asserted high, the XMC shall disable writes to non-volatile memory on the XMC. The CHAMP-AV8 ties this signal to the VITA 46 NVMRO signal (VITA 46 P0-A4).

  • Page 136: Xmc J16 User I/O Connector

    URTISS RIGHT XMC J16 U I/O C ONNECTOR Table A.28 lists the pin assignments for the XMC J16 connector. The J16 connector is the secondary XMC connector as defined in V42.0 and is used for user I/O. The user I/O includes single ended and high speed differential signals routed between the J16 connector and the VITA 46/48 P5 and P6 connectors in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 137 J16 Row A XMC User I/O signals to the corresponding VITA 46/48 P5 or P6 connector pins of the CHAMP-AV8 board. The signals are routed as high speed differential signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 138 XMC site. The table maps the J16 Row B XMC User I/O signals to the corresponding VITA 46/48 P5 or P6 connector pins of the CHAMP-AV8 board. The signals are routed as high speed differential signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 139 XMC site. The table maps the J16 Row C XMC User I/O signals to the corresponding VITA 46/48 P5 connector pins of the CHAMP-AV8 board. The signals are routed as single ended signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 140 XMC site. The table maps the J16 Row D XMC User I/O signals to the corresponding VITA 46/48 P5 or P6 connector pins of the CHAMP-AV8 board. The signals are routed as high speed differential signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 141 XMC site. The table maps the J16 Row E XMC User I/O signals to the corresponding VITA 46/48 P5 or P6 connector pins of the CHAMP-AV8 board. The signals are routed as high speed differential signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.
  • Page 142 XMC site. The table maps the J16 Row F XMC User I/O signals to the corresponding VITA 46/48 P5 connector pins of the CHAMP-AV8 board. The signals are routed as single ended signals in accordance with the P5w3P6–X38s+X8d+X12d pattern defined in VITA 46.9.

  • Page 143: Rear Transition Module (Rtm

    An illustration of the various ports and the industry-standard connectors provided by the RTM is shown below in Figure A.18. Figure A.18: CHAMP-AV8 Rear Transition Module Views Additional interfaces and controls are made available on the RTM PWB, as seen in Figure A.19, “RTM Printed Wiring Board Component Side View,”...

  • Page 144: Figure A.19: Rtm Printed Wiring Board Component Side View

    URTISS RIGHT Figure A.19: RTM Printed Wiring Board Component Side View Configuration Switches 826448 V 2015 A-53 ERSION ARCH ROPRIETARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 145: Rear Transition Module Panel-Mounted Connectors

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT RANSITION ODULE ANEL OUNTED ONNECTORS The pinout details for the industry-standard panel-mounted connector interfaces on the Rear Transition Module are provided in the following sections. Ethernet ports A and B are available on RJ-45 connectors via the RTM. Both ports will RTM ENET A, auto-select 10 Mbps, 100 Mbps or 1000 Mbps, depending on what they are connected to.

  • Page 146: Figure A.20: Serial Port Loopback Control Via Rtm P3

    URTISS RIGHT Serial ports are labelled consecutively. Ports 1-4 are EIA-232 and 5-6 are EIA-422. Note EIA-232 serial ports are available through RTM connectors, J2 and J3 (labelled as COM A and RTM EIA-232 Serial COM B on the RTM connector panel). J2 connects to processor A's serial port, J3 to processor Port Connectors B's serial port, The pinout for the serial ports is provided in Table A.38 below.

  • Page 147: Figure A.21: Proper Jumper Orientation For Rtm P3 Jumpers

    NODE A0_TX NODE A0_RX NODE A1_RX NODE A1_TX NODE B0_RX NODE B0_TX NODE B1_TX NODE B1_RX INCORRECT The RTM JTAG connector is reserved for Curtiss-Wright use only. RTM JTAG Connector A-56 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 148: Rear Transition Module (Rtm) Configuration Switches

    NVMRO signal). When the same backplane, or the in this state, it is possible to CHAMP-AV8 JB10 jumper enable writes to main is ON – see Table 2.3 on NAND flash, main boot page 2-7 for details).When...

  • Page 149: Rear Transition Module (Rtm) Pwb Header Connectors

    INSTALLED, or both, the non-default setting is selected. Note The NVMRO switch on the CHAMP-AV8's RTM has the opposite polarity when compared to the VITA 46 Specification. In other words, according to the VITA 46 spec, when a NVMRO jumper is installed (or the switch is closed), the non-volatile memories are write protected.

  • Page 150: Table A.40: Rtm Header Functions

    Headers indicated as “Factory use only” are not intended for use in the field. Field operations are not supported. All Headers and their functions are listed for completeness. Note The CHAMP-AV8 PMC I/O (J14 on the CHAMP-AV8 board) is mapped to the RTM JB2 header RTM JB2 PMC I/O as shown below in Table A.41.
  • Page 151 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Table A.41: RTM PMC I/O (JB2) Pin Assignments (Continued) PMC J14 Pin (Odd Numbers) JB2 Pin JB2 Pin PMC J14 Pin (Even Numbers) PMC_15 PMC_16 PMC_17 PMC_18 PMC_19 PMC_20 PMC_21 PMC_22 PMC_23...

  • Page 152: Table A.42: Rtm Discrete I/O (P4, P5) Pin Assignments

    11, 15 On the CHAMP-AV8, the VITA 46 Geographical Addressing pins are routed to the CF-FPGA, so RTM P12 that the CHAMP-AV8 can determine which slot it is in. These pins are also mapped to the P12 Geographical Addressing header on the RTM.

  • Page 153: Table A.44: Xmc Single Ended I/O (Jb6) Pin Assignments

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT On the CHAMP-AV8, the XMC Site Single-Ended User I/O signals are mapped to the RTM JB6 RTM JB6 Single connector as shown below in Table A.44. Ended XMC I/O Signals Table A.44:...

  • Page 154: Table A.45: Rtm Xmc Differential User I/O (J7) Pin Assignments

    URTISS RIGHT On the CHAMP-AV8, the XMC Site Differential User I/O signals are mapped to the RTM J7 RTM J7 Connector connector as shown below in Table A.45. Assignments Table A.45: RTM XMC Differential User I/O (J7) Pin Assignments Signal Name...
  • Page 155 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT A-64 826448 V 2015 ROPRIETARY ERSION ARCH Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 156: Statement Of Memory Volatility

    TATEMENT OF EMORY OLATILITY PPENDIX This appendix contains the Curtiss-Wright Statement of Memory Volatility found in the following section: • “CHAMP-AV8 Statement of Volatility” on page B-2 826448 V 2015 ERSION ARCH ROPRIETARY Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 157: Table B.1: Memory Devices Available On The Champ-Av8

    There are no battery-backed memories on the CHAMP-AV8. Note The following Table B.1 describes all of the memory devices on the CHAMP-AV8 board and their associated procedures for write-protection and scrubbing. "RTM" refers to the CHAMP-AV8 Rear Transition Module, Curtiss-Wright part number RTM6-462-000.
  • Page 158 URTISS RIGHT Table B.1: Memory Devices Available On The CHAMP-AV8 (Continued) Memory Type Size Volatility Function Accessible Write-protection Process to from CPU (Note 1) Clear PABS SPI Flash 8MB/CPU on Non-volatile Backup copy of the The memory is pro- None boards with BIOS SPI Flash.
  • Page 159 CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT Table B.1: Memory Devices Available On The CHAMP-AV8 (Continued) Memory Type Size Volatility Function Accessible Write-protection Process to from CPU (Note 1) Clear Serial Flash 4 Mbit Non-volatile Contains configuration The memory is pro-...

  • Page 160: Memory Write Protection

    EMORY RITE ROTECTION PPENDIX This appendix provides clarifying information and procedures for hardware memory write protection. It discusses the following topics: • “NVRAM Write Protection” on page C-2 • “BIOS SPI Flash Write Protection” on page C-3 • “On-Board SATA (NAND) Flash Write Protection” on page C-4 826448 V 2015 ERSION...

  • Page 161: Nvram Write Protection

    RITE ROTECTION Early versions of the CHAMP-AV8 BIOS and BSPs stored vital product data, or VPD, such as board serial number and similar information, in a memory block of the NVRAM. This required the NVRAM write protection mechanism to write-protect the block containing the VPD by default.

  • Page 162: Bios Spi Flash Write Protection

    URTISS RIGHT BIOS SPI F LASH RITE ROTECTION Upon boot, the BIOS attempts to write to certain blocks of its Boot Flash, per normal BIOS boot algorithms. When write-protected, the BIOS still attempts these writes to memory. When read-backs show the write is unsuccessful, the BIOS continues to attempt further writes. Eventually, the process will time out and the BIOS boot continues.

  • Page 163: On-Board Sata (Nand) Flash Write Protection

    CHAMP-AV8 (VPX6-462) H ’ ARDWARE ANUAL URTISS RIGHT SATA (NAND) F OARD LASH RITE ROTECTION Linux, as a part of its basic configuration, caches its file system. When cached, it has been observed that a write-protected SATA Flash may appear to delete a file. Once the file system has been made coherent with the NAND Flash, the “deleted”...
  • Page 164 2-2 In This Chapter 1-1 choosing a VPX slot location 3-4 initial screen message 3-13 configuring an emulator for use with CHAMP-AV8 3-14 initial screen message, displaying 3-13 configuring jumpers 2-7 inserting the basecard in the chassis 3-4...
  • Page 165 1-40 software development tools 1-41 software, overview of available 1-40 specifications 1-31 SRIO Fabric connector (P1) pin assignments A-17 summary of CHAMP-AV8 connectors, functions support- ed 1-39 switches, Rear Transition Module (RTM) configuration A-57 system controller (SYSCON) 3-4 826448 V...
  • Page 166 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...

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