Sony CXD2701Q Data Book page 192

SONY
cwhtoic
Microprocessor
Interface
Control
instructions
from the microprocessor are carried out
under
the three
assumptions
list
below
(PRGD,
PRGCK, PRGL), Depending on
how
these
factors
are setup internally for
DSP
program,
IIP, filter
and
MIX
coefficients
can be
partially
or globally
changed! Each
mode
is
program
selectable.
•
PRGD
DATA
RAM ADDRESS
transfer
case
1
cycle
transfer, 24-bit serial
data
DSP
coefficient, Instruction
transfer
case
1
cycle transfer, 24-bit serial
data
K-BAM
transfer
case
1
cycle
transfer, 28-bit serial
data
MODE
transfer
case
1
cycle
transfer,
1
2-bit
serial
data
PRGCK
-A
serial
clock. Serial
data
(PRGD)
is
transferred
to
the
internal
shift
register activated
by
the rising
edge
signal,
•
PRGL
When
serial data
PRGD
is
input to
the
shift
register,
data
Is
globally
latched by the gate pulse
(active
when
set low).
Concurrently with the
rising
edge, a processing request
is
sent
internally to
thelC.
The
transfer
format
and
timing
are
shown
below:
S
(1-bit)
:
When
set "Low",
DSP
transfers active:
when
set "High*,
non-DSP
transfers.
L
(7-bit/3-bit)
:
Discrimination label
and
transfer
address
of transfer
data
D
(16-bit/20-bit/8-bit)
:
Transfer data
L
and
D
use
LSB
first
format
PRGD
is
accepted
at rising
PRGCK
and
the internal register
is
latched
at falling
PRGL.
Explanation
of
Each
Mode
1}
DATA
RAM,
ADDRESS
External
DRAM
relative
address
2)
DSP
coefficient
INSTRUCTION
DSP
program and
coefficient.
DSP
section multiplication coefficient
K
(8-bit) is
equal
to
7FH
*tX1,
8QH=
x(-1).
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188
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