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IDT SerDes
Notes
PES32NT24xG2 User Manual
Table 8.11 SerDes Transmit Drive Swing in Low Swing Mode at Gen 2 Speed (Part 2 of 2)
When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following
occurs:
– The transmit drive level is selected by the Transmit Margin (TM) field in the PCIELCTL2 register.
This field has specific transmit margin levels for full-swing and low-swing mode. The values corre-
sponding to low-swing mode are applied.
– De-emphasis is turned off.
Receiver Equalization Controls
PES32NT24xG2 contains SerDes receiver equalization controls on a per-lane basis. The receiver
equalization circuit has two controls which may be programmed via the SerDes Receiver Equalization Lane
Control (S[x]RXEQLCTL) register. These are:
– Receiver Equalization Zero (RXEQZ): Increases the high-frequency gain of the equalizer.
– Receiver Equalization Boost (RXEQB): Reduces the low-frequency gain of the equalizer.
Together, RXEQZ and RXEQB provide wide programmability and fine grain control over the equalizer's
boost. Refer to the definition of the S[x]RXEQLCTL register for further details on programming these
controls.
SerDes Power Management
In order to maximize power savings in the SerDes, the PES32NT24xG2 adheres to the following guide-
lines. For SerDes quads that are used, their power state depends on the state of the port(s) associated with
the SerDes, as described below. When a port is disabled:
– For a x4 or x8 port, the SerDes quad(s) associated with the disabled port are placed in a deep low
power state.
• There is one SerDes quad associated with a x4 port.
• There are two SerDes quads associated with a x8 port.
– For a x1 or x2 port, the SerDes lanes associated with the disabled port are placed in a deep low
power state.
• If all lanes of a SerDes quad are associated with disabled ports, the entire SerDes quad is
placed in a deep low power state.
When a port is not disabled:
– The SerDes quad(s) associated with the port are turned-on.
– Unused lanes are powered down.
• Lanes that form the initial link width (i.e., lanes on which the PHY LTSSM detected the presence
of a link partner in the Detect state) are considered used. All other lanes associated with the port
1
are unused.
– Used lanes are active and fully powered.
– Dynamic link width downconfigure (i.e., change of link width while the link is up) is handled per the
rules in the PCI Express Base Specification. In this case, inactive lanes place their transmitter in
electrical idle and enable receiver termination
1.
Note that unused lanes may become used when the PHY LTSSM transitions to the Detect state and retrains the
link.
Drive Level
TDVL_LSG2
(mV)
203
166
129
91
2
.
8 - 14
0x03
0x02
0x01
0x00
January 30, 2013
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