Functional Description - Samsung BL8531H Manual

12BIT 10MSPS ADC

FUNCTIONAL DESCRIPTION

1. The BL8531H_ADC is a CMOS four step pipelined Analog-to-Digital Converter. It contains 4-bit flash A/D
Converters, three 3bit flash A/D converters and three multiplying D/A Convertors. The N-bit flash ADC is
N
composed of 2 -1 latched comparators, and multiplying DAC is composed of 2*(2
fully-differential amplifiers.
2. The BL8531H_ADC operates as follows. During the first "L" cycle of external clock the analog input data is
sampled, and the input is held from the rising edge of the external clock, which is fed to the first 4-bit flash
ADC, and the first multiplying DAC. Multiplying DAC reconstructs a voltage corresponding to the first 4-bit
ADC's output, and finally amplifies a residue voltage by 2
worked as same manner. Finally amplified residue voltage at the third multiplying DAC is fed to the last 3-bit
flash ADC decides final 3-bit digital digital code.
3. BL8531H_ADC has the error correction scheme, which handles the output from mismatch in the first, second, third
and fourth flash ADC.
MAIN BLOCK DESCRIPTION
1. SHA
SHA (Sample-and-Hold Amplifier) is the circuit that samples the analog input signal and hold that value until next
sample-time. It is good as small as its different value between analog input signal and output signal. SHA amp
gain is higher than 70dB at 10MHz conversion rate, its settling-time must be shorten than 38ns with less than 1/2
LSB error voltage at 12bit resolution. This SHA is consist of fully differential op amp, switching tr. and sampling
capacitor. The sampling clock is non-overlapping clock (Q1, Q2) and sampling capacitor value is about 4pF. SHA
uses independent bias to protect interruption of any other circuit. SHA amp is designed that open-loop dc gain is
higher than 70dB, phase margin is higher than 60 degrees. Its input block is designed to be the rail-to-rail
architecture using complementary different pair.
2. FLASH
The 4-bit flash converters compare analog signal (SAH output) with reference voltage, and that results transfer to
MDAC and digital correction logic block. It is realized fully differential comparators of 15EA. Considering
self-offset, dynamic feed through error, it should distinguish 40mV at least. First, the comparators charge the
reference voltage at the sampling capacitors before transferred SHA output.That operation is performed on the phase
of Q2, and discharging on the phase of Q1. That is, the comparators compare relative different values dual input
voltage with dual reference voltage. Its output during Q1 operation is stored at the pre-latch block by Q1P.
3. MDAC
MDAC is the most important block at this ADC and it decides the characteristics. MDAC is consist of two stage
op amp, selection logic and capacitor array (c_array). c_array's compositions are the capacitors to charge the analog
input and and the reference voltage, switches to control the path. Selection logic controls the c_array internal
switches. If Q1 is high, selection's output are all low, the switches of tsw1 are off, the switches of tsw2 are all
on. Therefore the capacitors of c_array can charge analog input values held at SHA.
SEC ASIC
4
. The second and third flash ADC, and MDAC are
6 / 11
BL8531H_ADC
N
+1) capacitors and two
MIXED