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1. General Description
The DM9000 is a fully integrated and cost-effective
single chip Fast Ethernet MAC controller with a
general processor interface, a 10/100M PHY and 4K
Dword SRAM. It is designed with low power and high
performance process that support 3.3V with 5V
tolerance.
The DM9000 also provides a MII interface to connect
HPNA device or other transceivers that support MII
interface. The DM9000 supports 8-bit, 16-bit and 32-
bit uP interfaces to internal memory accesses for
2. Block Diagram
TX+/-
RX+/-
Final
Version: DM9000-DS-F02
June 26, 2002
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
LED
PHYceiver
100 Base-TX
100 Base-TX
transceiver
PCS
10 Base-T
Tx/Rx
Autonegotiation
different processors. The PHY of the DM9000 can
interface to the UTP3, 4, 5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliant with the IEEE 802.3u Spec.
Its auto-negotiation function will automatically configure the
DM9000 to take the maximum advantage of its abilities. The
DM9000 also supports IEEE 802.3x full- duplex flow control.
This programming of the DM9000 is very simple, so user
can port the software drivers to any system easily.
External MII
Interface
MAC
TX Machine
Control &Status
MII
Registers
RX Machine
MII Management
Control
& MII Register
DM9000
EEPROM
Interface
Memory
Management
Internal
SRAM
1
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Table of Contents
Related Manuals for Davicom DM9000
Summary of Contents for Davicom DM9000
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Page 1: General Description
Dword SRAM. It is designed with low power and high Its auto-negotiation function will automatically configure the performance process that support 3.3V with 5V DM9000 to take the maximum advantage of its abilities. The tolerance. DM9000 also supports IEEE 802.3x full- duplex flow control. -
Page 2: Table Of Contents
6.13 ROM & PHY Address Register (0CH) ....17 (DSCR) – 16 .............28 6.14 EEPROM & PHY Data Register (0DH, 0EH)..17 8.9 DAVICOM Specified Configuration and Status 6.15 Wake Up Control Register (0FH)....17 Register (DSCSR) – 17 ........29 6.16 Physical Address Register (10H~15H) ...17 8.10 10BASE-T Configuration/Status (10BTCSR) –... - Page 3 10.4.3 Processor Register Read Timing....39 10.4.4 Processor Register Write Timing ....40 10.4.5 External MII Interface Transmit Timing..41 10.4.6 External MII Interface Receive Timing..41 10.4.7 MII Management Interface Timing ....42 10.4.8 EEPROM Interface Timing ......42 Final Version: DM9000-DS-F02 June 26, 2002...
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Page 4: Features
– Selectable TX drivers for 1:1 or 1.25:1 magic packet events for remote wake up transformers for additional power reduction. ■ Integrated 4K dword SRAM ■ Compatible with 3.3V and 5.0V tolerant I/O ■ 100-pin LQFP with CMOS process Final Version: DM9000-DS-F02 June 26, 2002... -
Page 5: Pin Configuration
TEST5 WAKEUP RX_CLK PW_RST# RX_ER DGND RX_DV SD15 SD14 SD13 DGND SD12 RXD3 SD11 RXD2 DM9000 SD10 RXD1 RXD0 LINK_I DVDD DVDD AVDD IO16 TXO- TXO+ AGND AGND RXI- RXI+ AVDD DGND AVDD BGRES Final Version: DM9000-DS-F02 June 26, 2002... -
Page 6: Pin Configuration Ii: With 32-Bit Data Bus
SD22 PW_RST# SD23 DGND SD24 SD15 SD25 SD14 SD26 SD13 DGND SD12 SD27 SD11 SD28 DM9000 SD10 SD29 SD30 SD31 DVDD DVDD AVDD IO16 TXO- TXO+ AGND AGND RXI- RXI+ AVDD DGND AVDD BGRES Final Version: DM9000-DS-F02 June 26, 2002... -
Page 7: Pin Description
This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Address Enable A low active signal used to select the DM9000. IOWAIT Processor Command Ready When a command is issued before last command is completed, the IOWAIT will... -
Page 8: Processor Interface
SD16~31 (in Processor Data Bus bit 16~31 51,50,49, double word These pins are used as data bus bits 16~31 when the DM9000 is set to 47,46,45, mode) double word mode (the straps pin EEDO is pulled high and WAKEUP is... -
Page 9: Eeprom Interface
BGGND Bandgap Ground BGRES Bandgap Pin AVDD Bandgap and Guard Ring Power AVDD RX Power RXI+ TP RX Input RXI- TP RX Input AGND RX Ground AGND TX Ground TXO+ TP TX Output Final Version: DM9000-DS-F02 June 26, 2002... -
Page 10: 10/100 Phy/Fiber
Issue a wake up signal when wake up event happens This pin has a pulled down resistor about 60k ohm internally. PW_RST# Power on Reset Active low signal to initiate the DM9000 The DM9000 is ready after 5us when this pin deasserted 74,75,77 Not Connect 5.8 Power Pins 5,20,36,... -
Page 11: Vendor Control And Status Register Set
ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6. Vendor Control and Status Register Set The DM9000 implements several control and status are byte aligned. All CSRs are set to their default values by registers, which can be accessed by the host. These CSRs... - Page 12 RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write 1 WO = Write only Reserved bits are shaded and should be written with 0. Reserved bits are undefined on read access. Final Version: DM9000-DS-F02 June 26, 2002...
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Page 13: Network Control Register (00H)
CRC Appends Disable for Packet Index 2 PAD_DIS1 0,RW PAD Appends Disable for Packet Index 1 CRC_DIS1 0,RW CRC Appends Disable for Packet Index 1 TXREQ 0,RW TX Request. Auto clears after sending completely Final Version: DM9000-DS-F02 June 26, 2002... -
Page 14: Tx Status Register I (03H)
When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabled DIS_LONG 0,RW Discard Long Packet Packet length is over 1522byte DIS_CRC 0,RW Discard CRC Error Packet 0,RW Pass All Multicast RUNT 0,RW Pass Runt Packet PRMSC 0,RW Promiscuous Mode RXEN 0,RW RX Enable Final Version: DM9000-DS-F02 June 26, 2002... -
Page 15: Rx Status Register (06H)
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) 7H, RW Jam Pattern Time. Default is 200us bit3 bit2 bit1 bit0 time 10us 15us 25us 50us 100us 150us 200us 250us 300us 350us 400us 450us 500us 550us 600us Final Version: DM9000-DS-F02 June 26, 2002... -
Page 16: Flow Control Threshold Register (09H)
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after the operation completes. ERRE 0,RO EEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress Final Version: DM9000-DS-F02 June 26, 2002... -
Page 17: Rom & Phy Address Register (0Ch)
X,RW Physical Address Byte 4 (14H) PAB3 X,RW Physical Address Byte 3 (13H) PAB2 X,RW Physical Address Byte 2 (12H) PAB1 X,RW Physical Address Byte 1 (11H) PAB0 X,RW Physical Address Byte 0 (10H) Final Version: DM9000-DS-F02 June 26, 2002... -
Page 18: Multicast Address Register (16H~1Dh)
TX SRAM Read Pointer Address Low Byte (22H) 6.21 RX SRAM Write Pointer Address Register (24H~25H) Name Default Description RWPAH 0CH,RO RX SRAM Write Pointer Address High Byte (25H) RWPAL 04H.RO RX SRAM Write Pointer Address Low Byte (24H) Final Version: DM9000-DS-F02 June 26, 2002... -
Page 19: Rx Sram Write Pointer Address Register
Memory Data Read_ address Low Byte 6.29 Memory Data Write Command without Address Increment Register (F6H) Name Default Description MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is unchanged Final Version: DM9000-DS-F02 June 26, 2002... -
Page 20: Memory Data Write_Address Register (Fah~Fbh)
REG_F5 will set to 0Ch automatically RESERVED 0,RO Reserved ROOM 0,RW Enable Receive Overflow Counter Overflow Latch 0,RW Enable RX Overflow Latch 0,RW Enable Packet Transmitted Latch 0,RW Enable Packet Received Latch Final Version: DM9000-DS-F02 June 26, 2002... -
Page 21: Eeprom Format
Bit7: LED mode 1 (default: 0) Bit8: internal PHY is enabled after power-on (default: no) The GPR bit 0 and the GPIO0 pin are modified from this bit. Bit15:9: reserved RESERVED 16-17 RESERVED 18-19 Final Version: DM9000-DS-F02 June 26, 2002... -
Page 22: Mii Register Description
Value latched from pin # at reset <Access Type>: RO = Read Only RW = Read/Write <Attribute (s)>: SC = Self Clearing P = Value Permanently Set LL = Latching Low LH = Latching High Final Version: DM9000-DS-F02 June 26, 2002... -
Page 23: Basic Mode Control Register (Bmcr) - 00
1 until auto- negotiation is initiated by the PHY. The operation of the auto- negotiation process will not be affected by the management entity that clears this bit 0 = Normal operation Final Version: DM9000-DS-F01 April 12, 2002... -
Page 24: Basic Mode Status Register (Bmsr) - 01
Auto Configuration Ability negotiation 1 = Able to perform auto-negotiation Ability 0 = Not able to perform auto-negotiation Link status 0,RO/LL Link Status 1 = Valid link is established (for either 10Mbps or 100Mbps Final Version: DM9000-DS-F02 June 26, 2002... -
Page 25: Phy Id Identifier Register #1 (Phyid1) - 02
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. -
Page 26: Auto-Negotiation Advertisement Register
DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9000 device as they will be transmitted to its link partner during Auto-negotiation. Bit Name... -
Page 27: Auto-Negotiation Link Partner Ability Register
PDF = 0: No fault detected via parallel detection function LP_NP_ABLE 0, RO Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page NP_ABLE 0,RO/P Local Device Next Page Able Final Version: DM9000-DS-F02 June 26, 2002... -
Page 28: Davicom Specified Configuration Register Dscr) – 16
(register 6) is read by management LP_AN_ABLE 0, RO Link Partner Auto-negotiation Able A “1” in this bit indicates that the link partner supports Auto- negotiation 8.8 DAVICOM Specified Configuration Register (DSCR) - 16 Bit Name Default Description 16.15 BP_4B5B 0, RW... -
Page 29: Davicom Specified Configuration And Status
0, RW When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit Name Default Description 17.15... -
Page 30: 10Base-T Configuration/Status (10Btcsr)
Write as 0, ignore on read 18.0 POLR 0, RO Polarity reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically Final Version: DM9000-DS-F02 June 26, 2002... -
Page 31: Functional Description
DMA port and then write the byte count to byte_ count register at TX Packet Length Register (0fch/0fdh). Set the bit 0 of TX Control Register (02h). The DM9000 9.2 Direct Memory Access Control starts to transmit the index I packet. Before the... -
Page 32: 100Base-Tx Operation
Transmit Enable is asserted and the next transmit two binary data streams, with alternately phased logic packet is detected. one event. The DM9000 includes a Bypass 4B5B conversion 9.5.6 MLT-3 Driver option within the 100Base-TX Transmitter for support The two binary data streams created at the MLT-3... -
Page 33: 4B5B Code Group
00100 Invalid undefined 00000 Invalid undefined 00001 Invalid undefined 00010 Invalid undefined 00011 Invalid undefined 00101 Invalid undefined 00110 Invalid undefined 01000 Invalid undefined 01100 Invalid undefined 10000 Invalid undefined 11001 Table 1 Final Version: DM9000-DS-F02 June 26, 2002... -
Page 34: 100Base-Tx Receiver
125Mb/s serial data 9.6.3 MLT-3 to NRZI Decoder to synchronous 4-bit nibble data that is then provided The DM9000 decodes the MLT-3 information from the to the MII. Digital Adaptive Equalizer into NRZI data. The... -
Page 35: Code Group Alignment
The 10Base-T transceiver is IEEE 802.3u compliant. at the best common mode of operation. If more than When the DM9000 is operating in 10Base-T mode, one common mode exists between the two devices, a the coding scheme is Manchester. Data processed for... -
Page 36: Power Reduced Mode
(cable disconnected). The Power Down mode, which disables all transmit, receive DM9000 automatically turns off the power and enters the functions and MII interface functions, except the MDC/MDIO Power Reduced mode, whether its operation mode is N- management interface. -
Page 37: Dc And Ac Electrical Characteristics
These are stress ratings only. Functional periods may affect the reliability of the device. operation of this device at these or any other conditions above, which indicated in the operational Final Version: DM9000-DS-F02 June 26, 2002... -
Page 38: Dc Electrical Characteristics
100TX+/- Differential Output Peak to Peak TD100 Voltage 10TX+/- Differential Output Voltage Peak to Peak TD10 100TX+/- Differential Output │19│ │20│ │21│ Absolute Value TD100 Current 10TX+/- Differential Output Current │44│ │50│ │56│ Absolute Value TD10 Final Version: DM9000-DS-F02 June 26, 2002... -
Page 39: Ac Electrical Characteristics & Timing Waveforms
IOR width SD Setup time IOR invalid to SD invalid IOR invalid to system address invalid IOR invalid to next IOR valid （access DM9000） System address valid to IO16,IO32 valid System address invalid to IO16, IO32 invalid Final Version: DM9000-DS-F02... -
Page 40: Processor Register Write Timing
IOW Width SD Setup Time SD Hold Time IOW Invalid to System Address Invalid IOW Invalid to Next IOW validaccess DM9000） System Address Valid to IO16, IO32 Valid System Address Invalid to IO16, IO32 Invalid Note： ： ： ： 1. The IO16 is valid when the SD bus width is 16-bit or 2. -
Page 41: External Mii Interface Transmit Timing
TXEN,TXD[3：0] Setup Time TXEN,TXD[3：0] Hold Time 10.4.6 External MII Interface Receive Timing RXCK ∫∫ RXER,RXDV → ← → ← RXD[3:0] ∫∫ Symbol Parameter Min. Typ. Max. Unit RXER, RXDV,RXD[3：0] Setup Time RXER, RXDV,RXD[3：0] Hold Time Final Version: DM9000-DS-F02 June 26, 2002... -
Page 42: Mii Management Interface Timing
→ ← Symbol Parameter Min. Typ. Max. Unit MDC Frequency MDIO by DM9000 Setup Time MDIO by DM9000 Hold Time MDIO by External MII Setup Time MDIO by External MII Hold Time 10.4.8 EEPROM Interface Timing → ← EESS →... -
Page 43: Application Notes
DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY Final Version: DM9000-DS-F02 June 26, 2002... -
Page 44: 10Base-T/100Base-Tx
Place all the 50 Ω resistors as close as ground away from all active signals. The RJ-45 connector possible to the DM9000 RXI± and TXO± pins. Traces and any unused pins should be tied to chassis ground routed from RXI± and TXO± to the transformer should run through a resistor divider network and a 2KV bypass in close pairs directly to the transformer. -
Page 45: Power Decoupling Capacitors Figure 11-3
0.1µF Ω AGND 3.3V AVDD 0.1µF 0.1µF DM9000 78Ω AGND AGND 1.25:1 78Ω 3.3V AVCC TX0- 0.1µF Ω 75Ω BGRES Ω AGND Ω 8.5KΩ, 1% BGGND 0.1µF/2KV or 0.01µF/ Chasis GND AGND Figure 11-2 Final Version: DM9000-DS-F02 June 26, 2002... -
Page 46: Ground Plane Layout Figure 11-4
0.1μF or 0.01μF, as required by decoupling capacitors for all power supply pins as close as the design layout. possible to the power pads of the DM9000 (The best placed distance is < 3mm from pin). The recommended Figure 11-3... -
Page 47: Power Plane Partitioning Figure 11-5
DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.5 Ground Plane Layout Davicom Semiconductor recommends a single ground network interface card not comply with specific FCC plane approach to minimize EMI. Ground plane partitioning regulations (part 15). Figure 4 shows a recommended can cause increased EMI emissions that could make the ground layout scheme. -
Page 48: Magnetics Selection Guide
VDD and Ground impedance at least 75Ω at 100MHz. A suitable bead is at the device side of each of the ferrite bead. the Panasonic surface mound bead, part number Figure 11-5 Final Version: DM9000-DS-F02 June 26, 2002... -
Page 49: Application Of Reverse Mii Figure 11-7
The crystal crystal lead to ground with a 22pf capacitor (see figure must be a fundamental type, and series-resonant. X1_25M X2_25M 22pf 22pf AGND AGND Figure 11-6 Crystal Circuit Diagram Final Version: DM9000-DS-F02 June 26, 2002... -
Page 50: Package Information
Link Full Mode (Reverse MII Normal MII) Figure 11-7 Note: When operating DM9000 at Reverse MII mode, pin 87 is pulled high . At this application, the txclk , col and crs pins will be changed from input to output. Final... -
Page 51: Appendix
0° ~ 12° Notes: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. Final Version: DM9000-DS-F02 June 26, 2002... - Page 52 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 13. APPENDIX: 1. Data Sheet Changed Errata List Items Data & Ver. Page Content 05/02/2001 P01 DM9000 Data Sheet Start 06/14/2001 P01 Page 1 Modify Block Diagram 06/22/2001 P01 Page 14 Check TableA-1-A &A-1-B 12/05/2001 P02 Page 7 Check TableA-2-A &A-2-B...
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Page 53: Order Information
(Reserved) Table A-3-B Before Modification Symbol Parameter Min. Typ. Max. Unit SD Setup time IOW invalid to next IOW （access DM9000） TableA-4-A After Modification Symbol Parameter Min. Typ. Max. Unit SD Setup time IOW invalid to next IOW （access DM9000）... - Page 54 Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: Sales & Marketing Office: 3F, No. 7-2, Industry E. Rd., IX, 2F, No.
- Page 55 This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.
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