Page 1 Programming Manual AX5043 Advanced high performance ASK and FSK narrow-band transceiver for 27-1050 MHz range Version 1.9...
Page 2: Table Of Contents
A B L E O F O N T E N T S 1.Overview ..........................7 1.1.Connecting the AX5043 to an AX8052F100 or other Microcontroller ......8 1.2.Pin Function Descriptions ..................... 9 1.3.SPI Register Access ..................... 10 1.3.1.Deep Sleep ......................12 1.3.2.Address Space ....................
Page 3 5.11.Signal Strength ......................75 5.11.1.Register: RSSI ....................75 5.11.2.Register: BGNDRSSI ..................76 5.11.3.Register: DIVERSITY ..................76 5.11.4.Register: AGCCOUNTER ..................76 5.12.Receiver Tracking ..................... 76 5.12.1.Register: TRKDATARATE2, TRKDATARATE1, TRKDATARATE0 ....... 76 5.12.2.Register: TRKAMPL1, TRKAMPL0 ................ 76 Version 1.9 Programming Manual AX5043...
Page 4 5.15.27.Register: FREQDEV10, FREQDEV00, FREQDEV11, FREQDEV01, FREQDEV12, FREQDEV02, FREQDEV13, FREQDEV03 ................ 90 5.15.28.Register: FOURFSK0, FOURFSK1, FOURFSK2, FOURFSK3 ......... 90 5.15.29.Register: BBOFFSRES0, BBOFFSRES1, BBOFFSRES2, BBOFFSRES3 ....92 5.16.Transmitter Parameters .................... 93 5.16.1.Register: MODCFGF ................... 93 5.16.2.Register: FSKDEV2, FSKDEV1, FSKDEV0 ............93 Version 1.9 Programming Manual AX5043...
Page 5 5.22.3.Register: TMGRXBOOST .................. 103 5.22.4.Register: TMGRXSETTLE .................. 103 5.22.5.Register: TMGRXOFFSACQ ................103 5.22.6.Register: TMGRXCOARSEAGC ................103 5.22.7.Register: TMGRXAGC ..................104 5.22.8.Register: TMGRXRSSI ..................104 5.22.9.Register: TMGRXPREAMBLE1 ................104 5.22.10.Register: TMGRXPREAMBLE2 ................. 104 5.22.11.Register: TMGRXPREAMBLE3 ................. 105 Version 1.9 Programming Manual AX5043...
Page 6 5.24.4.Register: LPOSCREF1, LPOSCREF0 ..............109 5.24.5.Register: LPOSCFREQ1, LPOSCFREQ0 ............. 110 5.24.6.Register: LPOSCPER1, LPOSCPER0 ..............110 5.25.DAC ........................110 5.25.1.Register: DACVALUE1, DACVALUE0 ..............110 5.25.2.Register: DACCONFIG ..................110 5.26.Performance Tuning Registers ................111 6.References ........................113 7.Contact Information ......................114 Version 1.9 Programming Manual AX5043...
Page 7: Overview
Wake-on-radio enable very low power standby applications. The AX5043 is also available with the AX8052F100 microcontroller in a single integrated circuit as the AX8052F143. Figure 1 shows the block diagram of the AX5043. AX5043 Digital IF Mixer Channel modulator IF Filter &...
Page 8 Connecting the interrupt line is highly recommended, though not strictly required. With the AX8052F100, it is also recommended to connect the SYSCLK line. This allows the Microcontroller to run from the precise crystal clock of the AX5043, or to calibrate its internal oscillators from against this clock.
Page 9 Can be programmed to be used as a general purpose I/O Selectable internal 65 kΩ pull-up resistor Serial peripheral interface select Serial peripheral interface clock MISO Serial peripheral interface data output MOSI Serial peripheral interface data input Must be left unconnected Version 1.9 Programming Manual AX5043...
Page 10 Registers are accessed via a synchronous Serial Peripheral Interface (SPI). Most Registers are 8 bits wide and accessed using the waveforms as detailed in Figure 3. These waveforms are compatible to most hardware SPI master controllers, and can easily be generated in Version 1.9 Programming Manual AX5043...
Page 11 During the address phase of the access, the chip outputs the most important status bits. This feature is designed to speed up software decision on what to do in an interrupt handler. The table below shows which register bit is transmitted during the status timeslots. Version 1.9 Programming Manual AX5043...
Page 12: Deep Sleep
The address space has been allocated as follows. Addresses from 0x000 to 0x06F are reserved for “dynamic registers”, i.e. registers that are expected to be frequently accessed during normal operation, as they can be efficiently accessed using single address byte SPI Version 1.9 Programming Manual AX5043...
Page 13 PLL, crystal oscillator. Adresses from 0x200 to 0x2FF have been reserved for medium access parameters, such as framing, packet handling. Addresses from 0x300 to 0x3FF have been reserved for special functions, such as GPADC. Version 1.9 Programming Manual AX5043...
Page 14: Fifo Operation
FIFOCOUNT FIFOFREE do not add up to 256 Bytes whenever there are uncommitted bytes in the FIFO. Figure 6 Illustrates this. Write ahead pointer Write pointer 256−FIFOFREE FIFOCOUNT Read pointer Figure 6: FIFO Pointer Version 1.9 Programming Manual AX5043...
Page 15 Variable length payload; payload size is encoded in the following length byte the length byte is part of the header (and not included in length), everything after the length byte is included in the length Version 1.9 Programming Manual AX5043...
Page 16: Nop Command
NOP C O M M A N D The NOP command will be discarded without efect by the transmitter. The receiver will not generate NOP commands. 2.1.2. RSSI C O M M A N D RSSI Version 1.9 Programming Manual AX5043...
Page 17: Rssi Command
PKTSTOREFLAGS. If DIVENA is set in register DIVERSITY, the ANTRSSI3 command is generated instead. The encoding of the RSSI field is the same as that of the RSSI register. The BGNDNOISE field contains an estimate of the background noise. Version 1.9 Programming Manual AX5043...
Page 18: Freqoffs Command
The RFFREQOFFS command will only be generated by the receiver at the end of a packet if bit STRFOFFS is set in register PKTSTOREFLAGS. The encoding is the same as that of the TRKRFFREQ register. Version 1.9 Programming Manual AX5043...
Page 19: Datarate Command
The DATA command transports actual transmit and receive data. While the basic format is the same for transmit and receive, the semantics of the flag byte difers. 2.1.11.1. RA N S M I T O R M AT LENGTH UNENC NOCRC RESIDUE PKTEND PKTSTART DATA ⁝ Version 1.9 Programming Manual AX5043...
Page 20 Flag Byte: Unencoded, to ensure 0-1 remains 0-1, and Residue set, because the number of bits transmitted is not a multiple of 8 0xAA Alternating 0-1 bits 0xAA Alternating 0-1 bits 0x1A Alternating 0-1 bits; Bit 4 is the “Stop” bit Version 1.9 Programming Manual AX5043...
Page 21 It is therefore important that the microcontroller receiver routine clears its receive bufer at the beginning of DATA commands whose PKTSTART bit is set, as the bufer may still contain bytes from erroneous packets. Version 1.9 Programming Manual AX5043...
Page 22: Txpwr Command
LENGTH = 10 TXPWRCOEFFA(7:0) TXPWRCOEFFA(15:8) TXPWRCOEFFB(7:0) TXPWRCOEFFB(15:8) TXPWRCOEFFC(7:0) TXPWRCOEFFC(15:8) TXPWRCOEFFD(7:0) TXPWRCOEFFD(15:8) TXPWRCOEFFE(7:0) TXPWRCOEFFE(15:8) The TXPWR command allows the transmit power to be changed on the fly. This command updates the TXPWRCOEFFA, TXPWRCOEFFB, TXPWRCOEFFC, TXPWRCOEFFD TXPWRCOEFFE registers. Version 1.9 Programming Manual AX5043...
Page 23: Programming The Chip
Set, and then clear, the RST bit of register PWRMODE. 2. Set the PWRMODE register to POWERDOWN. 3. Program parameters. It is recommended that suitable parameters are calculated using the AX_RadioLab tool available from Axsem. Version 1.9 Programming Manual AX5043...
Page 24: Autoranging
Each individual chip must be auto-ranged. If both frequency register sets FREQA FREQB are used, then both frequencies must be auto-ranged by first starting auto-ranging in PLLRANGINGA, waiting for its completion, followed by starting auto-ranging in PLLRANGINGB and waiting for its completion. Version 1.9 Programming Manual AX5043...
Page 25 If you have no prior knowledge about the correct range, set VCORA/VCORB to 8. Starting with VCORA/VCORB < 6 should be avoided, as the initial synthesizer frequency can exceed the maximum frequency specification. Version 1.9 Programming Manual AX5043...
Page 26 Inversion, diferential, manchester, scrambled, for recommendations see the description of the register ENCODING. The following table gives an overview of the trade-ofs between the diferent modulations that AX5043 ofers, they should be considered when making a choice. Modulation Trade-offs For bit rates up to 125 kbit/s Frequency deviation is a free parameter Version 1.9...
Page 27: Framing
3.4. F RA M I N G Figure 1 shows the block diagram of the AX5043. After the user writes a transmit packet into the FIFO, the Radio Controller sequences the transmitter start-up, and signals the Packet Controller to read the packet from the FIFO and add framing bits, allowing the receiver to lock to the transmit waveform, and to detect packet and byte boundaries.
Page 28 Diferential: Diferential transmits zero bits as constant level, and one bits as level • change. This allows to accomodate modulations that can invert the bit-stream, such as PSK. It is available for compatibility with other Axsem transceivers, but usually not used on the AX5043. Version 1.9...
Page 29: Transmitter
FIFO is no longer empty. It then powers up the synthesizer and settles it (registers TMGTXBOOST TMGTXSETTLE determine the timing). The Preamble and the Packet(s) are then transmitted, followed by the transmitter and synthesizer shut-down. Version 1.9 Programming Manual AX5043...
Page 30 (bit IRQMRADIOCTRL) in register IRQMASK0 and setting the radio controller to signal an interrupt at the end of transmission (bit REVMDONE of register RADIOEVENTMASK0). Version 1.9 Programming Manual AX5043...
Page 31: Receiver
FSKDMIN0 and FSKDMAX0) On the AX5043, these loops run in parallel. An AGC that is significantly of however causes the received signal to fall outside the IF strip dynamic range, and thus prevents the other loops from working. And a frequency ofset that is compensated insufficiently causes the received signal to fall (partially) outside the IF filter, thus also preventing the timing and 4- FSK loops from working.
Page 32 Figure 10 shows the receiver flow chart. When the microprocessor places the chip into FULLRX mode, the AX5043 immediately powers up the synthesizer, settles it (registers TMGRXBOOST TMGRXSETTLE determine the timing) and starts receiving. The reception continues until the microprocessor changes the PWRMODE register. Version 1.9 Programming Manual AX5043...
Page 33 Which meta-data is written to the FIFO is controlled by the register PKTSTOREFLAGS. Wake-on-Radio mode allows the AX5043 to periodically poll the radio channel for a transmission while using only very little power. Figure 11 shows the wake-on-radio flow Version 1.9 Programming Manual AX5043...
Page 34 AGC using a slower time constant. RSSI measures the received signal strength. This value is then used to determine whether the receiver should be kept running in wake- on-radio, or to select the antenna with the stronger signal in diversity mode. Version 1.9 Programming Manual AX5043...
Page 35 Once a frame start is detected, it switches to an even lower loop bandwidth. Figure 13 shows the state diagram that controls which receiver parameter set is used. Version 1.9 Programming Manual AX5043...
Page 36 This signal is then compared to the actual frequency of the Low Power Oscillator. The frequency diference is then low pass filtered (LPOSCKFILT register) and used to adjust the Low Power Oscillator frequency (LPOSCFREQ register). Version 1.9 Programming Manual AX5043...
Page 37: Auxiliary Dac
Its output voltage range is 0 to VDDIO for a DACVALUE range from −2048 to 2047. PWRAMP or ANTSEL Figure 15: DAC RC Filter A low pass filter, such as a simple R-C filter as shown in Figure 15, must be used to obtain the analog voltage. Version 1.9 Programming Manual AX5043...
Page 38 This signal is then sent to the DAC core. Note that if DACVALUE is selected as input, the register value is directly sent to the DAC, the shifter is not used. In fact, DACVALUE and DACSHIFT share the same register bits. Version 1.9 Programming Manual AX5043...
Page 39: Register Overview
00000000 IRQMASK(7:0) IRQ Mask RADIOEVENTMASK1 ‒‒‒‒‒‒‒0 ‒ ‒ ‒ ‒ ‒ ‒ ‒ RADIO Radio Event Mask EVENT MASK(8) RADIOEVENTMASK0 00000000 RADIO EVENT MASK(7:0) Radio Event Mask IRQINVERSION1 ‒‒‒00000 ‒ ‒ ‒ IRQINVERSION(12:8) IRQ Inversion Version 1.9 Programming Manual AX5043...
Page 40: Modulation And Framing
FEC NEG FEC POS FECINPSHIFT(2:0) FEC ENA FEC (Viterbi) Configuration TERBI FECSYNC 01100010 FECSYNC(7:0) Interleaver Synchronisation Threshold FECSTATUS ‒‒‒‒‒‒‒‒ FEC INV MAXMETRIC(6:0) FEC Status Status RADIOSTATE ‒ ‒‒‒‒0000 ‒ ‒ ‒ ‒ RADIOSTATE(3:0) Radio Controller State Version 1.9 Programming Manual AX5043...
Page 41: Status
Number of Words currently in FIFO FIFOFREE1 ‒‒‒‒‒‒‒1 ‒ ‒ ‒ ‒ ‒ ‒ ‒ FIFO Number of Words that can be FREE(8) written to FIFO FIFOFREE0 00000000 FIFOFREE(7:0) Number of Words that can be written to FIFO Version 1.9 Programming Manual AX5043...
Page 42: Synthesizer
PLL Charge Pump Current PLLRANGINGB 00001000 STICKY PLL LOCK RNGERR VCORB(3:0) PLL Autoranging LOCK START FREQB3 00111001 FREQB(31:24) Synthesizer Frequency FREQB2 00110100 FREQB(23:16) Synthesizer Frequency FREQB1 11001100 FREQB(15:8) Synthesizer Frequency FREQB0 11001101 FREQB(7:0) Synthesizer Frequency Version 1.9 Programming Manual AX5043...
Page 43: Signal Strength
TRKFREQ(15:8) Frequency Tracking TRKFREQ0 ‒‒‒‒‒‒‒‒ TRKFREQ(7:0) Frequency Tracking TRKFSKDEMOD1 ‒‒‒‒‒‒‒‒ ‒ ‒ TRKFSKDEMOD(13:8) FSK Demodulator Tracking TRKFSKDEMOD0 ‒‒‒‒‒‒‒‒ TRKFSKDEMOD(7:0) FSK Demodulator Tracking Timer TIMER2 ‒ ‒‒‒‒‒‒‒‒ TIMER(23:16) 1MHz Timer TIMER1 ‒ ‒‒‒‒‒‒‒‒ TIMER(15:8) 1MHz Timer Version 1.9 Programming Manual AX5043...
Page 44: Timer
00000000 RXDATARATE(23:16) Receiver Datarate RXDATARATE1 00111101 RXDATARATE(15:8) Receiver Datarate RXDATARATE0 10001010 RXDATARATE(7:0) Receiver Datarate MAXDROFFSET2 00000000 MAXDROFFSET(23:16) Maximum Receiver Datarate Ofset MAXDROFFSET1 00000000 MAXDROFFSET(15:8) Maximum Receiver Datarate Ofset MAXDROFFSET0 10011110 MAXDROFFSET(7:0) Maximum Receiver Datarate Ofset Version 1.9 Programming Manual AX5043...
Page 45: Receiver Parameters
Receiver Parameter Set 0 AGCGAIN0 10110100 AGCDECAY0(3:0) AGCATTACK0(3:0) AGC Speed AGCTARGET0 01110110 AGCTARGET0(7:0) AGC Target AGCAHYST0 ‒‒‒‒‒000 ‒ ‒ ‒ ‒ ‒ AGCAHYST0(2:0) AGC Digital Threshold Range AGCMINMAX0 ‒000‒000 ‒ AGCMAXDA0(2:0) ‒ AGCMINDA0(2:0) AGC Digital Minimum/Maximum Set Points Version 1.9 Programming Manual AX5043...
Page 46 Receiver Frequency Deviation FOURFSK0 ‒‒‒10110 ‒ ‒ ‒ DEVDECAY0(3:0) Four FSK Control UPDATE0 BBOFFSRES0 10001000 RESINTB0(3:0) RESINTA0(3:0) Baseband Ofset Compensation Resistors Receiver Parameter Set 1 AGCGAIN1 10110100 AGCDECAY1(3:0) AGCATTACK1(3:0) AGC Speed AGCTARGET1 01110110 AGCTARGET1(7:0) AGC Target Version 1.9 Programming Manual AX5043...
Page 47 BBOFFSRES1 10001000 RESINTB1(3:0) RESINTA1(3:0) Baseband Ofset Compensation Resistors Receiver Parameter Set 2 AGCGAIN2 11111111 AGCDECAY2(3:0) AGCATTACK2(3:0) AGC Speed AGCTARGET2 01110110 AGCTARGET2(7:0) AGC Target AGCAHYST2 ‒‒‒‒‒000 ‒ ‒ ‒ ‒ ‒ AGCAHYST2(2:0) AGC Digital Threshold Range Version 1.9 Programming Manual AX5043...
Page 48 BBOFFSRES2 10001000 RESINTB2(3:0) RESINTA2(3:0) Baseband Ofset Compensation Resistors Receiver Parameter Set 3 AGCGAIN3 11111111 AGCDECAY3(3:0) AGCATTACK3(3:0) AGC Speed AGCTARGET3 01110110 AGCTARGET3(7:0) AGC Target AGCAHYST3 ‒‒‒‒‒000 ‒ ‒ ‒ ‒ ‒ AGCAHYST3(2:0) AGC Digital Threshold Range Version 1.9 Programming Manual AX5043...
Page 49: Transmitter Parameters
Baseband Ofset Compensation Resistors Transmitter Parameters MODCFGF ‒‒‒‒‒‒00 ‒ ‒ ‒ ‒ ‒ ‒ FREQ SHAPE(1:0) Modulator Configuration F FSKDEV2 00000000 FSKDEV(23:16) FSK Frequency Deviation FSKDEV1 00001010 FSKDEV(15:8) FSK Frequency Deviation FSKDEV0 00111101 FSKDEV(7:0) FSK Frequency Deviation Version 1.9 Programming Manual AX5043...
Page 50: Pll Parameters
TXPWRCOEFFD(15:8) Transmitter Predistortion Coefficient D TXPWRCOEFFD0 00000000 TXPWRCOEFFD(7:0) Transmitter Predistortion Coefficient D TXPWRCOEFFE1 00000000 TXPWRCOEFFE(15:8) Transmitter Predistortion Coefficient E TXPWRCOEFFE0 00000000 TXPWRCOEFFE(7:0) Transmitter Predistortion Coefficient E PLL Parameters PLLVCOI 0‒010010 VCOIE ‒ VCOI(5:0) VCO Current Version 1.9 Programming Manual AX5043...
Page 51: Crystal Oscillator
Packet Address 3 PKTADDR2 00000000 ADDR(23:16) Packet Address 2 PKTADDR1 00000000 ADDR(15:8) Packet Address 1 PKTADDR0 00000000 ADDR(7:0) Packet Address 0 PKTADDRMASK3 00000000 ADDRMASK(31:24) Packet Address Mask 3 PKTADDRMASK2 00000000 ADDRMASK(23:16) Packet Address Mask 2 Version 1.9 Programming Manual AX5043...
Page 52 Pattern Match Unit 1, Minimum Match MATCH1MAX ‒‒‒‒1111 ‒ ‒ ‒ ‒ MATCH1MAX(3:0) Pattern Match Unit 1, Maximum Match Packet Controller TMGTXBOOST 00110010 TMGTXBOOSTE(2:0) TMGTXBOOSTM(4:0) Transmit PLL Boost Time TMGTXSETTLE 00001010 TMGTXSETTLEE(2:0) TMGTXSETTLEM(4:0) Transmit PLL (post Boost) Settling Time Version 1.9 Programming Manual AX5043...
Page 53: Baseband
ST CRCB ST RSSI ST DR ST FOFFS ST TIMER Packet Controller Store Flags RSSI RFOFFS PKTACCEPTFLAGS ‒‒000000 ‒ ‒ ACCPT ACCPT ACCPT ACCPT ACCPT ACCPT Packet Controller Accept Flags LRGP ADDRF CRCF ABRT RESIDUE Version 1.9 Programming Manual AX5043...
Page 54 01100001 LPOSCREF(15:8) Low Power Oscillator Calibration Reference LPOSCREF0 10101000 LPOSCREF(7:0) Low Power Oscillator Calibration Reference LPOSCFREQ1 00000000 LPOSCFREQ(9:2) Low Power Oscillator Calibration Frequency LPOSCFREQ0 0000‒‒‒‒ LPOSCFREQ(1:-2) ‒ ‒ ‒ ‒ Low Power Oscillator Calibration Frequency Version 1.9 Programming Manual AX5043...
Page 55 Period DACVALUE1 ‒‒‒‒0000 ‒ ‒ ‒ ‒ DACVALUE(11:8) DAC Value DACVALUE0 00000000 DACVALUE(7:0) DAC Value DACCONFIG 00‒‒0000 DAC PWM DAC CLK ‒ ‒ DACINPUT(3:0) DAC Configuration Performance Tuning Registers F00‒ PERFTUNE ‒‒‒‒‒‒‒‒ Performance Tuning Registers Version 1.9 Programming Manual AX5043...
Page 56 7:0 R 11000101 Scratch Register The SCRATCH register does not afect the function of the chip in any way. It is intended for the Microcontroller to test communication to the AX5043. 5.2. O P E R AT I N G O D E 5.2.1.
Page 57 ‒ Sticky Analog Domain Voltage Regulator Ready SSVREF ‒ Sticky Reference Voltage Regulator Ready SSREF ‒ Sticky Reference Ready SSSUM ‒ Sticky Summary Ready Status (zero when any unmasked POWIRQMASK power sources is not ready) Version 1.9 Programming Manual AX5043...
Page 58 Crystal Oscillator Ready interrupt enable IRQMWAKEUPTIMER 9 RW 0 Wakeup Timer interrupt enable IRQMLPOSC RW 0 Low Power Oscillator interrupt enable IRQMGPADC RW 0 GPADC interrupt enable IRQMPLLRNGDONE RW 0 PLL autoranging done interrupt enable Version 1.9 Programming Manual AX5043...
Page 59 GPADC interrupt inversion IRQINVPLLRNGDONE 12 RW 0 PLL autoranging done interrupt inversion 5.4.4. : IRQREQUEST1, IRQREQUEST0 E G I S T E R Name Bits R/W Reset Description IRQRQFIFONOTEMPT 0 ‒ FIFO not empty interrupt pending Version 1.9 Programming Manual AX5043...
Page 60 RA M I N G 5.5.1. : MODUL ATION E G I S T E R Name Bits R/W Reset Description MODULATION 3:0 RW 1000 Bits Meaning 0000 0001 ASK Coherent 0100 0110 OQSK 0111 Version 1.9 Programming Manual AX5043...
Page 61 The scrambler polynomial is 1 + X , it is therefore compatible to the K9NG/G3RUH Satellite Modems. Figure 17 and Figure 18 show schematic diagrams of the scrambler and the descrambler operation. The numbered boxes represent delays by one bit. Version 1.9 Programming Manual AX5043...
Page 62 It encodes 1 as no transition at the bit center, and 0 MANCH=1 as a transition at the bit center. Manchester INV=0, DIFF=0, Manchester encodes 1 as a 10 pattern, and 0 as a 01 SCRAM=0, pattern. Manchester is not inversion invariant. MANCH=1 Guidelines: Version 1.9 Programming Manual AX5043...
Page 63: Pattern Match
Note: The wireless M-Bus definition of “Manchester” is inverse to the definition used by the AX5043. AX5043 defines “Manchester” as the transmission of the data bit followed by the transmission of the inverted data bit. Wireless M-Bus defines it the other way around. In...
Page 64 The Convolutional Code is a nonsystematic Rate ½ code with the generators g = 1 + D and g = 1 + D + D . It has a minimum free distance of d = 7. Figure 20 shows a free schematic diagram of the convolutional encoder. Version 1.9 Programming Manual AX5043...
Page 65 0000 Idle 0001 Powerdown 0100 Tx PLL Settling 0110 Tx 0111 Tx Tail 1000 Rx PLL Settling 1001 Rx Antenna Selection 1100 Rx Preamble 1 1101 Rx Preamble 2 1110 Rx Preamble 3 1111 Rx Version 1.9 Programming Manual AX5043...
Page 66 SYSCLK Output inverted f XTAL 00100 SYSCLK Output f XTAL XTAL 00101 SYSCLK Output XTAL 00110 SYSCLK Output XTAL 00111 SYSCLK Output XTAL 01000 SYSCLK Output XTAL 01001 SYSCLK Output XTAL 01010 SYSCLK Output XTAL 01011 SYSCLK Output Version 1.9 Programming Manual AX5043...
Page 67 DATA, and you do not want to generate a clock yourself 110 invalid 111 DCLK Output Test Observation PIDCLK RW 0 DCLK inversion PUDCLK RW 0 DCLK weak Pullup enable Version 1.9 Programming Manual AX5043...
Page 68 Name Bits R/W Reset Description PFANTSEL 2:0 RW 110 Bits Meaning 000 ANTSEL Output ’0’ 001 ANTSEL Output ’1’ 010 ANTSEL Output ’Z’ 011 ANTSEL Output Baseband Tune Clock 100 ANTSEL Output External TCXO Enable Version 1.9 Programming Manual AX5043...
Page 69 E G I S T E R Name Bits R/W Reset Description PWRAMP RW 0 Power Amplifier Control The PWRAMP bit may be output on the PWRAMP pin. This signal may be used to control an external power amplifier. Version 1.9 Programming Manual AX5043...
Page 70 Clear FIFO Data and Flags 000100 Commit 000101 Rollback 000110 Invalid 000111 Invalid 001XXX Invalid 01XXXX Invalid 1XXXXX Invalid FIFO AUTO COMMIT 7 RW 0 If one, FIFO write bytes are automatically commited on every write Version 1.9 Programming Manual AX5043...
Page 71 E G I S T E R The PLLLOOP and PLLLOOPBOOST select PLL Loop Filter configuration for both normal mode and boosted mode. All fields in this register are separate, except for FREQSEL, which is common to both registers. Version 1.9 Programming Manual AX5043...
Page 72 RF divider: 0=no RF divider, 1=divide RF by 2 VCOSEL RW 0 0=fully internal VCO1, 1=internal VCO2 with external inductor or external VCO, depending on VCO2INT VCO2INT RW 0 1=internal VCO2 with external Inductor, 0=external VCO Version 1.9 Programming Manual AX5043...
Page 73 It is strongly recommended to always set bit 0 to avoid spectral tones. 5.10.6. : FREQB3, FREQB2, FREQB1, FREQB0 E G I S T E R Name Bits R/W Reset Description FREQB 31:0 RW 0x3934CCCD ⌊ ⌋ CARRIER FREQB= Frequency; ⋅2 XTAL See notes of FREQA register. Version 1.9 Programming Manual AX5043...
Page 74 Bits R/W Reset Description TRKDATARATE 23:0 R ‒ Current datarate tracking value 5.12.2. : TRKAMPL1, TRKAMPL0 E G I S T E R Name Bits R/W Reset Description TRKAMPL 15:0 R ‒ Current amplitude tracking value Version 1.9 Programming Manual AX5043...
Page 75 Bits R/W Reset Description TRKFSKDEMOD 13:0 R ‒ Current FSK demodulator value 5.12.7. : TRKAFSKDEMOD1, TRKAFSKDEMOD0 E G I S T E R Name Bits R/W Reset Description TRKAFSKDEMOD 15:0 R ‒ Current AFSK demodulator value Version 1.9 Programming Manual AX5043...
Page 76 1. The counting frequency can be set to 640Hz or 10.24kHz (register LPOSCCONFIG). Whenever the WAKEUPTIMER register matches the WAKEUP register, an event is signalled, and the WAKEUPFREQ register is added to the WAKEUP register, to prepare for the next wakeup event. Version 1.9 Programming Manual AX5043...
Page 77 Name Bits R/W Reset Description IFFREQ 15:0 RW 0x1327 ⌊ ⌋ ⋅f XTALDIV IF Frequency; IFFREQ= ⋅ 2 XTAL Please use the AX_RadioLab software to calculate the optimum IF frequency for given physical layer parameters. Version 1.9 Programming Manual AX5043...
Page 78 19:0 RW 0x01687 ⌊ ⌋ Δ f CARRIER MAXRFOFFSET= ⋅2 XTAL FREQOFFSCORR RW 0 Correct frequency ofset at the first LO if this bit is one; at the second LO if this bit is zero Version 1.9 Programming Manual AX5043...
Page 79 AFSK Space (0-Bit encoding) Frequency For receive, the register should be computed as follows: ⌊ ⌋ ⋅DECIMATION⋅f ⋅2 AFSKSPACE XTALDIV AFSKSPACE= XTAL For transmit, the register has a slightly diferent definition: ⌊ ⌋ ⋅2 AFSKSPACE AFSKSPACE= XTAL Version 1.9 Programming Manual AX5043...
Page 80 E G I S T E R Name Bits R/W Reset Description AMPLFILTER 3:0 RW 0000 3dB corner frequency of the Amplitude (Magnitude) Lowpass Filter; +2⋅k−2 XTAL ⋅arccos 2⋅(k−1) ⋅π⋅f ⋅DECIMATION XTALDIV with −AMPLFILTER 0000: Filter bypassed Version 1.9 Programming Manual AX5043...
Page 81 Baseband Ofset Acquisition 5.15.15. : AGCGAIN0, AGCGAIN1, AGCGAIN2, AGCGAIN3 E G I S T E R Name Bits R/W Reset Description AGCATTACK0 3:0 RW 0100 AGC gain reduction speed AGCATTACK1 0100 AGCATTACK2 1111 AGCATTACK3 1111 Version 1.9 Programming Manual AX5043...
Page 82 E G I S T E R AGCTARGET3 Name Bits R/W Reset Description AGCTARGET0 7:0 RW 01110110 The target ADC output average magnitude is AGCTARGETx . Note that the ADC can produce AGCTARGET1 01110110 magnitudes from 0…2 AGCTARGET2 01110110 Version 1.9 Programming Manual AX5043...
Page 83 : TIMEGAIN0, TIMEGAIN1, TIMEGAIN2, TIMEGAIN3 E G I S T E R Name Bits R/W Reset Description TIMEGAIN0E 3:0 RW 1000 Gain of the timing recovery loop; this is the exponent TIMEGAIN1E 0110 TIMEGAIN2E 0101 TIMEGAIN3E 0101 Version 1.9 Programming Manual AX5043...
Page 84 5.15.21. : PHASEGAIN0, PHASEGAIN1, PHASEGAIN2, E G I S T E R PHASEGAIN3 Name Bits R/W Reset Description PHASEGAIN0 3:0 RW 0011 Gain of the phase recovery loop PHASEGAIN1 0011 PHASEGAIN2 0011 PHASEGAIN3 0011 Version 1.9 Programming Manual AX5043...
Page 85 FREQAMPLGATE0 RW 0 If set to 1, only update the frequency ofset recovery loops if the amplitude of the signal is FREQAMPLGATE1 larger than half the maximum (or larger than the average amplitude) FREQAMPLGATE2 FREQAMPLGATE3 Version 1.9 Programming Manual AX5043...
Page 86 FREQAVG3 FREQFREEZE0 RW 0 Freeze the baseband frequency recovery loop if FREQFREEZE1 FREQFREEZE2 FREQFREEZE3 Set FREQGAINA0 = 15 and FREQGAINB0 = 31 to completely disable the baseband frequency recovery loop, setting its output to zero. Version 1.9 Programming Manual AX5043...
Page 87 5.15.26. : AMPLGAIN0, AMPLGAIN1, AMPLGAIN2, AMPLGAIN3 E G I S T E R Name Bits R/W Reset Description AMPLGAIN0 3:0 RW 0110 Gain of the amplitude recovery loop AMPLGAIN1 0110 AMPLGAIN2 0110 AMPLGAIN3 0110 Version 1.9 Programming Manual AX5043...
Page 88 : FOURFSK0, FOURFSK1, FOURFSK2, FOURFSK3 E G I S T E R Name Bits R/W Reset Description DEVDECAY0 3:0 RW 0110 Deviation Decay DEVDECAY1 1000 DEVDECAY2 1010 DEVDECAY3 1010 DEVUPDATE0 RW 1 Enable Deviation Update DEVUPDATE1 DEVUPDATE2 DEVUPDATE3 Version 1.9 Programming Manual AX5043...
Page 89 The shift register shifts right, so the bits end up in the FIFO word as follows: Version 1.9 Programming Manual AX5043...
Page 90 The amount of leakage is controlled by DEVDECAY . DEVDECAY # Samples to Decay to 0.5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1419 1100 2839 1101 5678 1110 11356 1111 22713 Version 1.9 Programming Manual AX5043...
Page 91 FSKDEV = ⋅2 XTAL Note that f is actually half the deviation. The mark frequency is f , the DEV IATION CARRIER DEV IATION space frequency is f − f CARRIER DEV IATION ⋅BITRATE DEVIATION Version 1.9 Programming Manual AX5043...
Page 92 ± ADCFS⋅f XTAL 110 FM: DEVIATION ± ADCFS⋅f XTAL 111 FM: DEVIATION FMINPUT 9:8 RW 10 Input Selection Bits Meaning GPADC13 GPADC1 GPADC2 GPADC3 FMSEXT RW 0 ADC Sign Extension FMOFFS RW 0 ADC Ofset Subtract Version 1.9 Programming Manual AX5043...
Page 93 Transmit Bitrate XTAL XTAL In asynchronous wire mode, BITRATE< 5.16.5. : TXPWRCOEFFA1, TXPWRCOEFFA0 E G I S T E R Name Bits R/W Reset Description TXPWRCOEFFA 15:0 RW 0x0000 ⌊ ⌋ Transmit Predistortion TXPWRCOEFFA= α ⋅2 Version 1.9 Programming Manual AX5043...
Page 94 5.16.8. : TXPW RCOEFFD1, TXPWRCOEFFD 0 E G I S T E R Name Bits R/W Reset Description TXPWRCOEFFD 15:0 RW 0x0000 Transmit Predistortion ⌊ ⌋ TXPWRCOEFFD= α ⋅2 TXPWRCOEFFB0 for an explanation. Version 1.9 Programming Manual AX5043...
Page 95 Lock Detector Delay 14ns LOCKDETDLYM RW 0 0=Automatic Lock Delay (determined by the currently active frequency register); 1=Manual Lock Delay (Bits LOCKDETDLY) LOCKDETDLYR 7:6 R ‒ Lock Detect Read Back (not valid in power down mode) Version 1.9 Programming Manual AX5043...
Page 96 Bits R/W Reset Description XTALCAP 7:0 RW 00000000 Load Capacitance Configuration Bits (5:0) Meaning 000000 000001 8.5pF 000010 ⁝ ⁝ 110111 36pF ⁝ ⁝ 111111 40pF For values XTALCAP(5:0)≠0, C = 8pF + 0.5pF ⋅ XTALCAP(5:0). Version 1.9 Programming Manual AX5043...
Page 97 The built-in packet length logic can support up to 255 byte packets. It is still possible to receive larger packets if packet length and, unless using HDLC, CRC is handled in the microprocessor firmware. In order to enable reception of arbitrary length packets, the following settings must be made: Version 1.9 Programming Manual AX5043...
Page 98 Description MAX LEN 7:0 RW 0x00 Packet Maximum Length 5.20.5. : PKTADD R3, PKTADD R2, PKTADDR1, PKTADDR0 E G I S T E R Name Bits R/W Reset Description ADDR 31:0 RW 0x00000000 Packet Address Version 1.9 Programming Manual AX5043...
Page 99 5.21.4. : MATCH0MAX E G I S T E R Name Bits R/W Reset Description MATCH0MAX 4:0 RW 11111 A match is signalled if the received bitstream matches the pattern in more than MATCH0MAX positions. Version 1.9 Programming Manual AX5043...
Page 100 E G I S T E R Name Bits R/W Reset Description TMGTXBOOSTM 4:0 RW 10010 Transmit PLL Boost Time Mantissa TMGTXBOOSTE 7:5 RW 001 Transmit PLL Boost Time Exponent The Transmit PLL Boost Time is TMGTXBOOSTM ⋅ 2 μs. TMGTXBOOSTE Version 1.9 Programming Manual AX5043...
Page 101 μs. TMGRXOFFSACQE 5.22.6. : TMGRXCOARSEAGC E G I S T E R Name Bits R/W Reset Description TMGRXCOARSEAGC 4:0 RW 11001 Receive Coarse AGC Time Mantissa TMGRXCOARSEAGCE 7:5 RW 001 Receive Coarse AGC Time Exponent Version 1.9 Programming Manual AX5043...
Page 102 E G I S T E R Name Bits R/W Reset Description TMGRXPREAMBLE2M 4:0 RW 00000 Receiver Preamble 2 Timeout Mantissa TMGRXPREAMBLE2E 7:5 RW 000 Receiver Preamble 2 Timeout Exponent The Receiver Preamble 2 Timeout is TMGRXPREAMBLE2M ⋅ 2 Bits. TMGRXPREAMBLE2E Version 1.9 Programming Manual AX5043...
Page 103 Antenna RSSI measurement is performed in state RSSI in the Receiver Timing Diagram Figure 12. The background RSSI estimate is updated only once if antenna selection is performed. The update is performed as follows: −BGNDRSSIGAIN BGNDRSSI :=BGNDRSSI + ( RSSI −BGNDRSSI )⋅ 2 Version 1.9 Programming Manual AX5043...
Page 104 E G I S T E R Name Bits R/W Reset Description RXRSSI CLK RW 0 Clock source for RSSI settling timeout: 0=1μs, 1=Bit clock RXAGC CLK RW 0 Clock source for AGC settling timeout: 0=1μs, 1=Bit clock Version 1.9 Programming Manual AX5043...
Page 105 Accept Packets that fail CRC check ACCPT ADDRF RW 0 Accept Packets that fail Address check ACCPT SZF RW 0 Accept Packets that are too long ACCPT LRGP RW 0 Accept Packets that span multiple FIFO chunks Version 1.9 Programming Manual AX5043...
Page 106 LPOSC IRQR RW 0 Enable LP Oscillator Interrupt on the Rising Edge LPOSC IRQF RW 0 Enable LP Oscillator Interrupt on the Falling Edge LPOSC CALIBF RW 0 Enable LP Oscillator Calibration on the Falling Edge Version 1.9 Programming Manual AX5043...
Page 107: Low Power Oscillator Calibration
FILT 5.24.4. : LPOSCREF1, LPOSCREF0 E G I S T E R Name Bits R/W Reset Description LPOSCREF 15:0 RW 0x61A8 LP Oscillator Reference Frequency Divider; set to XTAL 640Hz Version 1.9 Programming Manual AX5043...
Page 108 3:0 RW 0000 DAC Input Multiplexer Bits Meaning 0000 DACVALUE 0001 TRKAMPLITUDE 0010 TRKRFFREQUENCY 0011 TRKFREQUENCY 0100 FSKDEMOD 0101 AFSKDEMOD 0110 RXSOFTDATA 0111 RSSI 1000 SAMPLE_ROT_I 1001 SAMPLE_ROT_Q 1100 GPADC13 1101 invalid 1110 invalid 1111 invalid Version 1.9 Programming Manual AX5043...
Page 109: Performance Tuning Registers
This register should be reset between WOR wake-ups. The reset value is the value read after successful packet reception or 0x3F if no packet has been received yet. This register should be reset between WOR wake-ups. The reset value is the Version 1.9 Programming Manual AX5043...
Page 110: References
RX/TX Set to 0x10 for reference frequencies (crystal or TCXO) less than 24.8MHz (⟶ f =1), or to 0x11 otherwise (⟶ f XTALDIV XTALDIV RX/TX Set to 0x24 Set to 0x06 if the framing mode is set to “Raw, Soft Bits” (register FRAMING), or to 0x00 otherwise Version 1.9 Programming Manual AX5043...
Page 111 References 6. R E F E R E N C E S Wikipedia. High-Level Data Link Control. http://en.wikipedia.org/wiki/HDLC. Axsem AG. AX5043 Datasheet. http://www.axsem.com Ross N. Williams. A Painless Guide to CRC Error Detection Algorithms. http://www.ross.net/crc/download/crc_v3.txt Version 1.9 Programming Manual AX5043...
Page 112: Contact Information
The specifications in this document are subject to change at AXSEM's discretion. AXSEM assumes no responsibility for any claims or damages arising out of the use of this document, or from the use of products based on this document, including but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights.