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Lattice Semiconductor LatticeMico8 Reference Manual

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LatticeMico8 Processor
Reference Manual
October 2014

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  • Page 1 LatticeMico8 Processor Reference Manual October 2014...
  • Page 2 Copyright Copyright © 2014 Lattice Semiconductor Corporation. All rights reserved. This document may not, in whole or part, be reproduced, modified, distributed, or publicly displayed without prior written consent from Lattice Semiconductor Corporation (“Lattice”). Trademarks All Lattice trademarks are as listed at www.latticesemi.com/legal. Synopsys and Synplify Pro are trademarks of Synopsys, Inc.
  • Page 3 Omitted lines in code and report examples. Optional items in syntax descriptions. In bus specifications, the brackets are required. Grouped items in syntax descriptions. Repeatable items in syntax descriptions. A choice between items in syntax descriptions. LatticeMico8 Processor Reference Manual...
  • Page 4 LatticeMico8 Processor Reference Manual...

  • Page 5: Table Of Contents

    Instruction Set Lookup Table 14 Instruction Descriptions 16 Programming Model Data Representation 37 Procedure Caller-Callee Convention 38 Register Usage 38 Stack Frame 39 Parameter Passing 40 Interrupt Convention 41 Acessing LatticeMico8 Memory Regions 42 Scratchpad 42 Peripheral 42 PROM 43 LatticeMico8 Processor Reference Manual...
  • Page 6 ONTENTS Index LatticeMico8 Processor Reference Manual...

  • Page 7: Introduction

    Chapter 1 Introduction The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Programmable Logic Device architectures from Lattice Semiconductor. It combines a full 18-bit wide instruction set with 16 or 32 general-purpose registers. It is suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial and automotive.
  • Page 8 NTRODUCTION Figure 1: LatticeMico8 Microcontroller Core LatticeMico8 Processor Reference Manual...

  • Page 9: Architecture

    256 bytes (see “Memory Modes” on page 9). The memory address is formed by concatenating the values in registers R13, R14, and R15 with an 8-bit value derived from the LatticeMico8 memory instruction. Table 1 on page 4 highlights the three LatticeMico8 memory modes and corresponding designation of registers R13, R14, and R15.

  • Page 10: Control And Status Registers

    : Register Architecture RCHITECTURE  In the medium memory mode, register R13 indicates which of the 256 pages is currently active. Table 1: Designation of LatticeMico8 Registers Based on LatticeMico8 Memory Mode LatticeMico8 Memory Mode Register Number Small Medium Large...

  • Page 11: Memory Architecture

    LatticeMico System Builder. Figure 2 shows the three memory regions and the address space to which they are confined by LatticeMico System Builder. See “Acessing LatticeMico8 Memory Regions” on page 42 for details on how to access each of the three memory regions from a software programmer's perspective.
  • Page 12 256, 512, 1024, 2048, or 4096 instruction opcodes. By default the memory region is located within the LatticeMico8 microcontroller. The memory regions can also be configured to be external to the LatticeMico8 microcontroller. When the PROM memory region is internal to the microcontroller, it is connected to the LatticeMico8 instruction fetch engine via a dedicated high- speed bus that fetches one instruction opcode per clock cycle.
  • Page 13  The internal scratchpad is implemented using single-port EBRs and is hooked up to the LatticeMico8 core through a dedicated bus. Reads or writes to the internal scratchpad take a single clock cycle.  The external scratchpad is accessed through the Peripheral WISHONE interface of the LatticeMico8 microcontroller (see “Interrupt Architecture”...
  • Page 14 : Memory Architecture RCHITECTURE Peripheral (Input/Output) Space LatticeMico8 provides an independent memory space that is designed to be used for peripherals and other memory-mapped hardware. The size of this peripheral memory space can be configured from 0 bytes to 4G bytes in power-of-two increments.

  • Page 15: Memory Modes

    Set” on page 13.) To access memory regions that are larger than 256 bytes, LatticeMico8 relies on a concept called “paging,” in which the memory is logically divided into 256-byte pages. The memory address is composed of two parts, as shown in Figure 4: the page index and the page pointer. The page index is 8 bits wide and addresses a byte in the currently active page, while the page pointer provides the address of the currently active page.

  • Page 16: Interrupt Architecture

    (call instruction) and procedure/interrupt return (ret and iret instructions). The depth of this call stack determines the number of nested procedure calls that can be handled by the LatticeMico8 microcontroller, and designers can choose the depth to be 8, 16, or 32. When a call instruction is executed, the address of the next instruction is pushed on to the call stack.

  • Page 17: Configuration Options

    Chapter 3 Configuration Options The LatticeMico8 microcontroller is reconfigurable. Table 6 outlines the various configuration options that are available to a designer. Table 6: LatticeMico8 Configuration Options Parameter Name Description LATTICE_FAMILY The target Lattice FPGA family. CFG_PROM_INIT_FILE Provides the file that contains the initialization data (program code) for an internal PROM.
  • Page 18 PROM image. The default is 0, i.e., both memories are different. 1 indicates that both memories are the same (i.e., no copying needs to be done) and the PROM is external to LatticeMico8. INTERRUPTS Indicates the number of external interrupts. The default is 8.

  • Page 19: Instruction Set

    This chapter includes descriptions of all the instruction opcodes of the LatticeMico8 microcontroller. Instruction Formats All LatticeMico8 instructions are 18 bits wide. They are in three basic formats, as shown in Figure 5, Figure 6, and Figure 7. Figure 5: Register-Register Format...

  • Page 20: Instruction Set Lookup Table

    IRET PC, Carry, Zero = Stack Carry, Zero LSP RD, SS Rd = Scratchpad (SS) LSPI Rd, Rb Rd = Scratchpad (Page Pointer, Rb) MOV Rd, Rb Rd = Rb MOVI Rd, C Rd = Const LatticeMico8 Processor Reference Manual...
  • Page 21 Rd & Rb Zero TESTI Rd, C Rd & C Zero XOR Rd, Rb Rd = Rd ^ Rb Zero XORI Rd, C Rd = Rd ^ C Zero WCSR CRd, Rb CSR (Rd) = Rb Zero LatticeMico8 Processor Reference Manual...

  • Page 22: Instruction Descriptions

    Rd = Rd + Rb + Carry Flag (add registers and carry flag) The carry flag is updated with the carry out from the addition. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 23 1 if all the bits of the result are 0. AND Rd, Rb CY Flag Updated Zero Flag Updated Rd = Rd and Rb (bitwise AND registers) The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 24 Branch if carry. If carry flag is set, the PC is incremented by the signed offset of the label from the current PC. If carry flag is not set, then execution continues with the following instruction. The offset can be +2047/-2048. LatticeMico8 Processor Reference Manual...
  • Page 25 Branch if 0. If zero flag is set, the PC is incremented by the signed offset of the label from the current PC. If zero flag is 0, then execution continues with the following instruction. The offset can be +2047/-2048. LatticeMico8 Processor Reference Manual...
  • Page 26 1) is pushed into the call stack and the PC is incremented by the signed offset (+2047/-2048) of the label from the current PC. If the carry flag is not set, then execution continues from the following instruction. LatticeMico8 Processor Reference Manual...
  • Page 27 (PC + 1) is pushed into the call stack and the PC is incremented by the signed offset (+2047/-2048) of the label from the current PC. If the zero flag is set, then execution continues from the following instruction. LatticeMico8 Processor Reference Manual...
  • Page 28 CLRC CY Flag Updated Zero Flag Updated Carry Flag = 0 Clear carry flag. CLRI CY Flag Updated Zero Flag Updated Interrupt Enable Flag = 0 Clear interrupt enable flag. Disable interrupts. LatticeMico8 Processor Reference Manual...
  • Page 29 Subtract Constant from Rd and update the flags. The result of the subtraction is not written back. The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 30 Rb. In small memory mode, the peripheral address can be 0 - 255. In medium memory mode, the peripheral address can be 0 - 64K. In large memory mode, the peripheral address can be 0 - 4Gbyte. LatticeMico8 Processor Reference Manual...
  • Page 31 PC = Top of Call Stack Pop Call Stack Restore Zero and Carry Flags from Call Stack Return from interrupt. In addition to popping the call stack, the carry and zero flags are restored from shadow locations. LatticeMico8 Processor Reference Manual...
  • Page 32 0 - 4Gbyte. MOV Rd, Rb CY Flag Updated Zero Flag Updated Rd = Rb (move register to register) The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 33 No operation moves R0 to R0. OR Rd, Rb CY Flag Updated Zero Flag Updated Rd = Rd | Rb (bitwise OR registers) The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 34 The zero flag is set to 1 if all the bits of the result are 0. CY Flag Updated Zero Flag Updated PC = Top of Call Stack Pop Call Stack Unconditional return. PC is set to the value on the top of the call stack. LatticeMico8 Processor Reference Manual...
  • Page 35 The result is written back to Register Rd. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 36 The result is written back to Register Rd. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 37 Carry Flag = 1 Set carry flag. SETI CY Flag Updated Zero Flag Updated Interrupt Enable Flag = 1 Set interrupt enable flag. Enable interrupt. SETZ CY Flag Updated Zero Flag Updated Zero Flag = 1 Set zero flag. LatticeMico8 Processor Reference Manual...
  • Page 38 Rb. In small memory mode, the peripheral address can be 0 - 255. In medium memory mode, the peripheral address can be 0 - 64K. In large memory mode, the peripheral address can be 0 - 4Gbyte. LatticeMico8 Processor Reference Manual...
  • Page 39 Rd = Rd - CCCCCCCC (subtract constant from register) The carry flag is set to 1 if the result is negative. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 40 Perform a bitwise AND between Rd and Constant, update the zero flag. The result of the AND operation is not written back. The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 41 The zero flag is set to 1 if all the bits of the result are 0. XORI Rd, C CY Flag Updated Zero Flag Updated Rd = Rd and CC (bitwise XOR register with constant) The zero flag is set to 1 if all the bits of the result are 0. LatticeMico8 Processor Reference Manual...
  • Page 42 : Instruction Descriptions NSTRUCTION LatticeMico8 Processor Reference Manual...

  • Page 43: Programming Model

    This chapter describes the LatticeMico8 programming model, including data types, calling sequence, and interrupt convention. Data Representation The LatticeMico8 microcontroller supports the data types listed in Table 8. Table 8: LatticeMico8 Data Types Size in Memory Model Alignment in Memory Model...

  • Page 44: Procedure Caller-Callee Convention

    Register Usage The register usage model shown in Table 9 is used by the LatticeMico8 Compiler. It must be used by developers who are writing ASM code that will be compiled into an executable using the LatticeMico8 compiler.

  • Page 45: Stack Frame

    All frames must be aligned. The first 32 bytes below the stack frame are reserved for leaf functions that do not need to modify the stack pointer. Interrupt handlers must guarantee that they will not use this area. LatticeMico8 Processor Reference Manual...

  • Page 46: Parameter Passing

    R0-R3. Void functions leave registers R0-R3 undefined. A function that returns a small structure or union places the returned value in registers R0-R3. Other structures and unions are returned in memory, pointed by the “invisible” first function argument. LatticeMico8 Processor Reference Manual...

  • Page 47: Interrupt Convention

    "interrupt" attribute. For this interrupt handler to link correctly, it must be named "__IRQ". An example is shown in Figure 8. Figure 8: LatticeMico8 Interrupt Handler __attribute ((interrupt)) __IRQ (void) // user's interrupt handling code...

  • Page 48: Acessing Latticemico8 Memory Regions

    Scratchpad The LatticeMico8 Scratchpad can be read from (or written to) using LatticeMico8 instructions - lsp, lspi, ssp, and sspi - regardless of whether it is internal or external to the microcontroller. The developer should note that the LatticeMico8 compiler always defaults to the Scratchpad for its data reads/ writes.

  • Page 49: Prom

    PROM The LatticeMico8 PROM can either be internal to the microcontroller, or can be externally located within a non-volatile memory such as SPI flash. When the PROM is internal to the microcontroller, it cannot be modified via the LatticeMico8 instruction set.
  • Page 50 : Acessing LatticeMico8 Memory Regions ROGRAMMING ODEL LatticeMico8 Processor Reference Manual...
  • Page 51 4 LatticeMico8 general-purpose 3 compiler 38 page pointers 9 features 1 ret 10 microcontroller core 2 lookup table 14 scratchpad interrupt handling 10 memory size 7 address 3 space 7 implementation of registers 3 LatticeMico8 Processor Reference Manual...
  • Page 52 NDEX stack frame layout 39 interrupt 41 pointer 39 WISHBONE peripheral interface signals 8 PROM interface signals 6 LatticeMico8 Processor Reference Manual...

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