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Model 5065A
Circuit Diagrams, Theory, and Maintenance
A3, Clock Display Board
The clock display board consists of a MOS clock chip, a
transistor array, a buffer amplifier array, four driver
transistors and six LED displays. This assembly's func
tion is to accumulate and display time-of-day in synchro
nism with the instruments' 1 PPS signal.
The MOS clock circuit U1 operates from the 50 Hz input
from A2 50 Hz logic board. U1 divides the 50 Hz signal by
50 and generates a 1 PPS output at pin 20 which is used
to synchronize the display to the instrument 1 PPS signal.
Counter stages with U1 divide the input 50 Hz signal and
generate the hours, minutes, and seconds outputs for
the LED displays.
The time display signals from U1 are comprised of two
parts:
1. The digit enable signal.
2. The multiplexed 7-segment signal.
The digits enable signals from U1 are:
Pin 23: tens-of-hours.
Pin 24: units-of-hours.
Pin 25: tens-of-minutes.
Pin 26: units-of-minutes.
Pin 21: tens-of-seconds.
Pin 22: units-of-seconds.
These signals enable the LED displays through U3 gates,
and allow the multiplexed 7 segments outputs to turn-
on the correct display segment.
The multiplexed 7 segment signals from U1 are (see
Figure
for "segments"):
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
for segment a.
for segment b.
for segment c.
for segment d.
for segment e.
for segment f.
for segment g.
/ • ;
■/
These "segment enabling signals" are buffered through
U2 stages and applied to the LED displays. Thus, the
segments of an individual number display are enabled
by outputs from U1(6 to 12) while the number itself is
turned on by one of the U1 (21 to 26) outputs.
MAINTENANCE
General
The A19 LED Digital Clock Assembly has no adjustments
and requires no periodic maintenance. Should repair be
necessary, the unit may be removed and operated on
the bench while remaining connected to the instrument.
When operating in this manner, however, the clock
chassis or circuit common must be connected to the
instrument chassis with a CLIP LEAD OR JUMPER WIRE.
The following paragraphs describe assembly removal,
fault finding procedures for the clock system, and
troubleshooting information for the individual circuits.
NOTE
Most of the circuits on the 50 Hz LOGIC and
CLOCK DISPLAY assemblies are CMOS. Use
high impedance tet equipment when checking
signals. Precautions should be taken when
removing or replacing these circuits to pre
vent damage from static charges.
Repairs
Before repairs are attempted:
a.
Momentarily set front panel DIVIDER MODE
switch to START.
Check CIRCUIT CHECK meter in 1 MHz position
for reading of approximately 40. If not, trouble-
shoot A6 assembly.
Check front panel 1 PPS output. If not present,
troubleshoot A5 assembly.
d.
If the display is not lit, press STANDBY DISPLAY
switch. If display lights and operates normally, the
instrument is not operating from AC power. This
condition is normal. If the display does not light
when the STANDBY DISPLAY switch is pressed,
perform troubleshooting procedures.
e.
Read LED Digital Clock Theory of Operation.
A19 Assembly Removal
Prior to removing or reinstalling the LED Digital Clock,
all operating power must be removed. Wire and cable
7-43
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