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Pipeline Interlocks
Data ALU Pipeline Interlocks
6-2
Optimizing DSP56300/DSP56600 Applications
6.1.1
What are the Data ALU Pipeline Interlocks?
There are three types of Data ALU pipeline interlocks:
• Arithmetic Interlock—An arithmetic interlock causes a
single cycle delay in the execution of the MOVE instruction.
It is caused by moving the contents of (or one part of) an
accumulator that was the destination in the preceding
arithmetic instruction.
Example:
mpy
move
Note: The following code sequence does not generate an arithmetic
pipeline interlock:
mpy
mac
• Transfer Interlock—A transfer interlock causes a single cycle
delay in the execution of the second MOVE instruction (the
one that reads the accumulator or one of its parts). It is
caused by moving the contents of an (or parts of)
accumulator that was the destination of the preceding or
second preceding MOVE instruction.
Example:
move
move
• Status Interlock—A status interlock causes a double or
single cycle delay in the execution of the MOVE instruction
that reads SR. It is caused by a MOVE instruction that reads
the contents of the Status Register (SR) immediately or two
instructions after an arithmetic instruction.
Example:
mac
move
Out of these three pipeline interlocks, only the Arithmetic Interlock
may occur more often in a typical application. Transfer Interlock
X0,Y0,A
;Arithmetic Instruction. A is
;destination
A,X:(R0)+
;Move the contents of A to
;memory
X0,Y0,A
;Arithmetic Instruction. A is
;destination
X1,Y1,A
;Add A contents from previous
;instruction with X1
X:(R0)+,A
;Move memory to A
A1,Y0
;Move A1 to register
X1,Y1,B
;Arithmetic Instruction
SR,X:(R0)+
;Read SR by a MOVE instruction
×
Y1
MOTOROLA
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