Panasonic MN103SFX1K Manual page 4

Reset function
Error detection reset
Watchdog timer
Detection time
Function
8-bit timer
Function
16-bit timer
Function
Serial interface 0 and 1
Communication mode
Clock synchronous serial
Full duplex UART
Serial interface 2
Communication mode
Clock synchronous serial
Full duplex UART
Complementary 3-phase PWM timer
Minimum resolution
Function
A/D converter
Resolution
Number of channels
Function
Publication date: April 2018
Error detection by watchdog timer
8.192 ms to 2097.15 ms (At External oscillation is 8 MHz.)
Non-maskable interrupt generates when 1st overflow is detected.
Forced-reset generates in LSI when 2nd overflow is detected.
Interval timer, Timer pulse output, Event count, Baud rate timer, Cascade connection
Interval timer, Event count, Up/Down count, Timer output, PWM output (Cycle varia-
ble, Pulse width variable), Input capture, One-shot output, Start trigger start, Generation
of Start trigger for A/D conversion
Function
Maximum transfer rate
Function
Maximum transfer rate
Function
Maximum transfer rate
Function
Maximum transfer rate
13.9 ns
Triangular wave and saw-tooth wave output, dead time auto-insertion, double buffer up-
date, output protection circuit, output timing variable function
10 bits
Up to 20 channels in 3 units (There is the share channel.)
16-bit timer, A/D conversion start in synchronization with PWM, Multiple channel con-
version, Conversion channel omitted function, Conversion result error detect function
MN103SFX1K/X2K/X3K/X5K/X6K/X7K
Clock synchronous serial/ Full duplex UART
Parity error detection, Overrun error detection, Specifica-
tion of First transfer bit, Selection of any transfer size
from 7 to 8 bits
3.0 Mbps
Parity error detection, Overrun error detection, Framing
error detection, Specification of First transfer bit, Selec-
tion of any transfer size from 7 to 8 bits
375 kbps
Clock synchronous serial/ Full duplex UART
Overrun error detection, Specification of First transfer bit,
Selection of any transfer size from 2 to 8 bits
5.0 Mbps
Parity error detection, Overrun error detection, Framing
error detection, Specification of First transfer bit, Selec-
tion of any transfer size from 7 to 8 bits
300 kbps
32-bit Single-chip Microcontroller
PubNo. 232X701-015E
4