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Renesas TPS-1 User Manual

Renesas TPS-1 User Manual

Hardware. ethernet controller for profinet io devices. renesas assp.
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TPS-1
RENESAS ASSP
Ethernet Controller for PROFINET IO Devices
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.1.07 Jul 2018

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Summary of Contents for Renesas TPS-1

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
  • Page 3 Instructions for the use of product In this section, the precautions are described for over whole of CMOS device. Please refer to this manual about individual precaution. When there is a mention unlike the text of this manual, a mention of the text takes first priority 1.
  • Page 4 The following documents apply to the TPS-1. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Electronics Web site.
  • Page 5 3. List of Abbreviations and Acronyms Abbreviation Full Form Clocked Serial Interface Fiber Optic FPBGA Fine Pitch Ball Grid Array Ground Potential GPIO General Purpose Input /Output Input I/O or IO Input/Output MISO Master in Slave out (SPI signal) MOSI Master out Slave in (SPI signal) Media Redundancy Protocol (IEC 61158) Output...

  • Page 6: Table Of Contents

    VENTS FROM THE HOST TO THE FIRMWARE 4.4. TPS-1 ........................39 NTERRUPT OMMUNICATION WITH THE 4.4.1. How to generate an interrupt by an event ........................39 TPS-1 BOOT SUBSYSTEM ..............................43 5.1........................ 43 ARDWARE TRUCTURE FOR THE PERATION 5.2..............44 OADING AND UPDATE OF THE FIRMWARE DURING THE MANUFACTURING PROCESS 5.2.1.
  • Page 7 CLOCK CIRCUIT .................................. 56 9.1..........................56 SING THE INTERNAL CLOCK OSCILLATOR 9.2............................... 57 XTERNAL CLOCK SOURCE RESET OF THE TPS-1 ..............................58 BOUNDARY SCAN INTERFACE (JTAG) ......................... 59 11.1. JTAG I ......................60 IRCUIT RECOMMENDATION OF THE NTERFACE SETTING OF OPERATING MODES ........................

  • Page 8: Overview

    Two application relations available (from stack version V1.2 onwards) • The TPS-1 firmware allows a up to 64 Slot/Subslots (e.g. 1 Slot with up to 64 Subslots) • Configuration of all host interfaces with software tool; configuration data are stored in a boot Flash Note: A maximum data size of 1016 Byte is possible with stack version 1.4.0.14 or newer.

  • Page 9: Abstract

    PROFINET CPU. Due to the low space requirement and low power dissipation of the TPS-1, a PROFINET interface can also be integrated into automation devices with special requirements regarding housing size and protection classes. Conductor routing between the balls is still possible in order to keep down PCB cost.

  • Page 10: Block Diagram

    Figure 1-2: TPS-1 Block Diagram The TPS-1 contains the PROFINET CPU, the PROFINET core, the I/O interface, and the Host Interface for connecting a host CPU. The PROFINET core processes the PROFINET communication. All time-critical services are implemented in hardware to realize high performance.

  • Page 11: Pin Function

    TPS-1 User’s Manual: Hardware 2. Pin function 2. Pin function 2.1. Signal overview and description Table 2-1 contains an overview about all signals of the TPS-1. Table 2-1: TPS-1 signal overview and description Designation Function Remark SPI Master for Boot Flash ROM...
  • Page 12 TMC2 Test Mode Control 2 (production test) (pull down external recommended) TEST_1_IN Test Pin 1 for hardware test of the TPS-1 (pull down external recommended) TEST_2_IN Test Pin 2 for hardware test of the TPS-1 (pull down external recommended)
  • Page 13 TPS-1 User’s Manual: Hardware 2. Pin function UART6_TX Boot UART “Transmit Data“ UART6_RX Boot UART “Receive Data“ BOOT_1 Forced Boot Test signals for switching regulator TEST1 Test Pin switching regulator (in combination with Test2, Test3) TEST2 Test Pin switching regulator (in combination with...

  • Page 14: Gpio Multiplexing

    LBU BE 1 IN Byte Selection (low) GPIO 4 LBU BE 2 IN Byte Selection (high) GPIO 5 LBU READY OUT Ready Signal TPS-1 (Note 1), (Note 2) GPIO 6 LBU DATA0 Data Bit GPIO 7 LBU DATA1 Data Bit...

  • Page 15: Supply Voltage Circuitry

    2.3. Supply Voltage Circuitry The TPS-1 works with three operating voltages: VDD15 (1.5 V), VDD33 (3.3 V, IO) and VDD10 (1.0 V, core). Additionally, the on-chip PLL for the device clock generation requires a supply called PLL_AVDD (1.0 V), which is typically a filtered version of VDD10. The integrated PHYs of the TPS-1 require additional filtered operating voltages.

  • Page 16: Signals For Irt Communication

    2. Pin function 2.4. Signals for IRT Communication The TPS-1 synchronizes the IO device to the PROFINET controller and generates trigger signals that are used for application synchronization. T_IO_Input relates peripheral inputs and T_IO_Output relates peripheral outputs to the data cycle.

  • Page 17: Host Interface

    3.1. Testing DPRAM Interface For testing the DPRAM Interface it is useful to have addresses with defined values. After start of the TPS-1 firmware the TPS-1 writes the magic number and the NRT Area Size into the addresses 0x8000 and 0x8004.

  • Page 18: Signal Description Of The Parallel Interface

    A(15:0) LBU_SEG(1:0)_IN A(15:14) Figure 3-2: TPS-1 with address page 16 Kbyte You can also choose a page size of 4 Kbyte. When you choose 4 Kbyte pages you have less space inside the NRT area for configuration slots and subslots.
  • Page 19 High Bit of the segment page selection During a memory access, the TPS-1 behaves like a „16-bit Little Endian“ device with an 8-bit or 16-bit memory. The possible access types are listed in Table 3-3. Table 3-3: 16-Bit External Host Databus...

  • Page 20: Memory Segmentation At 4 Kbyte And 16 Kbyte

    TPS-1 User’s Manual: Hardware 3. Host Interface 3.2.3. Memory Segmentation at 4 kByte and 16 kByte page size You decide the page size with the TPS Configurator. A connected Host CPU selected the pages with the LBU_SEGx_IN signals. Table 3-5 shows the page decoding.
  • Page 21 TPS-1 User’s Manual: Hardware 3. Host Interface Using the 4 kByte address pages limits the available address space of the NRT area. Figure 3-5 shows the pages. You can reach the complete Event- Unit and the complete IO-RAM. Out of the NRT area you can only use the address space between 0x8000 and 0x9FFF.

  • Page 22: Connection Example For A 8Bit Data Bus

    TPS-1 User’s Manual: Hardware 3. Host Interface 3.2.4. Connection example for an 8bit data bus Figure 3-6 shows a connection example of an 8-bit data bus to the TPS-1. TPS-1 HOST-CPU LBU_CS_IN INTN INT Port INT_OUT A0 – A15 LBU_A0_IN – LBU_A13_IN A0 –...

  • Page 23: Connection Example For A 16-Bit Data Bus

    3.2.5. Connection example for a 16-bit data bus Figure 3-7 shows the connection of a 16-bit CPU to the TPS-1. The connection uses a 16-bit data bus and an address bus of 16 bit. Thus, it is possible to access the entire address space of 64 KByte. Address line A0 should not be connected using the 16-bit data bus. The Address line LBU_A0_IN should be connected to a pull down.

  • Page 24: Spi Slave Interface

    The clock phase and the CPOL (clock polarity) is adjustable (active low, active high). The following figure shows the connection of a host CPU (V850ES/JG2) to the SPI Slave interface of the TPS-1. The “chip select” line is not connected. The data transfer is controlled by the status of the “clock line” (CSI-Master).

  • Page 25: Serial Access To The Shared Memory

    TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.1. Serial access to the shared memory The access to the shared memory is processed with command bytes that are part of the SPI-Header. The command structure depends on the device. Generally, an SPI interface works like a shift register. The clock is driven by the SPI master. After processing the SPI command, the SPI slave sends the requested data to the host CPU (or data is only sent to the SPI slave).
  • Page 26 TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.1.2. Structure of a command byte Figure 3-9 shows the format of a command byte. A command byte can be followed by an address area, length area and data. Direct IO Length Access Area...
  • Page 27 TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.1.3. Command overview The SPI commands are optimized for the use with PROFINET. The following table describes the implemented commands. Table 3-8: Implemented SPI commands This gives the external host CPU access to the complete address space of 64 Kbyte.

  • Page 28: Spi Slave Interface Timing

    TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.2. SPI Slave Interface Timing The SPI transfer is controlled by the signal HOST_SFRN_IN. A chip select signal is not used. 3.3.2.1. SPI Slave Interface Typical Timing The following figure shows a typical SPI-Slave Timing (Motorola Mode).
  • Page 29 Figure 3-11 (T1, T2 and T3). The timing is based on the system clock of the TPS-1 (100 MHz, 10 ns); it must as well be applied in the situations shown in Figure 3-12, Figure 3-13 and Figure 3-14.
  • Page 30 TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.2.2. SPI Slave Interface Handshake Mode If the header contains a read or exchange command, it is necessary to wait for a short time after transferring the header in order to enable the slave interface to collect the data before transferring.
  • Page 31 TPS-1 User’s Manual: Hardware 3. Host Interface 3.3.2.2.2. SPI Slave Interface Handshake Wait Mode When using the Handshake Wait Mode, the SPI master deactivates the data transfer after the header has been transmitted and starts a wait time. During this time, the SPI Slave can provide the requested data.
  • Page 32 TPS-1 User’s Manual: Hardware 3. Host Interface The time between two complete data transfers is calculated with the following equation: L = ((4 * (T + 10)) – 8 * f ) (L * 1/fsys = break between two cycle);...

  • Page 33: Spi Slave Interface Reset Timing

    3.3.3. SPI Slave Interface Reset Timing Figure 3-14 describes the behavior when a reset for the SPI Slave interface occurs. The communication process is interrupted and after a wait time of 4 system clocks (40 ns for the TPS-1), the next transfer can start. HOST_SCLK_IN...

  • Page 34: Shared Memory Structure

    AlarmMailbox low RecordMailbox AlarmMailbox high Area (32k Byte) AlarmMailbox low RecordMailbox Supervisor AR RecordMailBox Implicit AR TCP/IP Mailbox Slot/Subslot configuration reserved 0xFFFF Figure 4-1: TPS-1 Shared Memory Structure (Dual Ported RAM) R19UH0081ED0107 Rev. 1.07 page 34 of 86 Jul 30, 2018...
  • Page 35 TPS-1 User’s Manual: Hardware 4. Shared memory structure The structure of the configuration written into the NRT area is checked by the TPS-1 firmware. If there are structure errors the TPS-1 firmware does not start. The host interface and the NRT area are accessible in a continuous address space.

  • Page 36: Event Communication With The Tps-1 Firmware

    (32 Bit) Figure 4-3: TPS-1 Event Communication For process changes of the event register the TPS-1 and the host CPU has to poll these registers. You can also use an interrupt control mode if the host CPU supports this. The event bits corresponding to the mail box access are not ambiguous. After receiving this event it is necessary to check each mail box. In the header of the respective mail box, the READ_FLAG is set.

  • Page 37: Events From The Tps-1 Firmware To The Host

    TPS-1 User’s Manual: Hardware 4. Shared memory structure 4.2. Events from the TPS-1 firmware to the host Table 4-1: TPS-1 Firmware Events Name Description TPS_Event_Bits (Firmware Stack -> Host) TPS_EVENT_ONCONNECTDONE_AR0 Set when a connection for IOAR0 is established. TPS_EVENT_ONCONNECTDONE_AR1 Set when a connection for IOAR1 is established.

  • Page 38: Events From The Host To The Tps-1 Firmware

    Host CPU forces a software reset of the TPS-1 APP_EVENT_APP_MESSAGE The application filled the Ethernet mailbox with a record request for the TPS Communication Interface. The TPS-1 will read the request and send a response to the application. R19UH0081ED0107 Rev. 1.07...

  • Page 39: Nterrupt Ommunication With The Tps-1

    4. Shared memory structure 4.4. Interrupt Communication with the TPS-1 The communication between the TPS-1 and the Host CPU is processed by the Event-Unit. If you want to use the interrupt control, you need the registers shown in Table 4-3.
  • Page 40 TPS-1 User’s Manual: Hardware 4. Shared memory structure Table 4-5: Register PN_Event_high Name PN_Event_high Address 0x0040 Access r/ w Bits Type of Event Description Init: 31:00 Event-Bit high active events 0X00000000 (Stack Events) Bit 0: TPS_EVENT_ONCONNECTDONE_IOAR0 Bit 1: TPS_EVENT_ONCONNECTDONE_IOAR1 Bit 2: TPS_EVENT_ONCONNECTDONE_IOSAR...
  • Page 41 TPS-1 User’s Manual: Hardware 4. Shared memory structure One or more bits written in to these registers (*_low and *_high) process an external interrupt event (INT_OUT). A new one will influence no bits set before. Table 4-6: Register Host_IRQmask_low Name...
  • Page 42 TPS-1 User’s Manual: Hardware 4. Shared memory structure You can verify the interrupt event sources by reading the Host_IRQ_low and Host_IRQ_high register. Each bit corresponds with a masked event. A bit set to “1” shows a masked bit. Table 4-10: Register Host_IRQ_low...

  • Page 43: Tps-1 Boot Subsystem

    5.1. Hardware Structure for the Boot Operation The TPS-1 uses a boot loader which reads all necessary data from the boot Flash and carries out the necessary settings. The boot loader is integrated into the ASIC and cannot be changed.

  • Page 44: Loading And Update Of The Firmware During The Manufacturing Process

    Flash is soldered. It allows to do all required setting via ETHERNET. 5.2.1. UART interface (UART boot) The UART interface is used for basic communication with the TPS-1. The interface is reduced to a minimum and has no modem lines. Table 5-1: Boot UART lines...

  • Page 45: Spi Master Interface (Boot Flash)

    5.2.2. SPI master interface (Boot Flash) The TPS-1 has one SPI master interface for connecting a serial Flash device. The Flash contains the TPS-1 firmware as well as the device configuration and the three required MAC addresses. The operation of this interface is managed by the boot loader.
  • Page 46 TPS-1 User’s Manual: Hardware 5. TPS-1 boot subsystem 5.2.2.1. SPI Command Set A SPI memory device must support the following commands. Writing to the flash requires the command Sector Erase (SE). It must be possible to write sectors with a size of 4 Kbyte.

  • Page 47: Io Local Gpio Interface

    6. IO Local GPIO Interface 6. IO Local GPIO Interface For the development of small IO-Devices the TPS-1 offers the IO Parallel Interface with a maximum of 48 IO lines. These lines could be used for input, output and diagnostic purposes.

  • Page 48: Status Leds Of Thetps-1

    TPS-1 User’s Manual: Hardware 6. IO Local GPIO Interface 6.2. Status LEDs of theTPS-1 The TPS-1 uses 4 GPIOs to indicate the device status. These GPIOs can be connected directly to LEDs to display the status. Table 6-1: Status LEDs PROFINET LED:...

  • Page 49: Tps-1 Watchdog

    Figure 7-1: TPS-1 Watchdog Lines 7.1. Signal WD_OUT (pin B12) The WD_OUT signal is processed by the TPS-1. The TPS-1 starts its watchdog during start up (the signal is set to high level during power up). This is done by the TPS-1 firmware The signal WD_OUT indicates that a watchdog error occurs inside the TPS-1.

  • Page 50: Signal Wd_In (Pin A11)

    7. TPS-1 Watchdog 7.2. Signal WD_IN (pin A11) The signal WD_IN is implemented as a watchdog trigger. When recognizing the host watchdog event, the TPS-1 generates a diagnostic alarm and sets the IOPS of the input data to the BAD state.

  • Page 51: Profinet Io Switch

    8. PROFINET IO switch 8. PROFINET IO switch The TPS-1 contains a PROFINET switch with 2 external ports. Thus, PNIO devices can be connected directly to each other without the need for external switching devices (line topology). Figure 8-1: Network topologies with the TPS-1 All necessary PROFINET protocols are implemented (LLDP, PTCP, MRP, etc.).

  • Page 52: 100Base-Tx Interface

    For this interface, typically RJ45 plugs are used. However, it is recommended to use special connectors here that are suitable for industrial requirements. The interface hardware of the TPS-1 can be connected directly to the Ethernet transformer. The standard 100Base-TX requires CAT5 cables.

  • Page 53: 100Base-Fx Interface (Port 1)

    P2_TD_OUT_N Transmit signal (Difference -) 8.3. I2C-Bus – LWC Diagnostic The TPS-1 provides two “I C Interface Lines” for fiber optics diagnostic purposes. The recommended AVAGO transceiver (AFBR-5978Z) features internal registers that can be read by the I C interface. The transceiver can deliver diagnostic information via the I C interface.

  • Page 54: Additional Tps-1 Pins

    It is also possible to feed the TPS-1 with an external voltage of 1.5 V. Then you have to switch off the regulator (Pin TEST1 set to 1 with a pull-up). The regulator output (Pin LX) changes to HiZ status.
  • Page 55 Figure 8-2: Internal voltage regulator The time of power-supply rise to the point where all power supplies are stabilized must be reached within 100 ms. The typical behavior of the power supplies is shown in Figure 8-3: TPS-1 Power-up sequence. 3.3V 3.0V...

  • Page 56: Clock Circuit

    Figure 9-1: Wiring of the TPS-1 clock The recommended circuitry (Figure 9-1: Wiring of the TPS-1 clock) is based on the Seiko Epson TSX-3225 Crystal Unit. It is recommended to use this crystal and circuitry recommendation (using Seiko Epson crystal). In any case it is the customer’s responsibility to verify, whether crystal, circuitry and layout fulfill the requirements.

  • Page 57: External Clock Source

    Place the input and output pins of the oscillator and the resistor and external component close to each other, and keep wiring as short as possible. • Make the wiring between the ground side of the capacitor and the ground pin of the TPS-1 as short and as thick as possible. •...

  • Page 58: Reset Of The Tps-1

    An external reset is caused by a “low” level at the signal pin RESETN. This condition is held until the “low” level changes to a “high” level. During startup of the power supply the 3.3 V voltage is controlled by the TPS-1 (internal). The 1.5 V voltage (if fed from external) and the 1.0 V voltage must be controlled by an external circuitry.

  • Page 59: Boundary Scan Interface (Jtag)

    (4K7 Ω to V Test Data Output Test Clock JTAG clock signal to the TPS-1. It is recommended that this pin be set to a defined state on the target board. External pull-up (4K7 Ω to V Test Data Input External pull-up (4K7 Ω...

  • Page 60: Circuit Recommendation Of The Jtag Interface

    11.1. Circuit recommendation of the JTAG Interface If the JTAG interface is unused in the customer application the TRSTN input of the TPS-1 should be connected to digital GND via a 4.7kΩ resistor. The circuit recommendation for the interface looks as follows.

  • Page 61: Setting Of Operating Modes

    Setting of operating modes The basic configuration of the TPS-1 is managed with the “TPS Configurator” software. You can set the configuration of the host interface (serial, parallel) or the configuration of the Local IO Interface. There you can choose the IO interface (serial or parallel digital outputs).

  • Page 62: Host Interface

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes Host Interface The host interface realizes the connection of external host CPUs. Data exchange is carried out via an internal Shared Memory area. Depending on the type of external host CPU, you can choose a serial (SPI slave) or a parallel interface.

  • Page 63: Host Serial Interface

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes Host Serial Interface The serial host interface is an SPI-Slave interface. The necessary hardware settings are available on TAB ”Host Serial Settings”. The watchdog function for the host CPU is configured below the headline ”General Settings“. You can choose watchdog time and activity level.

  • Page 64: Local I/O-Configuration

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes Local I/O-Configuration These settings control the 48 GPIOs and the SPI master interface. GPIOs can be set individually or in groups. Single or groups of GPIOs can be configured to work as inputs or outputs. On the tab “Channel” you can configure some GPIOs for diagnostic functions (PROFINET ChannelDiagList).
  • Page 65 TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes If you need diagnosis channel on the Local IO Parallel interface, you can configure a maximum of 16 pins (see Tab IO General Settings). The special behavior can be configured inside the Tab Diag Channel.
  • Page 66 TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes To configure the GPIO’s you must refer to the part IO Parallel Settings. Figure A-6: IO Parallel Settings configuration part 2 R19UH0081ED0107 Rev. 1.07 page 66 of 86 Jul 30, 2018...

  • Page 67: Io Serial Interface

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes IO Serial Interface You can choose the IO Serial mode. This enables the SPI-Master interface of the TPS IO Local Mode Figure A-7: IO Serial Mode - SPI Master R19UH0081ED0107 Rev. 1.07...
  • Page 68 TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes The communication parameter of the SPI Master interface must be set in the following Tab “IO Serial Settings” Figure A-8: IO Serial Settings of the SPI Master Interface R19UH0081ED0107 Rev. 1.07...

  • Page 69: Io Local Interface

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes IO Local Interface For the development of small IO-Devices the TPS-1 offers the IO Parallel and IO Serial Interface. This interface can be used without an external Host CPU. IO Local parallel Interface There are some restrictions when using the IO Local Parallel interface.

  • Page 70: Configuration Of The Io Local Serial Interface (Spi Master)

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes Configuration of the IO Local Serial interface (SPI Master) The TPS Configurator supports in addition a SPI Master interface to connect another SPI Slave controller (e.g. connecting special IO devices or if you need more than 48 GPIO).

  • Page 71: I&M0 Configuration (I&M0 Data) "Deleted" Ok

    TPS-1 User’s Manual: Hardware Appendix. A Setting of operating modes I&M0 Configuration (I&M0 data) The provision of these parameter values is mandatory for every PROFINET device (I&M0 profile). Table A-1: I&M0 Parameter Parameter Description VENDOR ID The parameter VENDOR_ID carries the ID of the respective device manufacturer. It is assigned by PI.

  • Page 72: Ethernet Interface Configuration

    Figure A-11: Ethernet Interface Configuration The TPS-1 needs three MAC addresses to operate. One is used for the TPS-1 itself; additionally, each of the two ports has an individual MAC address as well in order to support port-based communication services for e.g. LLDP.

  • Page 73: Copying The Configuration Data Into The Boot Flash

    Flash device with a special program (FS_Prog.exe). The TPS Configurator can generate a command with all the parameters (see “Generate Command”). Figure A-12: Writing the TPS-1 configuration By clicking “Send Configuration”, the transfer of the configuration data to the PROPINET IO device is started.

  • Page 74: Generating A Complete Serial Boot Flash Image

    The configuration data is then copied to the TPS-1 and stored into the serial boot Flash device (Factory Settings Block). On the TPS-1 special software is running that enables you to copy a firmware image into the serial boot Flash device. The firmware block can be copied from every directory on your PC.

  • Page 75: Board Design Information

    Voltage supply The TPS-1 requires 3 supply voltages. The necessary supply voltages can be delivered directly from the power supply unit. In this case, the switching regulator is not needed (refer Chapter8.5). You can also use the integrated voltage regulator that is fed with 3.3 V. The recommended circuitry described in AppendixB.2...

  • Page 76: Wiring For The Switching Regulator

    Figure B-1 shows the wiring for the external regulator circuit if the regulator is used to generate the 1.5 V for the PHYs. Notes: • All components should be placed as close as possible to the TPS-1. • Important: The characteristic of C1 is mandatory. A lower ESR will cause problems with the regulator oscillation.

  • Page 77: Layout Example For Switching Regulator

    TPS-1 User’s Manual: Hardware Appendix. B Board Design Information R1a* C1a* Figure B-2: Change Tantalum to Ceramic Capacitor Layout Example for Switching Regulator This chapter shows an example for the connection between the external output and regulator. The real design of the layout must be done on the PCB board.

  • Page 78: Board Design Recommendations For Ethernet Phy

    Appendix. B Board Design Information Board Design Recommendations for Ethernet PHY Supply Voltage Circuitry The on-chip PHYs of the TPS-1 require additional filtered operating voltages as shown in the table below. Table B- 2: Supply Voltages Circuitry for Ethernet PHY Pin Name...
  • Page 79 TPS-1 User’s Manual: Hardware Appendix. B Board Design Information Figure B-5 illustrates the power supply pins and their recommended connection. Digital supply and digital ground is not shown. PHY Supply Voltages 3.3V VDD33ESD – E12 filter circuit VDDACB – H14 VDDQ_PECL_B1 –...

  • Page 80: 100Base-Tx Mode Circuitry

    100 Ω impedance and the trace length must be kept as short as possible. The EXTRES input must be connected to analog GND with a 12.4 kΩ resistor (1% tolerance). See “Additional TPS-1 Pins”.

  • Page 81: Unused 100Base-Tx Interface

    TPS-1 User’s Manual: Hardware Appendix. B Board Design Information Unused 100Base-TX Interface In applications that do not use the 100BASE-TX mode, but only the 100BASE-FX mode, the analog I/Os should be left open. Only EXTRES must still be connected with the 12.4 kΩ resistor to analog GND.

  • Page 82: 100Base-Fx Mode Circuitry

    TPS-1 User’s Manual: Hardware Appendix. B Board Design Information 100BASE-FX Mode Circuitry In case of 100BASE-FX operation, a PN-IO compliant optical transceiver module like Avago AFBR-5978Z or QFBR-5978Z is connected to the FX interface. The signals between the PHY and the transceiver module are 100 Ω differential respectively 50 Ω single-ended signals.
  • Page 83 Appendix. B Board Design Information The circuitry for the connection of the SD-Pin of the transceiver to the SD_P/SD_N Pin of the TPS-1 is shown in Figure B-9. The active circuitry is necessary because the QFBR/AFBR transceiver provides no differential signal.
  • Page 84 TPS-1 User’s Manual: Hardware Appendix. B Board Design Information Figure B-10: Power Supply for AVAGO Transceiver It is further recommended that a contiguous ground plane is provided in the device board directly under the transceiver to provide a low inductance ground for signal return current.

  • Page 85: Unused 100Base-Fx Interface

    TPS-1 User’s Manual: Hardware Appendix. B Board Design Information Unused 100Base-FX interface Figure B-11 shows the wiring of an unused „Fiber Optic Transceiver“. The interface uses PECL lines. If a 100Base-FX interface is not used, the pins Px_TD_OUT_P and Px_TD_OUT_N can remain open (no Pull-Up or Pull-Down resistor necessary).

  • Page 86: Fast Start Up Requirements

    The property prioritized startup demanded a startup time less than 500 ms. If you want to realize this feature be aware that the complete device (TPS-1 and you own Application) must come up to this time requirement. The function Autonegotiation is disabled and the system operates with a fixed transmission rate. To avoid the usage of crossover cables the Port 2 must...
  • Page 87 Chapter 3.3. , Table 3-3 : changed - LBU_BE(x)_IN Chapter 3.2.2.1. , figure 3-9 : changed - HOST_SCLK_IN Chapter 3.2.2.2.2 : added - the equitation for calculating the wait- and latency-time for the TPS-1 SPI Wait Mode Chapter 4. , Figure 4-1 : changed Chapter 5.2.2.
  • Page 88 Rev. Date Description Page Summary 1.06 Jan 31, 2018 Chapter 1.1 : Changed - Number of application relations ( From one to two ) HOST_SFRN_IN Chapter 2.2. : Added - Note 3) for in Table 2-2 Chapter 3.3.2 : Added - Description about HOST_SFRN_IN Chapter 4.2.
  • Page 89 TPS-1 User’s Manual: Hardware Publication Date: Rev.1.00 Sep 20, 2012 Rev.1.07 Jul 30, 2018 Published by: Renesas Electronics Corporation...
  • Page 90 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3...
  • Page 91 TPS-1 R19UH0081ED0107...

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