Renesas RL78/G1H User Manual page 867

RL78/G1H
Instruction
Mnemonic
Group
Multiply, MULU
Divide,
MULHU
Multiply &
MULH
accumulate
DIVHU
DIVWU
MACHU
MACH
Note 1. Number of CPU clocks (f
data is accessed.
Note 2. Number of CPU clocks (f
an 8-bit instruction.
Remark 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Remark 2. MACR indicates the multiplication and accumulation register (MACRH, MACRL).
R01UH0575EJ0120 Rev. 1.20
Dec 22, 2016
Table 30 - 16 Operation List (12/18)
Operands Bytes
X 1
3
3
3
3
3
3
) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
CLK
) when the code flash memory is accessed, or when the data flash memory is accessed by
CLK
Clocks
Note 1 Note 2
1 — AX ← A × X
2 — BCAX ← AX × BC (unsigned)
2 — BCAX ← AX × BC (signed)
AX (quotient), DE (remainder) ←
9 —
AX ÷ DE (unsigned)
BCAX (quotient), HLDE (remainder) ←
17 —
BCAX ÷ HLDE (unsigned)
3 — MACR ← MACR + AX × BC (unsigned)
MACR ← MACR + AX × BC(signed)
3 —
CHAPTER 30 INSTRUCTION SET
Clocks
Z
Page 849 of 920
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