SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory
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SmartFusion2 SoC FPGA - Error Detection
and Correction of eSRAM Memory
2.1
Introduction
This document describes the error detection and correction (EDAC) capabilities of the SmartFusion
devices on the embedded static random access memory (eSRAM).
The EDAC controllers implemented in the SmartFusion2 devices support single-error correction and
double-error detection (SECDED). All memories within the microcontroller subsystem (MSS) of the
SmartFusion2 are protected by SECDED. The eSRAM memory can be eSRAM_0 or eSRAM_1. The
address range of eSRAM_0 is 0x20000000 to 0x20007FFF and the address range of eSRAM_1 is
0x20008000 to 0x2000FFFF.
When SECDED is enabled:
•
A write operation computes and adds 8 bits of SECDED code to every 32 bits of data
•
A read operation reads and checks the data against the stored SECDED code to support 1-bit error
correction and 2-bit error detection
In this demo, the EDAC can be identified by the blinking light-emitting diode (LED) on the board and by
graphical user interface (GUI).
Figure 1 •
Top-Level Block Diagram
LED
The EDAC of eSRAM supports the following features:
1.
SECDED mechanism
2.
Provides interrupts to the ARM Cortex- M3 processor and FPGA fabric upon the detection of a
1-bit error or 2-bit error.
3.
Stores the number of 1-bit and 2-bit errors to the error counter registers.
4.
Stores the address of the last 1-bit or 2-bit error affected memory location.
5.
Stores 1-bit or 2-bit error data into the SECDED registers.
6.
Provides error bus signals to the FPGA fabric.
Refer to the EDAC chapter of the
User Guide
and the eSRAM chapter of the
Guide.
SmartFusion2
GPIO
EDAC
Controller Logic
eSRAM
UG0443: SmartFusion2 and IGLOO2 FPGA Security and Reliability
DG0388 Demo Guide Revision 10.0
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UG0331: SmartFusion2 Microcontroller Subsystem User
®
Graphical User
Interface
Running on Host PC
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