Page 1 FUJITSU SEMICONDUCTOR CM44-10121-5E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90480/485 Series HARDWARE MANUAL...
Page 3 Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Page 5 PREFACE ■ Purpose of This Manual and Intended Readers Thank you very much for purchasing FUJITSU products. MB90480/485 series is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90480/485 series functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VTRs.
Page 6 ■ Composition of This Manual This manual consists of the following 27 chapters and an appendix. CHAPTER 1 "OVERVIEW OF MB90480/485 SERIES" This chapter explains the features, block diagram, and functions to give basic specifications about the MB90480/485 series. CHAPTER 2 "CPU" This chapter provides basic information on the architecture, specifications, and instructions to help the reader understand the functions of the MB90480/485 series CPU core.
Page 7 CHAPTER 14 "16-BIT RELOAD TIMER" This chapter gives an overview of the 16-bit reload timer and explains the register configuration and functions and the 16-bit reload timer operation. CHAPTER 15 "8/16-BIT PPG TIMER" This chapter gives an overview of the 8/16-bit PPG timer and explains the register configuration and functions and the 8/16-bit PPG timer operation.
Page 8 CHAPTER 27 "I C INTERFACE" (only for MB90485 series) This chapter gives an overview of the I C interface and explains the register configuration and functions and the operation of the I C interface. APPENDIX The appendix gives information about the following parts: the I/O map, interrupt vectors, and list of instructions.
Page 9 Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information.
Page 11: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ............1 Features of MB90480/485 Series ......................2 Block Diagram of MB90480/485 Series ....................6 Package Dimensions ..........................7 Pin Assignment ............................9 Pin Functions ............................11 I/O Circuit Type ............................ 18 Handling the Device ..........................21 CHAPTER 2 CPU ......................
Page 12 3.7.5 Processing Time of the Extended Intelligent I/O Service (EI OS) ..........87 Exception Processing Interrupt ......................89 Stack Operation of Interrupt Processing ..................... 90 3.10 Sample Program of Interrupt Processing .................... 92 3.11 Delay Interrupt Generation Module ..................... 93 3.11.1 Operation of Delay Interrupt Generation Module ................
Page 13 7.5.3 Hold function ..........................174 CHAPTER 8 I/O PORT ....................177 Functions of I/O Port .......................... 178 Registers for I/O Port ......................... 179 8.2.1 Port registers (PDR0 to PDRA) ....................180 8.2.2 Port direction registers (DDR0 to DDRA) ..................181 8.2.3 Other registers ..........................
Page 14 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ........... 259 13.1 Overview of 8/16-bit Up/Down Counter Timer .................. 260 13.2 Configuration of 8/16-bit Up/Down Counter/Timer ................261 13.3 Configuration and Functions of Registers for 8/16-bit Up/Down Counter/Timer ....... 264 13.3.1 Counter control register (ch.0) upper (CCRH0) ................265 13.3.2 Counter control register (ch.1) upper (CCRH1) ................
Page 15 CHAPTER 17 8/10-BIT A/D CONVERTER ..............355 17.1 Overview of 8/10-Bit A/D Converter ....................356 17.2 Configuration of 8/10-Bit A/D Converter .................... 357 17.3 Configuration and Functions of 8/10-Bit A/D Converter Registers ............ 359 17.3.1 Control Status Register 1 (ADCS1) ....................360 17.3.2 Control Status Register 2 (ADCS2) ....................
Page 16 CHAPTER 20 CHIP SELECTION FACILITY ..............445 20.1 Overview of Chip Selection Facility ....................446 20.2 Configuration of Chip Selection Facility .................... 447 20.3 Configuration and Functions of Chip Selection Facility Registers ............ 449 20.3.1 Chip Select Area MASK Register (CMRx) ................... 450 20.3.2 Chip Selection Area Register (CARx) ..................
Page 17 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING CONNECTION ..........505 24.1 Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/ MB90F489B............................506 24.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply) ....... 510 24.3 Example of Minimum Connection with Flash Microcontroller Programmer (When Using the User Power Supply) ....................
Page 18 APPENDIX .......................... 577 APPENDIX A Memory Map ........................578 APPENDIX B I/O Map ..........................581 APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register ........589 APPENDIX D Instructions ........................... 591 Instruction Types ..........................592 Addressing ............................. 593 Direct Addressing ........................... 595 Indirect Addressing .........................
Page 19 → On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.) Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers is changed.
Page 20 Page Changes (For details, refer to main body.) Table 6.7-1 Pin states in single chip mode is changed. (*3: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. → *2: In the state of "Input cutoff", input A is masked and "L"...
Page 21 Page Changes (For details, refer to main body.) ■ Setting method other than program example is changed. (● Method to enable interrupt is added.) ■ Interrupt/DTP enable register (ENIR: Enable interrupt request register) is changed. (Note: is added.) ■ Interrupt/DTP source register (EIRR: External interrupt request register) in 16.2 Configuration and Func- tions of DTP/External Interrupt Unit Registers is changed.
Page 22 Page Changes (For details, refer to main body.) ❍ Clock setting in synchronous transfer is added 438 to 444 The whole description across 19.7 Program Example of UART is changed. The figure of bit configuration in ■ Chip selection control register (CSCR) is changed. (* : The initial value of this bit is "1"...
Page 23: Chapter 1 Overview Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES This chapter gives an overview of MB90480/485 series, including its basic features and basic specifications. 1.1 Features of MB90480/485 Series 1.2 Block Diagram of MB90480/485 Series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 I/O Circuit Type 1.7 Handling the Device...
Page 24: Features Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Features of MB90480/485 Series MB90480/485 series is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. ■ MB90480/485 series features The MB90480/485 series has the following features: ❍ Minimum instruction execution time 40.0 ns/6.25 MHz oscillation multiplied by 4 (25 MHz/3.3 V ±...
Page 25 2 channels of the 3 channels have the function of input compare. ❍ μPG: 1 channel (only for MB90485 series) *: I C license Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Rights to use, these components in an I C system provided that the system conforms to the I Standard Specification as defined by Philips.
Page 26 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ■ Product configuration Table 1.1-1 is an outline of the MB90480 series product configuration and Table 1.1-2 is an outline of the MB90485 series product configuration. Table 1.1-1 MB90480 series product configuration MB90V480B MB90F481B...
Page 27 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES ■ Package of corresponding products ❍ Package Differences among packages are shown below. Table 1.1-3 MB90480/485 series package and correspondence of product Product MB90487B/488B MB90F481B/F482B MB90V480B Package MB90483B MB90F488B/F489B MB90V485B ❍ ❍ ✕ FPT-100P-M06 ❍...
Page 28: Block Diagram Of Mb90480/485 Series
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Block Diagram of MB90480/485 Series This section has a block diagram of the MB90480/485 series. ■ Block diagram of MB90480/485 series Figure 1.2-1 is a block diagram of the MB90480/485 series. Figure 1.2-1 Block diagram of MB90480/485 Series X0, X1, RST Clock control X0A, X1A...
Page 29: Package Dimensions
.059 –0.10 –.004 INDEX (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50±0.20 0.25(.010) (.020±.008) 0.60±0.15 (.024±.006) 0.50(.020) 0.20±0.05 0.145±0.055 0.08(.003) (.008±.002) (.0057±.0022) Dimensions in mm (inches). Note: The values in parentheses are ref erence values. 2003 FUJITSU LIMITED F100007S-c-4-6...
Page 30 –0.20 +.014 .118 –.008 (Mounting height) 0~8 ° 0.65(.026) 0.32±0.05 0.17±0.06 0.13(.005) (.013±.002) (.007±.002) 0.25±0.20 0.80±0.20 "A" (.010±.008) (.031±.008) (Stand off) 0.88±0.15 (.035±.006) Dimensions in mm (inches). 2002 FUJITSU LIMITED F100008S-c-5-5 Note: The values in parentheses are ref erence values.
Page 31: Pin Assignment
Figure 1.4-1 is a pin assignment diagram for the QFP-100 type. Figure 1.4-1 Pin assignment diagram of MB90480/485 series (QFP-100) (FPT-100P-M06) MB90480 series only • I C pin P77 and P76 are N-ch open drain pin (without P-ch). However, MB90V485B uses the N-ch open drain pin (with P-ch) .
Page 32 Figure 1.4-2 is a pin assignment diagram for the LQFP-100 type. Figure 1.4-2 Pin assignment diagram of MB90480/485 series (LQFP-100) (FPT-100P-M05) MB90480 series only • I C pin P77 and P76 are N-ch open drain pin (without P-ch). However, MB90V485B uses the N-ch open drain pin (with P-ch) .
Page 33: Pin Functions
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Pin Functions This section explains the pin functions of the MB90480/485 series. ■ Pin functions Table 1.5-1 explains the pin functions of MB90480/485 series. Table 1.5-1 Pin functions (1/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P-...
Page 34 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (2/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- General-purpose input/output port. Functions as the general-purpose input/output port in the P20 to P23 external bus mode if the bit corresponding to external address output control register (HACR) is set to "1".
Page 35 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (3/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- General-purpose input/output port Functions as an external address pin in the non-multiplex mode. (CMOS/H) ZIN1 8/16-bit up-down timer input pin (channel 1) General-purpose input/output port P36, P37 MB90480...
Page 36 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (4/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- P46, P47 General-purpose input/output port A14, A15 F(CMOS) Functions as an external address pin in the non-multiplex mode. OUT4, OUT5 Functions as the output pin for output compare events. General-purpose input/output port.
Page 37 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (5/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- General-purpose input/output port. Functions as the CLK pin in the external bus mode if the CKE bit of the EPCR register is set to "1".
Page 38 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (6/7) Pin number Pin name Circuit Function FPT-100P- FPT-100P- P80, P81 General-purpose input/output port (CMOS/H) IRQ0, IRQ1 Functions as the external interrupt input pin. P82 to P87 General-purpose input/output port (CMOS/H) IRQ2 to IRQ7 Functions as the external interrupt input pin.
Page 39 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.5-1 Pin functions (7/7) Pin number Pin name Function Circuit FPT-100P- FPT-100P- MD0 to MD2 Input pin name to specify the operation mode. (CMOS/H) ± Power supply pin (V 3) of 3.3V 0.3V Power supply pin for 3.3V (its tolerance is MB90480 -0.3V to +0.3V)
Page 40: I/O Circuit Type
CHAPTER 1 OVERVIEW OF MB90480/485 SERIES I/O Circuit Type This section explains the I/O circuit type of MB90480/485 series pins. ■ I/O circuit type Table 1.6-1 summarizes the I/O circuit type of MB90480/485 series pins. Table 1.6-1 I/O circuit type (1/3) Class Circuit Description...
Page 41 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.6-1 I/O circuit type (2/3) Class Circuit Description • CMOS level input/output CMOS • Hysteresis input • CMOS level output CMOS • CMOS level input/output • Use of open-drain control Open-drain control signal CMOS •...
Page 42 CHAPTER 1 OVERVIEW OF MB90480/485 SERIES Table 1.6-1 I/O circuit type (3/3) Class Circuit Description • CMOS level input/output • Analog input CMOS Analog input • Hysteresis input • N-ch open drain output Digital output Hysteresis input (Flash product) • CMOS level input (Flash product) •...
Page 43: Handling The Device
As much as possible, the power supply source must be connected with V of this device at the lowest impedance. Fujitsu recommends placing a bypass condenser of 0.1 μF between V and V ❍ Crystal oscillation circuit Noise around the X0/X1 or X0A/X1A pins may cause an error during operation on this device.
Page 44 On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
Page 45: Chapter 2 Cpu
CHAPTER 2 This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90480/485 series functions. 2.1 Overview of CPU Specifications 2.2 Memory Space 2.3 CPU Registers 2.4 Prefix Codes...
Page 46: Overview Of Cpu Specifications
CHAPTER 2 CPU Overview of CPU Specifications This section gives an overview of the CPU specifications. ■ Overview of the CPU specifications The F MC-16LX CPU core is a 16-bit CPU designed for devices such as consumer devices that requires high-speed real-time processing. The F MC-16LX instruction set is designed for controller applications, providing high-speed and high-efficiency control processes.
Page 47: Memory Space
CHAPTER 2 CPU Memory Space The F MC-16LX CPU has a 16M bytes memory space, to which all input to and output from the F MC-16LX CPU controlled data program is allocated. CPU has a 24-bit address bus to access each resource. ■...
Page 48 CHAPTER 2 CPU ❍ Linear addressing (indirectly specified using 32-bit register) Figure 2.2-3 shows an example of linear addressing scheme indirectly specified using a 32-bit register. Figure 2.2-3 Linear addressing (indirectly specified using 32-bit register) MOV A, @RL1+7 090700 XXXX Old AL 240906F9 (Upper 8 bits are ignored)
Page 49 CHAPTER 2 CPU Table 2.2-1 Default Space Default space Addressing mode Program space PC indirect, program access, branch instruction Data space Addressing mode using @RW0, @RW1, @RW4, and @RW5; @A; addr16; dir Stack space Addressing mode using PUCHW, POPW, @RW3, and @RW7 Additional space Addressing mode using @RW2 and @RW6 Figure 2.2-4 shows an example of a memory space divided for a register bank.
Page 50 CHAPTER 2 CPU ■ Allocation for data of multi-byte length in memory space Figure 2.2-5 shows the configuration of data of a multi-byte length in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.2-5 Example for allocating data of multi-byte length in memory 1100110 11111111...
Page 51: Cpu Registers
CHAPTER 2 CPU CPU Registers The F MC-16LX registers are divided into special registers inside CPU and general- purpose registers on memory. The former is dedicated hardware inside the CPU, and its use is limited because of the CPU architecture. The latter shares CPU address spaces with RAM.
Page 52 CHAPTER 2 CPU ■ General-purpose register The F MC-16LX general-purpose register resides on the main memory addresses: 000180 00037F (maximum configuration). It uses a register bank register (RP) to indicate which part of addresses are currently used for register banks. Each bank has the three types of registers listed below.
Page 53: Accumulator (A)
CHAPTER 2 CPU 2.3.1 Accumulator (A) This section explains the accumulator (A) functions. ■ Accumulator (A) An accumulator (A) consists of two 16-bit arithmetic operation registers (AH/AL) that are used to store operation results and temporarily store data transfer results. For 32-bit data processing, AH is connected with AL.
Page 54: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) This section explains the functions of the user stack pointer (USP) and system stack pointer (SSP). ■ User stack pointer (USP) and system stack pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers indicating the push/pop instruction or the memory address to which data is saved or restored at subroutine execution.
Page 55: Processor Status (Ps)
CHAPTER 2 CPU 2.3.3 Processor Status (PS) This section explains the processor status (PS) functions. ■ Processor status (PS) Processor status (PS) consists of bits used to execute CPU operations and bits indicating the CPU state. As shown in Figure 2.3-6, the upper byte in the PS register consists of a register bank pointer (RP) and interrupt level mask register (ILM).
Page 56 CHAPTER 2 CPU ❍ Z: Zero flag If all operation results indicate "0", the Z-flag is set. Otherwise, it is cleared. ❍ V: Overflow flag If an overflow with a signed figure occurs as an operation execution result, the V-flag is set. Otherwise, it is cleared.
Page 57 CHAPTER 2 CPU Table 2.3-1 Level indicated by interrupt level mask register (ILM) ILM2 ILM1 ILM0 Level value Permitted interrupt level Interrupt prohibited "0" only Level value less than 1 Level value less than 2 Level value less than 3 Level value less than 4 Level value less than 5 Level value less than 6...
Page 58: Program Counter (Pc)
CHAPTER 2 CPU 2.3.4 Program Counter (PC) This section explains the program counter (PC) functions. ■ Program counter (PC) PC is a 16-bit counter indicating the lower 16 bits in the memory address of an instruction code to be executed by CPU. An upper 8-bit address is indicated with the program count bank register (PCB).
Page 59: Program Counter Bank Register (Pcb)
CHAPTER 2 CPU 2.3.5 Program Counter Bank Register (PCB) This section explains the program counter bank register (PCB) functions. ■ Program counter bank register (PCB) <Initial value: value in reset vector> The program counter bank register (PCB) consists of the following registers: •...
Page 60: Direct Page Register (Dpr)
CHAPTER 2 CPU 2.3.6 Direct Page Register (DPR) This section explains the direct page register (DPR) functions. ■ Direct page register (DPR) <Initial value: 01 > The direct page register (DPR) specifies, as shown in Figure 2.3-11, addresses 8 to 15 of an instruction operand in the direct addressing mode.
Page 61: General-Purpose Register (Register Bank)
CHAPTER 2 CPU 2.3.7 General-Purpose Register (Register Bank) This section explains the general-purpose register (register bank) functions. ■ General-purpose register (register bank) A register bank consists of 8 words and is used as a general-purpose register for arithmetic operation in the byte register (R0 to R7), word register (RW0 to RW7), and long-word register (RL0 to RL3).
Page 62: Prefix Codes
CHAPTER 2 CPU Prefix Codes By inserting a prefix code before an instruction, part of an instruction operation may change. Three types of prefix codes are provided: bank select prefixes, common register bank prefixes, and flag change suppress prefixes. ■ Bank select prefix (PCB, DTB, ADB, SPB) Memory space used in data access is determined according to the addressing mode.
Page 63 CHAPTER 2 CPU ❍ RETI SSB is used regardless of prefix. ■ Common register bank prefix (CMR) To facilitate data exchange between multiple tasks, the same register bank needs to be easily accessed regardless of each register bank pointer (RP) value. If CMR is inserted before an instruction that accesses a register bank, the instruction accesses the common bank with addresses ranging from 000180 to 00018F...
Page 64 CHAPTER 2 CPU ■ Interrupt suppress instruction No interrupt requests are sampled on ten types of instruction as follows. MOV ILM, #imm8/PCB/SPB/OR CCR, #imm8/NCC AND CCR, #imm8/ADB/CMR/POPW PS/DTB If an effective interrupt request is issued when any of above instructions is executed, an interrupt may be processed only if instructions other than the above are executed.
Page 65: Chapter 3 Interrupt
CHAPTER 3 INTERRUPT This chapter explains interrupts and direct memory access (DMA). 3.1 Overview of Interrupt 3.2 Interrupt Factor and Interrupt Vector 3.3 Interrupt Control Register and Peripheral Function 3.4 Hardware Interrupt 3.5 Software Interrupt 3.6 Interrupt by μDMAC 3.7 Interrupt by Extended Intelligent I/O Service (EI 3.8 Exception Processing Interrupt 3.9 Stack Operation of Interrupt Processing 3.10 Sample Program of Interrupt Processing...
Page 66: Overview Of Interrupt
CHAPTER 3 INTERRUPT Overview of Interrupt MC-16LX has the following four interrupt functions that temporarily stop processing currently being performed and make the control move to programs defined separately when certain events occur: • Hardware interrupt • Software interrupt • Interrupt by μDMAC •...
Page 67 CHAPTER 3 INTERRUPT ■ Overall flow of interrupt operation Four types of interrupt functions provide start and return processing, as shown in Figure 3.1-1. Figure 3.1-1 Overall flow of interrupt operation START Main program Valid hardware Interrupt start and return processing interrupt request String-type instruction being...
Page 68: Interrupt Factor And Interrupt Vector
FFFFC4 FFFFC5 FFFFC6 Unused Hardware interrupt #3 INT254 FFFC04 FFFC05 FFFC06 Unused #254 None INT255 FFFC00 FFFC01 FFFC02 Unused #255 None Reference: For interrupt vectors that are not used, Fujitsu recommends specifying such vectors for the address for exception processing.
Page 69 CHAPTER 3 INTERRUPT ■ Interrupt factors, interrupt vector, and interrupt control register Table 3.2-2 shows the relationship among interrupt factors excluding software interrupts, interrupt vectors, and interrupt control registers. Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (1 / 2) Interrupt control μDMAC Interrupt vector...
Page 70 CHAPTER 3 INTERRUPT Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (2 / 2) Interrupt control μDMAC Interrupt vector register Interrupt factor channel clear number Number Address Number Address ❍ × Output compare (ch.5) match FFFF78 ICR11 0000BB ❍...
Page 71: Interrupt Control Register And Peripheral Function
CHAPTER 3 INTERRUPT Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller, and they correspond to every peripheral function that has an interrupt function. This register controls interrupts. ■ List of interrupt control registers Table 3.3-1 lists interrupt control registers and the corresponding peripheral functions.
Page 72: Interrupt Control Register (Icr00 To Icr15)
CHAPTER 3 INTERRUPT 3.3.1 Interrupt Control Register (ICR00 to ICR15) The interrupt control register (ICR00 to ICR15) corresponds to every peripheral function that has interrupt functions for controlling processing during interrupt request generation. This register has different functions between write and read operations.
Page 73 CHAPTER 3 INTERRUPT ■ Function of each bit in interrupt control register (ICR00 to ICR15) ❍ Interrupt level setting bit (IL2 to IL0) This specifies the corresponding interrupt level in the peripheral function. A reset initializes the bit to level 7 (no interrupts). Table 3.3-2 lists the relationship between interrupt level setting bits and every interrupt level.
Page 74 CHAPTER 3 INTERRUPT ❍ Extended intelligent I/O service (EI OS) status bit (S1, S0) S1, S0 bits are read-only bits. Whether the state is operating or terminated can be read by confirming the S1, S0 bits value at the end of EI OS.
Page 75: Hardware Interrupt
CHAPTER 3 INTERRUPT Hardware Interrupt Hardware interrupt is a function to temporarily stop the execution of program being executed by the CPU in response to an interrupt request signal from the peripheral function. It then moves control to the interrupt processing program defined by a user. Also, μDMAC and external interrupt may be executed as a kind of hardware interrupt.
Page 76 CHAPTER 3 INTERRUPT ■ Configuration of hardware interrupt The hardware-interrupt mechanism is divided into four parts, as shown in Table 3.4-1. To use hardware interrupts, a program must contain settings for the four locations. Table 3.4-1 Hardware-interrupt mechanism Hardware-interrupt mechanism Function Interrupt enable bit, interrupt Control of interrupt request by peripheral...
Page 77 CHAPTER 3 INTERRUPT ❍ Suppressing hardware interrupts in the interrupt suppress instruction Of the ten types of hardware interrupt suppress instruction listed in Table 3.4-2, none can detect whether or not hardware interrupt requests are present, and none can ignore an interrupt request.
Page 78: Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.1 Hardware Interrupt Operation This section explains an operation starting from hardware interrupt request generation until completion of interrupt processing. ■ Starting hardware interrupt ❍ Operation of peripheral function (generating an interrupt request) The peripheral functions including hardware interrupt request functions have the "interrupt request flag"...
Page 79 CHAPTER 3 INTERRUPT ■ Hardware interrupt operation Figure 3.4-2 shows the operation from the generation of hardware interrupt until the completion of interrupt processing. Figure 3.4-2 Hardware interrupt operation Internal data bus PS,PC Microcode Check Comparator MC-16LX CPU Other peripheral function Peripheral function generating an interrupt request...
Page 80: Flow Of Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.2 Flow of Hardware Interrupt Operation If an interrupt request is generated by a peripheral function, the interrupt controller transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the instruction currently being executed is temporarily suspended to execute the interrupt processing routine or to start μDMAC.
Page 81: Procedure For Using Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4.3 Procedure for Using Hardware Interrupt To use hardware interrupts, necessary setup including the system stack area, peripheral functions, and interrupt control registers (ICR) must be performed. ■ Procedure for using hardware interrupt Figure 3.4-4 shows an example of a procedure for using hardware interrupts. Figure 3.4-4 Procedure for using hardware interrupt Start Setup of the system...
Page 82 CHAPTER 3 INTERRUPT (7) Interrupt processing hardware saves registers to branch to the interrupt processing program. (8) The interrupt processing program processes peripheral functions because of interrupt generation. (9) The interrupt request from peripheral function is canceled. (10) The interrupt return instruction is executed, and the program is restored to what it was before branching.
Page 83: Multiple Interrupts
CHAPTER 3 INTERRUPT 3.4.4 Multiple Interrupts Multiple hardware interrupt can be executed by specifying a different interrupt level for each interrupt level setting bit (IL0 to IL2) in the interrupt control register (ICR) in response to multiple interrupt request from the peripheral function. μDMACs cannot be started in duplicate, however.
Page 84 CHAPTER 3 INTERRUPT ❍ A/D interrupt generation When the A/D converter interrupt processing starts, the interrupt level mask register (ILM) is automatically set to the same interrupt level (i.e., 2 in this example) as that for the A/D converter (IL2 to IL0 in ICR). In this example, if an interrupt request of level 1 or 0 is generated, the interrupt with higher priority is executed first.
Page 85: Hardware Interrupt Processing Time
CHAPTER 3 INTERRUPT 3.4.5 Hardware Interrupt Processing Time The time period starting from generation of a hardware interrupt request until the execution of interrupt handling routine requires the time until the instruction currently being executed is completed plus the interrupt processing time. ■...
Page 86 CHAPTER 3 INTERRUPT ❍ Interrupt processing time (θ machine cycles) After the CPU accepts an interrupt request, the CPU saves the dedicated registers in the system stack and fetches the interrupt vector. The interrupt processing time is thus derived from the following formula: At interrupt start: θ...
Page 87: Software Interrupt
CHAPTER 3 INTERRUPT Software Interrupt Software interrupt is a function used to move control to the user-defined program for interrupt processing from a program that the CPU is being executed if a software interrupt instruction (INT instruction) is executed. A hardware interrupt is stopped while a software interrupt is executed.
Page 88 CHAPTER 3 INTERRUPT ■ Software interrupt operation Figure 3.5-1 shows the operation starting from software interrupt generation until interrupt processing completion. Figure 3.5-1 Software interrupt operation Internal data bus PS,PC (2) Microcode Queue Fetch PS : Processor status : Interrupt enable flag S : Stack flag IR : Instruction register 1.
Page 89: Interrupt By Μdmac
CHAPTER 3 INTERRUPT Interrupt by μDMAC The μDMAC controller is a simplified DMA that has the same function as EI OS. DMA transfers are set up using the DMA descriptor. μDMAC functions ■ μDMAC has the functions listed below. • Provides an automatic data transfer between a peripheral resource (I/O) and memory.
Page 90 CHAPTER 3 INTERRUPT μDMAC enable register (DER) has the bit functions listed below. ENx bit Function Outputs an interrupt request from a resource to the interrupt controller. (Initial value) (An interrupt request from a resource is not used as a DMA start request). An interrupt request output from a resource is used as a DMA start request.
Page 91 CHAPTER 3 INTERRUPT The functions of each bit in the μDMAC status register (DSR) is shown in the table below. DEx bit Function No DMA transfer has ended. (Initial value) If the DMA transfer ends, an interrupt request is output to the interrupt controller.
Page 92: Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.1 DMA Descriptor The DMA descriptor is located in internal RAM within a range from "000100 " to "00017F " consisting of 8 bytes x 16 channels. ■ DMA descriptor configuration The DMA descriptor consists of 8 bytes x 16 channels. Each DMA descriptor has the configuration shown in the Figure 3.6-2.
Page 93 CHAPTER 3 INTERRUPT Table 3.6-1 Relationship between channel number and descriptor address μDMAC enable Descriptor Channel Resource interrupt request register address 000100 INT0 000108 PWC0 (Only MB90485 series) 000110 PPG0/PPG1 counter borrow 000118 PPG2/PPG3 counter borrow 000120 PPG4/PPG5 counter borrow 000128 Input capture (channel 0) load 000130...
Page 94: Individual Registers Of Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.2 Individual Registers of DMA Descriptor Each DMA descriptor consists of the following registers: • Data counter (DCT) • I/O register address pointer (IOA) • DMA control status register (DMACS) • Buffer address pointer (BAP) The registers must be initialized because their initial values become undefined when they are reset.
Page 95 CHAPTER 3 INTERRUPT ■ DMA control status register (DMACS) The DMA control status register (DMACS) has a length of 8 bits that indicate the update or fixed state, transfer data format (byte/word), and transfer directions for the buffer address pointer (BAP) and I/O register address pointer (IOA).
Page 96 CHAPTER 3 INTERRUPT ■ Buffer address pointer (BAP) The buffer address pointer (BAP) has a length of 24 bits, containing the address used in the next DMA transfer. BAP is independent from each DMA channel, so each DMA channel can transfer data between any of 16M bytes addresses and I/O.
Page 97: Μdmac Processing Procedure
CHAPTER 3 INTERRUPT μDMAC Processing Procedure 3.6.3 If an interrupt request is generated by a peripheral resource (I/O) and the corresponding μDMAC enable register (DER) has a setting of DMA start, then a DMA transfer is performed. If a data transfer ends at the specified count, an interrupt request is output to the interrupt controller.
Page 98: Μdmac Processing Time
CHAPTER 3 INTERRUPT μDMAC Processing Time 3.6.4 Time consumed in μDMAC processing varies with the following factors: • Settings of DMA control status register (DMACS) • Address (area) indicated by the I/O register address pointer (IOA) • Address (area) indicated by the buffer address pointer (BAP) •...
Page 99 CHAPTER 3 INTERRUPT Note: B indicates a byte data transfer, 8 indicates a word transfer with an external bus width of 8 bits, even indicates word transfer of an even-numbered address, and odd indicates a word transfer of an odd-numbered address. ❍...
Page 100: Interrupt By Extended Intelligent I/O Service (Ei Os)
CHAPTER 3 INTERRUPT Interrupt by Extended Intelligent I/O Service (EI Extended Intelligent I/O Services (EI OS) are a function that automatically transfers data between the peripheral function (I/O) and RAM. After completion of the data transfer, hardware interruptions will occur. ■...
Page 101 CHAPTER 3 INTERRUPT ■ Operation of EI Figure 3.7-1 Operation of EI Memory Space Peripheral function (Resource) by I/OA Resource Resource register register Interrupt request by ICS Interrupt Control Register (ICR) Interrupt controller by BAP Buffer Count by DCT : EI OS descriptor I/OA : I/O address pointer...
Page 102: Ei 2 Os Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.7.1 OS descriptor (ISD) OS descriptor (ISD) which is in 000100 to 00017F of built-in RAM is consists of 8- byte x 16 channels. ■ Configuration of EI OS Descriptor (ISD) ISD comprises 8-byte x 16 channels. Figure 3.7-2 Configuration of EI OS Descriptor (ISD) Data counter upper 8bit (DCTH)
Page 103 CHAPTER 3 INTERRUPT Table 3.7-1 Relation between channel number and descriptor address Channel Descriptor address* 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 *:The address of ISD indicates the first address of 8-byte.
Page 104: Each Register Of Ei 2 Os Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.7.2 Each Register of EI OS Descriptor (ISD) Extended intelligent I/O service (EI OS) descriptor (ISD) is configurated by following 4 types of 8-byte registers. • Data counter (DCT: 2 bytes) • I/O register address pointer (IOA: 2 bytes) •...
Page 105 CHAPTER 3 INTERRUPT ■ OS Status Register (ISCS) OS status register (ISCS) is 8-bit register. The methods to renew the buffer address pointer and I/O address pointer, the transfer data type (byte/word) and the transfer direction can be specified. Figure 3.7-5 Configuration of EI OS Status Register (ISCS) Initial value XXXXXXXX...
Page 106 CHAPTER 3 INTERRUPT ■ Buffer address pointer (BAP) Buffer address pointer (BAP) is 24-bit register. EI OS operation set the memory address of the data transferring source. Buffer address pointer exists in each channel. So, the data can be transferring between the 16M-byte memory address and the peripheral function (resource) address.
Page 107: Operation Of Ei 2 Os
CHAPTER 3 INTERRUPT 3.7.3 Operation of EI CPU transfers the data by EI OS, when the interrupt request is output from the peripheral function (resource) and the interrupt control register has been set to the start of EI OS. When the EI OS operation ends, hardware interrupt is done.
Page 108: Procedure For Use Of Ei
CHAPTER 3 INTERRUPT 3.7.4 Procedure for Use of EI The setting of extended intelligent I/O service (EI OS) is set by the system stack area, the extended intelligent I/O service (EI OS) descriptor, the peripheral function (resource), and the interrupt control register (ICR). ■...
Page 109: Processing Time Of The Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.7.5 Processing Time of the Extended Intelligent I/O Service The time required for processing the extended intelligent I/O service (EI OS) depends on setting of the extended intelligent I/O service descriptor (ISD). • EI OS status register (ISCS) setting •...
Page 110 CHAPTER 3 INTERRUPT ● When the data counter (DCT) count terminates (final data transfer) Because the hardware interrupt is activated when data transfer by EI OS terminates, the interrupt handling time is added. The EI OS processing time when counting terminates is calculated with the following formula : OS processing time when data is transferred (21 + 6 ×...
Page 111: Exception Processing Interrupt
CHAPTER 3 INTERRUPT Exception Processing Interrupt In the F MC-16LX, the execution of an undefined instruction results in exception processing. Exception processing is basically the same as an interrupt. When the generation of an exception processing is detected on the instruction boundary, ordinary processing is interrupted and exception processing is executed.
Page 112: Stack Operation Of Interrupt Processing
CHAPTER 3 INTERRUPT Stack Operation of Interrupt Processing If an interrupt is accepted, contents of the dedicated registers are automatically saved in the system stack before branching to interrupt processing. Return from the stack is also automatically performed when interrupt processing is completed. ■...
Page 113 CHAPTER 3 INTERRUPT ■ Stack area ❍ Assigning the stack area The stack area is used for storage and return of the program counter (PC) required for executing interrupt processing, subroutine call instruction (CALL) and vector call instruction (CALLV), as well as temporary save and return of registers executed by using the PUSHW and POPW instructions.
Page 114: Sample Program Of Interrupt Processing
CHAPTER 3 INTERRUPT 3.10 Sample Program of Interrupt Processing A sample program for interrupt processing is shown below. ■ Sample program for interrupt processing ❍ Processing specification An example of an interrupt program using external interrupt 0 (INT0) is shown. Sample coding from the program is shown below.
Page 115: Delay Interrupt Generation Module
"0" clears the delay interrupt request. Resetting causes the factor clear state. Either "0" or "1" can be written to the reserve bit area. For future expansion, however, Fujitsu recommends using the set bit or clear bit instructions to access this register.
Page 116: Operation Of Delay Interrupt Generation Module
CHAPTER 3 INTERRUPT 3.11.1 Operation of Delay Interrupt Generation Module If CPU writes "1" to the relevant DIRR bit with software, the request latch in the delay interrupt generation module is set to generate an interrupt request to the interrupt controller.
Page 117: Chapter 4 Reset
CHAPTER 4 RESET This chapter explains reset for the MB90480/485 series. 4.1 Overview of Reset 4.2 Reset Factors and Oscillation Stabilization Wait Time 4.3 External-Reset Pin 4.4 Resetting 4.5 Reset-Factor Bits 4.6 Condition of Pins as Result of Reset...
Page 118: Overview Of Reset
CHAPTER 4 RESET Overview of Reset If a reset factor occurs, the CPU immediately stops the processing currently in progress and stands by for cancellation of the reset. After the reset is canceled, processing starts at the address specified by the reset vector. A reset is triggered by the following four factors: •...
Page 119 CHAPTER 4 RESET ❍ External reset An external reset is triggered by input of the "L" level to the external-reset pin (pin RST). More than 16 machine cycles (16/φ) is required for the "L" level input time to pin RST. An external reset (pin RST input reset) does not require the oscillation stabilization wait time.
Page 120: Reset Factors And Oscillation Stabilization Wait Time
CHAPTER 4 RESET Reset Factors and Oscillation Stabilization Wait Time The four types of reset factors can occur in the MB90480/485 series devices. The oscillation stabilization wait time during a reset varies depending on the reset factor. ■ Reset factors and oscillation stabilization wait time Table 4.2-1 summarizes the reset factors and the oscillation stabilization wait time.
Page 121 CHAPTER 4 RESET Figure 4.2-1 shows the oscillation stabilization wait time for evaluation devices, flash memory devices, and mask ROM devices during a power-on reset. Figure 4.2-1 Waiting times to stable oscillation for evaluation devices/flash memory devices and mask ROM devices during power-on reset Evaluation device/FLASH device /HCLK /HCLK...
Page 122: External-Reset Pin
CHAPTER 4 RESET External-Reset Pin The external-reset pin (pin RST) is a pin dedicated for the input of resets, and it triggers an internal reset by input of the "L" level. The MB90480/485 series devices have resets synchronized to the CPU operation clock. However, only external pins (e.g., ports) change asynchronously to a reset state.
Page 123: Resetting
CHAPTER 4 RESET Resetting After the cancellation of a reset, a read from operation of mode data and the reset vector can be selected by setting the mode pin to perform mode fetching. Mode fetching determines the CPU operation mode and the start address of execution after the end of a reset.
Page 124 ROM or external memory. If the external vector mode is specified with a mode pin, however, external memory and not internal ROM is accessed to read reset vectors and mode data. Fujitsu recommends specifying the internal vector mode with a mode pin when the single- chip mode and internal ROM external bus mode are used.
Page 125: Reset-Factor Bits
CHAPTER 4 RESET Reset-Factor Bits Reset factors can be determined by reading the watchdog timer control register (WDTC). ■ Reset-factor bits As shown in the Figure 4.5-1, each reset factor has a corresponding flip-flop assigned to it. This information can be obtained by reading the watchdog timer control register (WDTC). If a reset factor must be determined after a reset cancellation, run software to process the read value of the WDTC register, and branch to an appropriate program.
Page 126 CHAPTER 4 RESET ■ Correspondence between reset-factor bits and reset factors Figure 4.5-2 shows the configuration of the reset-factor bits for the watchdog timer control register (WDTC). Table 4.5-1 shows the correspondence between reset-factor bits and reset factors. For details, refer to Section "10.2 Watchdog Timer Control Register (WDTC)". Figure 4.5-2 Configuration of reset-factor bits (watchdog timer control register) 15 - - - - - - - 8 0000A8...
Page 127: Condition Of Pins As Result Of Reset
CHAPTER 4 RESET Condition of Pins as Result of Reset This section explains the states of pins after a reset. ■ Pin states during a reset States of the pins during a reset are determined by the settings of mode pins (MD2 to MD0). ❍...
Page 128 CHAPTER 4 RESET...
Page 129: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter describes the clocks of the MB90480/485 series. 5.1 Overview of Clocks 5.2 Block Diagram of Clock Generator 5.3 Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) 5.4 Clock Modes 5.5 Oscillation Stabilization Wait Time 5.6 Connecting Oscillator to External Clock...
Page 130: Overview Of Clocks
CHAPTER 5 CLOCKS Overview of Clocks The clock generator controls the operations of internal clocks, which are the operation clocks of the CPU and peripheral functions. In this document, the clocks are called as follows according to clock type: • Machine clock: Defined as an internal clock. •...
Page 131 CHAPTER 5 CLOCKS ■ Clock supply map Machine clocks generated by the clock generator are supplied as operation clocks of the CPU and peripheral functions. Therefore, operations of the CPU and peripheral functions are affected by changes between the main clock and PLL clock (clock mode) and by changes in the PLL clock multiplication rate.
Page 132: Block Diagram Of Clock Generator
CHAPTER 5 CLOCKS Block Diagram of Clock Generator The clock generator consists of the following five blocks: • System clock generator circuit/sub-clock generator circuit • PLL multiplier circuit • Clock selector • Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) •...
Page 133 CHAPTER 5 CLOCKS ❍ System clock generator circuit This circuit generates an oscillation clock (HCLK) by using an oscillator connected to the high- speed oscillation pin. Also, an external clock can be input to it. ❍ Sub-clock generator circuit This circuit generates a sub-clock (SCLK) by using an oscillator connected to the low-speed oscillation pin.
Page 134: Clock Selection Register (Ckscr) And Pll Output Selection Register (Pllos)
CHAPTER 5 CLOCKS Clock Selection Register (CKSCR) and PLL Output Selection Register (PLLOS) The clock selection register (CKSCR) switches among the main clock, sub-clock, and PLL clock, and it selects the oscillation stabilization wait time and PLL clock multiplication rate. The PLL output selection register (PLLOS) must be set for the PLL to be used when a machine clock is used at a frequency of 20 to 25 MHz.
Page 135 CHAPTER 5 CLOCKS Note: When reset, the machine clock selection (MCS) bit is initialized to the main clock selection. Table 5.3-1 Functions of bits in clock selection register (CKSCR) (1/2) Bit name Function This bit displays whether the main clock or sub-clock is selected as a machine clock.
Page 136 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) (2/2) Bit name Function This bit specifies selection of the main clock or sub-clock as a machine clock. • If this bit is "0", the sub-clock is selected. If "1", the main clock is selected.
Page 137 CHAPTER 5 CLOCKS ■ Configuration of PLL output selection register (PLLOS) Figure 5.3-2 shows the configuration of the PLL output selection register (PLLOS). Table 5.3-2 explains the functions of the bits for the PLL output selection register. Figure 5.3-2 Configuration of PLL output selection register (PLLOS) Address Initial value DIV2 PLL2...
Page 138 CHAPTER 5 CLOCKS Table 5.3-2 Functions of bits for PLL output selection register (PLLOS) Bit name Function Undefined Not used bit15 to bit10 bits • This bit selects dividing of input clock to PLL or input as it • It is initialized to "0" by all reset sources. •...
Page 139: Clock Modes
CHAPTER 5 CLOCKS Clock Modes The clock modes are the main clock, PLL clock, and sub-clock modes. ■ Main clock mode, PLL clock mode, and sub-clock mode ❍ Main clock mode The main clock mode uses a clock obtained by dividing the oscillation clock by two as the operation clock of the CPU and peripheral resources.
Page 140 CHAPTER 5 CLOCKS ❍ Change from the PLL clock mode to the sub-clock mode Rewriting the sub-clock selection bit (SCS) of the clock selection register (CKSCR) from "1" to "0" in the PLL clock mode changes the PLL clock to the sub-clock. ❍...
Page 141 CHAPTER 5 CLOCKS Figure 5.4-1 State transition diagram of machine clock selection Main→Sub MCS=1 MCM=1 Main SCS=0 (10) MCS=1 SCM=1 MCS=1 MCM=1 CS1,CS0=xx MCM=1 (16) SCS=1 SCS=0 SCM=1 Sub→Main (10) (11) SCM=0 CS1,CS0=xx MCS=1 CS1,CS0=xx MCM=1 SCS=1 SCM=0 Main→PLLx Sub→PLL CS1,CS0=xx (12) MCS=0...
Page 142 CHAPTER 5 CLOCKS (1) MCS bit "0" write (2) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 00 (3) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 01 (4) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 10 (5) Waiting for PLL clock oscillation stability is complete.
Page 143: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCKS Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released, or switching from the sub- clock to the main clock or from sub-clock to the PLL clock occurs, an oscillation stabilization wait time is required after oscillation begins because the oscillation clock is stopped.
Page 144: Connecting Oscillator To External Clock
CHAPTER 5 CLOCKS Connecting Oscillator to External Clock Devices in the MB90480/485 series contain a system clock generator circuit and generate clocks using an externally connected oscillator. Also, an external clock can be input to it. ■ Connection of oscillator and external clock ❍...
Page 145: Chapter 6 Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of the MB90480/485 series. 6.1 Overview of Low-Power Consumption Mode 6.2 Block Diagram of Low-Power Consumption Control Circuit 6.3 Low-Power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Transition Diagram 6.7 Pin State in Standby Mode, Hold, and Reset...
Page 146: Overview Of Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Overview of Low-Power Consumption Mode The following CPU operation modes are available on the MB90480/485 series devices by selecting a suitable operation clock and by controlling clock operation. • Clock modes (Main clock mode, and sub-clock mode) •...
Page 147 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Clock modes ❍ Main clock mode This mode operates the CPU and peripheral functions by using the clock of the oscillation clock (HCLK) divided by two. The PLL multiplier circuit stops its operation in the main clock mode. ❍...
Page 148: Block Diagram Of Low-Power Consumption Control Circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE Block Diagram of Low-Power Consumption Control Circuit The low-power consumption control circuit is composed of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU-clock control circuit • Peripheral clock control circuit •...
Page 149 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ CPU intermittent operation selector The CPU intermittent operation selector selects the number of pause clocks in the CPU intermittent operation mode. ❍ Standby control circuit The standby control circuit controls the CPU-clock control circuit and peripheral clock control circuit for resetting and changing to the low-power consumption mode.
Page 150: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW-POWER CONSUMPTION MODE Low-Power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs functions including changing the current mode to the low-power consumption mode, canceling from the low-power consumption mode, and specifying the number of CPU-clock pause cycles in the CPU intermittent operation mode.
Page 151 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.3-1 Functions of bits in low-power consumption mode control register (LPMCR) Bit name Function This bit instructs a change to the stop mode. • Write "1" in this bit to change the mode to the stop mode. STP: bit7 •...
Page 152 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Accessing low-power consumption mode control register Writing in the low-power consumption mode control register executes a change to the standby mode (stop, sleep, timebase timer and watch modes). Use the instructions listed in Table 6.3-2. The low-power consumption mode transition instruction in Table 6.3-2 must always be followed by an array of instructions highlighted by a line below.
Page 153: Cpu Intermittent Operation Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE CPU Intermittent Operation Mode The CPU intermittent operation mode reduces power consumption by intermittently operating the CPU while operating external buses and peripheral functions at high speeds. ■ CPU intermittent operation mode To delay activation of the internal bus cycle, the CPU intermittent operation mode stops clocks supplied to the CPU for a preset period for each instruction during access to registers, embedded memory (ROM or RAM), I/O, peripheral functions, and external buses.
Page 154: Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Standby Mode The standby mode is divided into four modes, namely, the sleep (PLL sleep, main sleep, and sub sleep), timebase timer, watch, and stop modes. ■ Operational states in standby mode Table 6.5-1 lists operational states in the standby mode. Table 6.5-1 Operational states in standby mode Change Machine...
Page 155: Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.1 Sleep Mode The sleep mode stops CPU operation clocks, allowing devices other than the CPU to continue operation. ■ Change to sleep mode Writing "1" in the sleep mode bit (SLP), "1" in the watch/timebase timer mode bit (TMD), and "0" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) changes the mode to the sleep mode.
Page 156 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Canceling the sleep mode The low-power consumption control circuit cancels the sleep mode by input of a reset or by an interrupt. ❍ Restore by a reset Reset initializes to the main clock mode. ❍...
Page 157: Timebase Timer Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.2 Timebase Timer Mode The timebase timer mode stops operations except for source oscillation, timebase timer and watch timer. All functions except the timebase timer and watch timer are stopped. ■ Change to timebase timer mode To change the mode to the timebase timer mode, write "0"...
Page 158 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the timebase timer mode is normally executed first before an interrupt request is processed. If a change to the timebase timer mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed.
Page 159: Watch Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.3 Watch Mode The watch mode stops operations other than those of the sub-clock and watch timer. Almost all functions on the chip are stopped. ■ Change to watch mode To change the mode to the watch mode, write "0" in watch/timebase timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) in the sub-clock mode (sub-clock display bit (SCS) = 0 of the clock selection register (CKSCR)).
Page 160 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Return by interrupt The watch mode is canceled by the low-power consumption control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0=111 of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the watch mode.
Page 161: Stop Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.4 Stop Mode The stop mode stops source oscillation and stops all functions, thereby enabling retention of data with the lowest consumption of power. ■ Change to stop mode Write "1" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) to change the mode to the stop mode.
Page 162 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Restore by interrupt The stop mode is canceled by the low-power consumption control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0=111 of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the stop mode.
Page 163: State Transition Diagram
CHAPTER 6 LOW-POWER CONSUMPTION MODE State Transition Diagram This section explains the transition of operational states for the MB90480/485 series and describes the transition conditions. ■ State transition diagram Figure 6.6-1 illustrates the transition of operational states for the MB90480/485 series and the transition conditions.
Page 164 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Operational state in low-power consumption mode Table 6.6-1 lists operational states in the low-power consumption mode. Table 6.6-1 Operational states in low-power consumption mode Main Sub- Timebase Clock Operational state PLL clock Peripheral Watch clock clock timer...
Page 165: Pin State In Standby Mode, Hold, And Reset
CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in Standby Mode, Hold, and Reset The states of the pins in the standby mode and in the hold and reset states are described for each memory access mode. ■ Pin state in single chip mode Table 6.7-1 lists the pin states in the single-chip mode.
Page 166 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode Table 6.7-2 summarizes pin states in the external bus 16-bit data bus mode and multiplex 16-bit external bus mode. Table 6.7-2 Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode When stopped Internal ROM...
Page 167 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode Table 6.7-3 lists pin states in the external bus 8-bit data bus mode and multiplex 8-bit external bus mode. Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode When stopped Internal ROM...
Page 168 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode Table 6.7-4 lists pin states in the external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode. Table 6.7-4 Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode When stopped Internal ROM...
Page 169 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode Table 6.7-5 summarizes pin states in the external bus 8-bit data bus mode and non-multiplex 8- bit external bus mode. Table 6.7-5 Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode When stopped Internal ROM...
Page 170: Caution On Using Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Caution on Using Low-Power Consumption Mode When operating in the low-power consumption mode, exercise reasonable care concerning the following: • Change to the standby mode and interrupts • Cancellation of standby mode by interrupt • Cancellation of stop mode •...
Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Oscillation stabilization wait time ❍ Oscillation stabilization wait time of oscillation clock The oscillator for source oscillation is stopped in the stop mode, and a oscillation stabilization wait time must be provided. Specify the oscillation stabilization wait time selected with the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR).
Page 172 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode • To access the low-power consumption mode control register (LPMCR) with assembler language - To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2.
Page 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I: _IO_LPMCR,#H'98 /* Set LPMCR STP bit to "1" */ /* Jump to next instruction */ #pragma endasm...
Page 174 CHAPTER 6 LOW-POWER CONSUMPTION MODE...
Page 175: Chapter 7 Mode Setting
CHAPTER 7 MODE SETTING This chapter explains mode setting, mode pins, mode data, external memory access and its operation. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data 7.4 External Memory Access 7.5 Operation of Each Mode for Mode Setting...
Page 176: Mode Setting
CHAPTER 7 MODE SETTING Mode Setting The F MC-16LX has different modes in each access system and access area. Each mode is set according to a mode pin at the reset state and according to mode data obtained by mode-fetch. ■...
Page 177: Mode Pins (Md2 To Md0)
CHAPTER 7 MODE SETTING Mode Pins (MD2 to MD0) Mode pins are three external pins (MD2 to MD0) that specify the reset vector and mode data fetching method. ■ Settings of mode pins (MD2 to MD0) Mode pins (MD2 to MD0) are used to select the source, either the external or internal data bus when reset vectors are read and stored, and to select the bus width when the external data bus is used.
Page 178: Mode Data
CHAPTER 7 MODE SETTING Mode Data Mode data stored at address FFFFDF in memory specifies the operation immediately after the reset sequence. Mode data is read and stored in the CPU automatically by mode fetching. ■ Mode data During the reset sequence, mode data at address FFFFDF is sent to the mode register in the CPU core.
Page 179 CHAPTER 7 MODE SETTING ■ Bus mode setting bits (M1, M0) Bits M1 and M0 specify the operation mode that is set after completion of the reset sequence. Table 7.3-2 lists the contents of the settings for bits M1 and M0. Table 7.3-2 Contents of bit M1 and M0 settings Functions Single-chip mode...
Page 180 CHAPTER 7 MODE SETTING ■ Relationship between mode pins and mode data (an example showing recommended relationship) Table 7.3-3 shows the relationship between mode pins and mode data. Table 7.3-3 Relationship between mode pins and mode data Mode Single chip Internal ROM external bus mode, 8-bit (address data multiplex) Internal ROM external bus mode, 16-bit...
Page 181 CHAPTER 7 MODE SETTING ■ Operation of external pins in each mode Table 7.3-4 shows the operation of each external pin in the non-multiplex mode and multiplex mode. Table 7.3-4 Operation of external pins in each mode Functions Non-multiplex mode Multiplex mode External address control External address control...
Page 182: External Memory Access
CHAPTER 7 MODE SETTING External Memory Access This section contains block diagrams about external memory access, the configuration and functions of registers, and operation of external memory access. ■ I/O signal pins for external memory access For accessing external memory and peripheral devices, the F MC-16LX supplies the following address, data, and control signals: •...
Page 183 CHAPTER 7 MODE SETTING ■ List of registers Figure 7.4-2 shows a list of registers in the external bus pin control circuit. Figure 7.4-2 Registers in external bus pin control circuit Automatic ready function selection register (ARSR) 0000A5 IOR1 IOR0 HMR1 HMR0 LMR1...
Page 184: Automatic Ready Function Selection Register (Arsr)
CHAPTER 7 MODE SETTING 7.4.1 Automatic ready function selection register (ARSR) This section shows the configuration and explains the function of the automatic ready function selection register (ARSR) ■ Automatic ready function selection register (ARSR) The bit configuration of the automatic ready function selection register (ARSR) is shown in the figure below.
Page 185 CHAPTER 7 MODE SETTING [bit9, bit8] LMR1, LMR0 These bits are used to select the automatic wait function for external access to areas in a range of 002000 to 7FFFFF . Contents of settings are listed below. LMR1 LMR0 Setting Automatic wait prohibited [Initial value] Automatic wait in 1 machine cycle during external access Automatic wait in 2 machine cycle during external access...
Page 186: External Address Output Control Register (Hacr)
CHAPTER 7 MODE SETTING 7.4.2 External address output control register (HACR) This section shows the configuration and explains the function of the external address output control register. ■ External address output control register (HACR) The bit configuration of the external address output control register is shown in the figure below. External address output control register 0000A6...
Page 187: Bus Control Signal Selection Register (Epcr)
CHAPTER 7 MODE SETTING 7.4.3 Bus control signal selection register (EPCR) This section shows the configuration and explains the function of the bus control signal selection register. ■ Bus control signal selection register (EPCR) The bus control signal selection register (EPCR) sets the bus operation control function in external bus mode.
Page 188 CHAPTER 7 MODE SETTING [bit12] IOBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 0000D0 to 0000FF in the external data bus 16-bit mode. 16-bit bus width access [Initial value] 8-bit bus width access [bit11] HMBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 800000...
Page 189: Operation Of Each Mode For Mode Setting
CHAPTER 7 MODE SETTING Operation of Each Mode for Mode Setting This section has a timing chart showing the operation of each mode for mode setting. ■ Types of mode Operation with the following items is categorized by function as follows: •...
Page 190: External Memory Access Control Signals
CHAPTER 7 MODE SETTING 7.5.1 External memory access control signals Access to external memory is performed in 3 cycles when the ready function is not used. ■ External memory access control signal Timing charts for external access in each mode are shown in Figure 7.5-1 to Figure 7.5-4. Access with an 8-bit bus width in the 16-bit external data bus mode is a function for reading from and writing to peripheral chips of an 8-bit width when a mixture of peripheral chips of an 8- bit width and 16-bit width are connected to the external bus.
Page 191 CHAPTER 7 MODE SETTING ❍ External data bus 8-bit mode (multiplex mode) Figure 7.5-2 Access timing chart of external data bus 8-bit mode (multiplex mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE Write address A23 to 16 Read address Read address A15 to 08...
Page 192 CHAPTER 7 MODE SETTING ❍ External data bus 16-bit mode (multiplex mode) Figure 7.5-4 Access timing chart of external data bus 16-bit mode (multiplex mode) Read Write Read P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address Read address A15 to 08 (Port data)
Page 193: Ready Function
CHAPTER 7 MODE SETTING 7.5.2 Ready function By setting the P56/RDY pin or defining the automatic ready function selection register (ARSR), access to low-speed memory and peripheral circuits is enabled. If the RYE bit in the bus control signal selection register (EPCR) is set to "1", wait cycles are generated during the period where the "L"...
Page 194 CHAPTER 7 MODE SETTING ❍ Non-multiplex mode Figure 7.5-5 Timing chart of ready function (non-multiplex mode) Even-numbered Even-numbered address word read address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address Read address A15 to 08 Write address A07 to 00 Read address...
Page 195 CHAPTER 7 MODE SETTING ❍ Multiplex mode Figure 7.5-6 Timing chart of ready function (multiplex mode) Even-numbered Even-numbered address word read address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address A15 to 08 (Port data) A07 to 00 (Port data) D15 to 08/...
Page 196: Hold Function
CHAPTER 7 MODE SETTING 7.5.3 Hold function This section uses timing charts to describe the operation of the hold function. ■ Operation of hold function When the HDE bit of EPCR is set to "1", the external bus hold function specified by both the P54/HRQ and P55/HAK pins becomes effective.
Page 197 CHAPTER 7 MODE SETTING ■ Non-multiplex mode Figure 7.5-7 shows a timing chart of the non-multiplex-mode hold function in the external data bus 16-bit mode. Figure 7.5-7 Timing chart of hold function (non-multiplex mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK...
Page 198 CHAPTER 7 MODE SETTING...
Page 199: Chapter 8 I/O Port
CHAPTER 8 I/O PORT This chapter explains the configuration and the functions of the registers used for the I/O port. 8.1 Functions of I/O Port 8.2 Registers for I/O Port...
Page 200: Functions Of I/O Port
CHAPTER 8 I/O PORT Functions of I/O Port This section outlines the functions of the I/O port. ■ Functions of I/O port The I/O port has functions to output data from the CPU to I/O pins and introduce the signals input to I/O pins to the CPU by using the port register (PDR).
Page 201: Registers For I/O Port
CHAPTER 8 I/O PORT Registers for I/O Port This section shows the configuration and explains the functions of the registers used for the I/O port. ■ Registers for I/O port The registers for the I/O port are listed below: • Port registers (PDR0 to PDRA) •...
Page 202: Port Registers (Pdr0 To Pdra)
CHAPTER 8 I/O PORT 8.2.1 Port registers (PDR0 to PDRA) This section shows the configuration and explains the functions of port registers (PDR0 to PDRA) ■ Port registers (PDR0 to PDRA) Figure 8.2-1 shows a list of port registers (PDR0 to PDRA). Figure 8.2-1 List of port registers (PDR0 to PDRA) PDR0 Initial value...
Page 203: Port Direction Registers (Ddr0 To Ddra)
CHAPTER 8 I/O PORT 8.2.2 Port direction registers (DDR0 to DDRA) This section shows the configuration and explains the functions of port direction registers (DDR0 to DDRA.) ■ Port direction registers (DDR0 to DDRA) Figure 8.2-2 shows a list of port direction registers (DDR0 to DDRA). Figure 8.2-2 List of port direction registers (DDR0 to DDRA) DDR0 Initial value...
Page 204 CHAPTER 8 I/O PORT Notes: • If this register is accessed with a command of the read-modify-write type (such as the bit-set command), the contents of the output registers corresponding to the other bits specified for input are replaced with the input value of the pin at the time of access even if the bit specified by the command is set to the required value.
Page 205: Other Registers
CHAPTER 8 I/O PORT 8.2.3 Other registers This section shows the configuration and explains the functions of registers other than port registers (PDR0 to PDRA) or port direction registers (DDR0 to DDRA). ■ Port input resistor registers (RDR0, RDR1) The bit configuration of port input resistor registers (RDR0, RDR1) is shown in the figure below. RDR0 Initial value Access Address:00001C...
Page 206 CHAPTER 8 I/O PORT ■ Analog input enable register (ADER) The bit configuration of the analog input enable register (ADER) is shown in the figure below. ADER Initial value Access Address:00001F ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111 R/W : Readable/Writable The analog input enable register (ADER) controls the pins of port 6 as follows: •...
Page 207: Chapter 9 Timebase Timer
CHAPTER 9 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 9.1 Overview of Timebase Timer 9.2 Timebase Timer Configuration 9.3 Timebase Timer Control Register (TBTC) 9.4 Timebase Timer Interrupt 9.5 Timebase Timer Operation 9.6 Notes on Using Timebase Timer 9.7 Sample Programs of Timebase timer...
Page 208: Overview Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Overview of Timebase Timer The timebase timer, which is an 18-bit free-running counter (timebase timer counter) that counts up in synchronization with the internal count clock (the source clock frequency divided by 2), has the interval timer function to enable selection for four types of interval times.
Page 209 CHAPTER 9 TIMEBASE TIMER ■ Clock supplying function The clock supplying function is the function supplying the timer for the oscillation stabilization wait time and the operation clocks to some peripheral functions. Table 9.1-2 lists the cycles of the clocks supplied by the timebase timer to individual peripheral functions. Table 9.1-2 Clock cycles supplied by timebase timer Function to which Clock cycle...
Page 210: Timebase Timer Configuration
CHAPTER 9 TIMEBASE TIMER Timebase Timer Configuration The timebase timer is composed of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block diagram of timebase timer Figure 9.2-1 is a block diagram of the timebase timer.
Page 211 CHAPTER 9 TIMEBASE TIMER ❍ Interval timer selector Selects one of the four types for timebase timer counter output. Overflow of the selected bit causes an interrupt. ❍ Timebase timer control register (TBTC) Selects the interval time, clears the counter, controls interrupt requests, and checks the current state.
Page 212: Timebase Timer Control Register (Tbtc)
CHAPTER 9 TIMEBASE TIMER Timebase Timer Control Register (TBTC) This register selects the interval time, clears the counter, controls interrupt requests, and checks the state. ■ Timebase timer control register (TBTC) Figure 9.3-1 Timebase timer control register (TBTC) Initial value bit15 bit14 bit13 bit12 bit11 bit10...
Page 213 CHAPTER 9 TIMEBASE TIMER Table 9.3-1 Functions of bits in timebase timer control register (TBTC) Bit name Function RESV: Always write "1" to this bit. bit15 Reserved bit bit14 • Undefined value in reading Undefined bits bit13 • No effect on write operation TBIE: This bit permits or prohibits output of interrupt requests to the CPU.
Page 214: Timebase Timer Interrupt
CHAPTER 9 TIMEBASE TIMER Timebase Timer Interrupt The timebase timer can generate the interrupt request caused by an overflow of the specified bit in the timebase timer counter (interval timer function). ■ Timebase timer interrupt When the timebase timer counter counts up using the internal count clock and the bit for the selected interval timer overflows, the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is set to "1".
Page 215: Timebase Timer Operation
CHAPTER 9 TIMEBASE TIMER Timebase Timer Operation The timebase timer has the interval timer function as well as the clock supplying function for some peripheral functions. ■ Operation of interval timer function (timebase timer) The interval timer function generates interrupt requests at any defined interval times. For its operation as an interval timer, the settings shown in Figure 9.5-1 are required.
Page 216 CHAPTER 9 TIMEBASE TIMER Table 9.5-1 Timebase timer counter clear operation and oscillation stabilization wait time. Counter TBOF Operation Oscillation stabilization wait time clear clear Writing "0" to timebase timer initializing bit (TBR) for timebase timer control register (TBTC) Power-on reset ✕...
Page 217 CHAPTER 9 TIMEBASE TIMER ■ Operation of timebase timer Operations in the following states are shown in Figure 9.5-2: • Where the power-on reset has occurred • Where transition to the sleep mode has occurred during processing for the interval timer function •...
Page 218: Notes On Using Timebase Timer
CHAPTER 9 TIMEBASE TIMER Notes on Using Timebase Timer This section explains notes on using the timebase timer, including the effects of clearing an interrupt request or clearing the timebase timer on peripheral functions. ■ Notes on using timebase timer ❍...
Page 219: Sample Programs Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Sample Programs of Timebase timer Sample programs for the timebase timer are shown below. ■ Sample programs of timebase timer ❍ Specifications for processing Repetitively generate an interval interrupt of 2 /HCLK (oscillation clock). The interval time in this case is approximately 1.0 ms (when operating at 4 MHz).
Page 220 CHAPTER 9 TIMEBASE TIMER...
Page 221: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER This chapter provides an overview of watchdog timer, explains control register, configuration, operations and shows the precautions on use, and sample program. 10.1 Overview of Watchdog Timer 10.2 Watchdog Timer Control Register (WDTC) 10.3 Watchdog Timer Configuration 10.4 Watchdog Timer Operation 10.5 Notes on Using Watchdog Timer 10.6 Sample Programs of Watchdog Timer...
Page 222: Overview Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses the output of the timebase timer or the watch timer as the count clock, and if it is not cleared within a certain period of time after startup, this timer resets the CPU.
Page 223: Watchdog Timer Control Register (Wdtc)
CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used for the start and clearing of the watchdog timer and the display of reset causes. ■ Watchdog timer control register (WDTC) Figure 10.2-1 shows the configuration of the watchdog timer control register (WDTC), and Table 10.2-1 explains the function of each bit in the WDTC register.
Page 224 CHAPTER 10 WATCHDOG TIMER Table 10.2-1 Function of bits in watchdog timer control register (WDTC) Bit name Function These are read-only bits that indicate reset causes. Each of these bits is bit7 PONR set to "1" when the corresponding reset cause has occurred. bit6 Reserved Reset cause...
Page 225: Watchdog Timer Configuration
CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Configuration The watchdog timer is composed of the following five blocks: • Count clock selector • Watchdog counter (2-bit counter) • Watchdog reset generation circuit • Counter clear control circuit • Watchdog timer control register (WDTC) ■...
Page 226 CHAPTER 10 WATCHDOG TIMER ❍ Watchdog reset generation circuit This circuit generates a reset signal for an overflow of the watchdog counter. ❍ Counter clear control circuit This circuit controls the clearing of the watchdog counter and the start and stop of the counter. ❍...
Page 227: Watchdog Timer Operation
CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operation The watchdog timer generates a watchdog reset for an overflow of the watchdog counter. ■ Operation of watchdog timer Figure 10.4-1 shows the settings required for operation of the watchdog timer. Figure 10.4-1 Watchdog timer settings Address bit15 bit8...
Page 228 CHAPTER 10 WATCHDOG TIMER Figure 10.4-2 Clearing timing and interval time of watchdog timer [Block diagram of watchdog timer] 2-bit counter frequency frequency Clock Reset circuit divide-by-2 divide-by-2 Reset signal selector circuit circuit Count permit and clear Count permit output circuit WTE bit [Minimum interval time] The WTE bit is cleared immediately before the count clock starts.
Page 229: Notes On Using Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.5 Notes on Using Watchdog Timer This section explains notes on using the watchdog timer. ■ Notes on using watchdog timer ❍ Stopping the watchdog timer The watchdog timer stops by all reset causes. ❍ Interval time Because the interval time uses the carry signals of the timebase timer as the count clock, the interval time of the watchdog timer may become longer than the specified time when the timebase timer is cleared.
Page 230: Sample Programs Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.6 Sample Programs of Watchdog Timer Sample programs for the watchdog timer are shown below. ■ Sample programs for watchdog timer ❍ Specifications for processing • Clears the watchdog timer once per loop of the main program. •...
Page 231: Chapter 11 Watch Timer
CHAPTER 11 WATCH TIMER This chapter provides an overview of the watch timer, explains the configuration and functions of its register, and the operation of the watch timer. 11.1 Overview of Watch Timer 11.2 Watch Timer Configuration 11.3 Watch Timer Control Register (WTC) 11.4 Watch Timer Operation...
Page 232: Overview Of Watch Timer
CHAPTER 11 WATCH TIMER 11.1 Overview of Watch Timer The watch timer is a 15-bit timer using the sub-clock. This timer can generate interval interrupts. Furthermore, depending on the setting, this timer can be used as the clock source for the watchdog timer. ■...
Page 233: Watch Timer Configuration
CHAPTER 11 WATCH TIMER 11.2 Watch Timer Configuration The watch timer is composed of four blocks that include the following: • Interval selector • Watch counter • Watch timer interrupt generating circuit • Watch timer control register (WTC) ■ Block diagram of watch timer Figure 11.2-1 is a block diagram of the watch timer.
Page 234: Watch Timer Control Register (Wtc)
CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) The watch timer control register (WTC) controls operation of the watch timer. This register also controls the time of interval interrupts. ■ Configuration of watch timer control register (WTC) Figure 11.3-1 shows the configuration of the watch timer control register (WTC), and Table 11.3-1 lists the functions of bits in the watch timer control register (WTC).
Page 235 CHAPTER 11 WATCH TIMER Table 11.3-1 Functions of bits in watch timer control register (WTC) Bit name Function This bit is for selecting the clock source for the watchdog timer. WDCS: • If set to "0", this bit specifies clock for the watch timer; if set to "1", it bit7 Watchdog timer clock specifies clock for the timebase timer.
Page 236: Watch Timer Operation
CHAPTER 11 WATCH TIMER 11.4 Watch Timer Operation The watch timer functions as a clock source for the watchdog timer, timer for the oscillation stabilization wait time of the sub-clock, and interval timer to generate interrupts at fixed intervals. ■ Watch counter The watch counter is composed of a 15-bit counter to count the sub-clock, and it always continues counting as long as the sub-clock is input.
Page 237 CHAPTER 11 WATCH TIMER ■ Clock source for watchdog timer specifying function The clock source for the watchdog timer can be specified with the watchdog timer clock source selection bit (WDCS) of the WTC register. If the sub-clock is used as the machine clock, set the WDCS bit to "0"...
Page 238 CHAPTER 11 WATCH TIMER...
Page 239: Chapter 12 16-Bit Input/Output Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER This chapter provides an overview of the 16-bit input/output timer, explains the configuration and functions of its registers, interrupt and its operation. 12.1 Overview of 16-bit Input/Output Timer 12.2 Configuration of 16-bit Input/Output Timer 12.3 Configuration and Function of 16-bit Input/Output Timer Register 12.4 Interrupt of 16-bit Input/Output Timer 12.5 16-bit Input/Output Timer Operation 12.6 Program Example of 16-bit Input/Output Timer...
Page 240: Overview Of 16-Bit Input/Output Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.1 Overview of 16-bit Input/Output Timer The 16-bit input/output timer consists of one free-running timer, six output compares, and two input captures. An output of six independent waveforms based on the free- running timer can be obtained, and measurement of input pulse widths and external clock intervals is enabled.
Page 241: Configuration Of 16-Bit Input/Output Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2 Configuration of 16-bit Input/Output Timer The 16-bit input/output timer consists of three modules for the free-running timer, output compare, and input capture. ■ Block diagram Figure 12.2-1 is a block diagram of the 16-bit input/output timer. Figure 12.2-1 Block diagram of 16-bit input/output timer Control logic Interrupt...
Page 242 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram of free-running timer Figure 12.2-2 is a block diagram of the free-running timer. Figure 12.2-2 Block diagram of free-running timer φ Interrupt request Prescaler STOP MODE SCLR CLK2 CLK1 CLK0 Clock Free-running timer Compare clear register Counter value output T15 to T00 Compare...
Page 243 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram of input capture Figure 12.2-4 is a block diagram of input capture. Figure 12.2-4 Block diagram of input capture Edge detect Capture data register 0 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Edge detect Capture data register 1...
Page 244 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram of pin related to 16-bit input/output timer Figure 12.2-5 Block diagram of pin related to 16-bit input/output timer Peripheral function output Peripheral (OUT0 to 5) function input (IN0/IN1) Peripheral function output enable Port data register (PDR) Open drain control signal (P46/P47 only)
Page 245: Configuration And Function Of 16-Bit Input/Output Timer Register
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3 Configuration and Function of 16-bit Input/Output Timer Register This section shows the configuration and functions of 16-bit input/output timer registers. ❍ Free-running timer Figure 12.3-1 Register configuration of free-running timer 000066/67 CPCLR Compare clear register 000062/63 TCDT Timer counter data register...
Page 246: Free-Running Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.1 Free-running timer This section shows the configuration and explains the functions of free-running timer registers. ■ List of free-running timer registers Figure 12.3-4 shows a list of the free-running timer registers. Figure 12.3-4 List of free-running timer registers CPCLR 000067 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08...
Page 247 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Timer counter data register (TCDT) Bit configuration of the timer counter data register (TCDT) is shown below. Figure 12.3-6 Bit configuration of timer counter data register (TCDT) TCDT 000063 Timer counter data register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 TCDT 000062...
Page 248 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [bit12, bit11, bit10] MSI2, MSI1, MSI0 These bits specify the count with which a compare clear interrupt is masked. It consists of 3- bit reload counter that reloads the count value every time the counter value reaches "000". During writing to this register, the count value is also loaded, where mask count = specified count (e.g., set to "010"...
Page 249 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [bit5] STOP This bit sets whether to enable or disable the counting by the free-running timer. If this bit is set to "1", the timer stops counting, and if it is set to "0", the timer starts counting. Count permit (operation) (initial value) Count prohibit (stop) If the free-running timer stops counting, the output compare operation also stops.
Page 250 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [bit2, bit1, bit0] CLK2, CLK1, CLK0 These bits select the count clock of the free-running timer. Since the clock changes after this bit is written, change the bit setting when output compare and input capture are in the stopped state.
Page 251: Output Compare
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.2 Output compare This section shows the configuration and explains the functions of registers for output compare. ■ List of output compare registers Figure 12.3-8 shows a list of the registers for output compare. Figure 12.3-8 Registers of output compare 00004B 00004D OCCP0 to 5...
Page 252 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Output compare register (OCCP0 to OCCP5) Output compare register (OCCP0 to OCCP5) has the bit configuration shown below. Figure 12.3-9 Bit configuration of output compare register (OCCP0 to OCCP5) ch.0 00004B 00004D OCCP0 to OCCP5 00004F C13 C12 Output compare register...
Page 253 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER • If CMOD = 1, compare register 0 (2/4) inverts the output level in the same manner as in cases where CMOD = 0; however, the pin OUT1 (OUT3/OUT5) output level corresponding to compare register 1 (3/5) inverts the output level only when both compare register 0 (2/4) and compare register 1 (3/5) have a match.
Page 254 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [bit5, bit4] ICE1, ICE0 These bits are the interrupt permit bits of output compare. If these bits are set to "1" and an interrupt flag (ICP1, ICP0) is set, an output compare interrupt occurs. Output compare interrupt prohibit (initial value) Output compare interrupt permit •...
Page 255: Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.3 Input capture This section describes the configuration and functions of the registers for the input capture. ■ List of input capture registers Figure 12.3-11 shows a list of the input capture registers. Figure 12.3-11 Input capture registers IPCP0, 1 ch0 00005D CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Input capture data register...
Page 256 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Input capture control status register (ICS01) The input capture control status register (ICS01) has the bit configuration shown below. Figure 12.3-13 Bit configuration of input capture control status register (ICS01) ICS01 000060 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Input capture control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 The input capture control status register (ICS01) consists of bits that have the functions...
Page 257: Interrupt Of 16-Bit Input/Output Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.4 Interrupt of 16-bit Input/Output Timer The interrupt request of the 16-bit input/output timer occurs for three following. • The counter value of the free-running timer overflows. • The trigger edge input to the input capture input pin is performed. •...
Page 258 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER request occurs. ● Output compare interrupt The interrupt operation when a match between the count value of the free-running timer and the setting value of the compare register is detected is shown as follows: • The output compare match flag in the control register is set to 1 (OCS:IOP=1). •...
Page 259: 16-Bit Input/Output Timer Operation
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5 16-bit Input/Output Timer Operation This section explains the operation and timing of the 16-bit input/output timer. ■ Operation and timing of 16-bit input/output timer The 16-bit input/output timer handles the operation and timing for the following items: •...
Page 260: Operation Of Free-Running Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.1 Operation of free-running timer This section explains the operation and timing of the free-running timer. ■ Operation of free-running timer The free-running timer starts counting at a counter value of "0000" after clearing reset operation. This counter value is used as a reference time for output compare and input capture.
Page 261 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER Figure 12.5-2 Timing chart of counter cleared because of compare results match Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare BFFF register value Interrupt...
Page 262: Operation Of Output Compare
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.2 Operation of output compare Output compare compares the specified compare register value with the free-running timer value, and if they match, it issues an interrupt request and reverses the output level. ■ Examples of output waveform Examples of output waveform are shown below.
Page 263 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ❍ Example of output waveform from two pairs of compare registers Figure 12.5-4 shows an example of output waveform where the initial value of output is specified as "0". Figure 12.5-4 Example of output waveform from two pairs of compare registers (initial value of output = 0) Counter value FFFF...
Page 264: Operation Of Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.3 Operation of input capture Input capture generates interrupt request by reading the free-running timer value into the capture register when the specified valid edge is detected. ■ Example of input capture timing Figure 12.5-5" shows an example of input capture timing. Figure 12.5-5 Example of input capture timing Counter value FFFF...
Page 265: Free-Running Timer Timing
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.4 Free-running timer timing The free-running timer is incremented according to the timing of input clock (internal or external clock). If an external clock is selected, counting is performed at the rising edge. ■ Count timing of free-running timer Figure 12.5-6 shows the count timing of the free-running timer.
Page 266: Output Compare Timing
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.5 Output compare timing The output compare is used to issue compare match signals when the free-running timer and the compare register have matching values, to reverse the output value, and to generate interrupts. Output reverse timing at the compare match is in sync with the counter timing.
Page 267: Timing Of Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.5.6 Timing of input capture This section describes a capture timing of the input signal for input capture. ■ Capture timing to input signal Figure 12.5-10 shows the capture timing of input signal for input capture. Figure 12.5-10 Capture timing of input signal for input capture φ...
Page 268: Program Example Of 16-Bit Input/Output Timer
Note: Note: Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt.
Page 269 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Setting method other than program example ● Type of internal clock and selection method There are eight internal clocks and they are set by the clock selection bit (TCCS.ECKE) and count clock bit (TCCS.CLK[2:0]). Setting Count cycle Internal clock...
Page 270 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER • Reset The free-running timer is cleared by reset (external reset, watchdog reset, software reset). • Set "0000 " to timer counter data register (TCDT) When "0000 " is written to the timer counter data register (TCDT) during operation of the free-running timer is stopped, the count value is cleared to "0000 ".
Page 271 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Program example of output compare Example of setting procedure Program example void OUTPUT01_sample(void) 2-channel independent output compare operation (7FFFF, BFFFF), interrupt generation, no compare freerun_initial(); clear OUTPUT01_initial(); OUTPUT01_start(); freerun_start(); <Initial setting> void freerun_initial(void) • Control free-running timer IO_TCCS.word = 0x0020;...
Page 272 Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR F value) are required in advance. See the chapter of 16LX FAMILY MB90480 SERIES". clock and interrupt. ■...
Page 273 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER • OUT4 output reverses output by a match with comparison result between free-running timer and compare register 4. ● Method to enable/disable compare operation Set by compare operation bit (OCS01. CST[1:0], OCS23. CST[1:0], OCS45. CST[1:0]). Operation Compare Compare operation enable bit...
Page 274 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ● Method to set compare pin OUT0-OUT5 to output Set by port function register (OCS01.OTE[1:0], OCS23.OTE[1:0], OCS45.OTE[1:0]). Operation Port function bit To set compare 0 pin (OUT0) to output Set (OCS01.OTE0) to "1" To set compare 1 pin (OUT1) to output Set (OCS01.OTE1) to "1"...
Page 275 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ● Interrupt related register The relationship between channel, interrupt level, and interrupt vector is shown in the following table. For details on the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT". Channel Interrupt vector Interrupt level setting register Interrupt level register (ICR08) Output compare 0...
Page 276 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ● Calculation method of compare value • Toggle output pulse (Example) Cycle : A, method to output 2-phase pulse of 1/4 phase difference Phase difference1/4 Formula : Compare 0 value = (A/2)/ count clock Compare 1 value = (A/4)/ count clock (Count clock : time set by free-running timer) Note: Setting to clear the free-running timer 0 by a match of compare 0...
Page 277 Note: Note: Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt.
Page 278 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Setting methods other than program example ● Type of external input valid edge polarity and selection method The valid edge polarity has rising edge, falling edge, and both edges. Set by the valid edge polarity bit of external input (ICS01.EG[01:00], ICS01.EG[11:10]). Valid edge polarity bit of external input Operation (EG[01:00], EG[11:10])
Page 279 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ● Method to enable interrupt Enabling the interrupt sets using the interrupt request enable bit (ICS01.ICE0, ICS01.ICE1). Interrupt request enable bit (ICE0, ICE1) Disable interrupt Set to "0" Enable interrupt Set to "1" Clearing the interrupt request set using the interrupt request bit ( ICS01.ICP0, ICS01.ICP1). Interrupt request bit (ICP0, ICP1) Clear interrupt request Write "0"...
Page 280 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER...
Page 281: Chapter 13 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER This chapter provides an overview of the 8/16-bit up/down counter/timer, explains the configuration and functions of its registers, interrupt and its operation. 13.1 Overview of 8/16-bit Up/Down Counter Timer 13.2 Configuration of 8/16-bit Up/Down Counter/Timer 13.3 Configuration and Functions of Registers for 8/16-bit Up/Down Counter/Timer 13.4 Interrupt of 8/16-bit Up/Down Counter/Timer 13.5 8/16-bit Up/Down Counter/Timer Operation...
Page 282: Overview Of 8/16-Bit Up/Down Counter Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.1 Overview of 8/16-bit Up/Down Counter Timer The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counter registers, two 8-bit reload/compare registers, and their control circuits. ■ Major functions of 8/16-bit up/down counter/timer •...
Page 283: Configuration Of 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2 Configuration of 8/16-bit Up/Down Counter/Timer The 8-bit up/down counter/timer has two channels and consists of three event input pins, one 8-bit up/down count, and one 8-bit reload/compare register per channel. Also, one of two 8-bit up/down counter/timer channels can be used as the 16-bit up/ down counter/timer.
Page 284 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.2-2 Block diagram of 8/16-bit up/down counter/timer (channel 1) Data bus 8 bits CGE1 CGE0 CGSC RCR1 (reload/compare register 1) Reload Edge/level ZIN1 CTUT detected control UCRE RLDE UDCC Counter clear 8 bits UDCR1 (up/down count register 1) CMPF UDFF OVFF CMS1 CMS0 CES1 CES0 M16E UDMS...
Page 285 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Block diagram of pin related to 8/16-bit up/down counter/timer Figure 13.2-3 Block diagram of pin related to 8/16-bit up/down counter/timer Peripheral function input (AIN0/BIN0/ZIN0 AIN1/BIN1/ZIN1) Port data register (PDR) PDR Read P-ch Output latch PDR Write Port direction register (DDR) Direction latch...
Page 286: Configuration And Functions Of Registers For 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3 Configuration and Functions of Registers for 8/16-bit Up/ Down Counter/Timer This section shows the configuration and explains the function of the 8/16-bit up/down counter/timer registers. ■ List of 8/16-bit up/down counter/timer registers Figure 13.3-1 shows a list of registers for the 8/16-bit up/down counter/timer. Figure 13.3-1 List of registers for 8/16-bit up/down counter/timer UDCR1 UDCR 0...
Page 287: Counter Control Register (Ch.0) Upper (Ccrh0)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.1 Counter control register (ch.0) upper (CCRH0) This section shows the configuration and explains the functions of counter control register (ch.0) upper (CCRH0). ■ Counter control register (ch.0) upper (CCRH0) The bit configuration of counter control register (ch.0) upper (CCRH0) is shown below. Figure 13.3-2 Bit configuration of counter control register (ch.0) upper (CCRH0) Initial value CCRH0...
Page 288 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER CFIE Direction reversal interrupt output Direction reversal interrupt output prohibit (initial value) Direction reversal interrupt output permit [bit12] CLKS (built-in prescaler selection) This bit is used to select the frequency of built-in prescaler in the selection of the timer mode. It is only valid in the timer mode, and only decrementing (down count) is permitted.
Page 289: Counter Control Register (Ch.1) Upper (Ccrh1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.2 Counter control register (ch.1) upper (CCRH1) This section describes the configuration and explains the function of counter control register (ch.1) upper (CCRH1). ■ Counter control register (ch.1) upper (CCRH1) The bit configuration of the counter control register (ch.1) upper (CCRH1) is shown below. Figure 13.3-3 Bit configuration of counter control register (ch.1) upper (CCRH1) Initial value CCRH1...
Page 290 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [bit12] CLKS (built-in prescaler selection) This bit is used to select the frequency of built-in prescaler when the timer mode is selected. This is only valid in the timer mode, where only decrementing is permitted. CLKS Selection internal clock 2 machine cycles (initial value)
Page 291: Counter Control Register (Ch.0/Ch.1) Lower (Ccrl0/Ccrl1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.3 Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) This section describes the configuration and explains the function of counter control register (ch.0/ch.1) lower (CCRL0/CCRL1). ■ Counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) The bit configuration of counter control register (ch.0/ch.1) lower (CCRL0/CCRL1) is shown below.
Page 292 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [bit5] UCRE (UDCR clear enable) This bit is used to control UDCR clear caused by compare. This does not affect the UDCR clear function (such as caused by the ZIN pin setting) other than clear because of compare generation. UCRE Counter clear caused by compare Counter clear prohibit (initial value)
Page 293: Counter Status Register 0/1 (Csr0/Csr1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.4 Counter status register 0/1 (CSR0/CSR1) This section describes the configuration and explains the function of counter status register 0/1 (CSR0/CSR1). ■ Counter status register 0/1 (CSR0/CSR1) The bit configuration of the counter status register 0/1 (CSR0/CSR1) is shown below. Figure 13.3-5 Bit configuration of counter status register 0/1(CSR0/CSR1) Initial value CSR0...
Page 294 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [bit4] CMPF (compare detect flag) This bit is a flag indicating that the UDCR and RCR values match each other after a comparison. The initialization (writing "0") is only permitted. Read-modify-write type instructions read "1" irrespective of bit values. CMPF Match/no match at compare detection No match in compare results (initial value)
Page 295: Up/Down Count Register (Ch.0/Ch.1) (Udcr0/Udcr1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.5 Up/down count register (ch.0/ch.1) (UDCR0/UDCR1) This section describes the configuration and explains the function of up/down count register (ch.0/ch.1) (UDCR0/UDCR1). ■ Up/down count register (ch.0/ch.1) (UDCR0/UDCR1) The bit configuration of the up/down count register (ch.0/ch.1) (UDCR0/UDCR1) is shown below.
Page 296: Reload/Compare Register (Ch.0/Ch.1) (Rcr0/Rcr1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.6 Reload/compare register (ch.0/ch.1) (RCR0/RCR1) This section describes the configuration and explains the function of reload/compare register (ch.0/ch.1) (RCR0/RCR1). ■ Reload/compare register (ch.0/ch.1) (RCR0/RCR1) Reload/compare register (ch.0/ch.1) (RCR0/RCR1) has the bit configuration shown below. Figure 13.3-7 Bit configuration of reload/compare register (ch.0/ch.1) (RCR0/RCR1) Initial value RCR1 ch.1 Address: 00006B...
Page 297: Interrupt Of 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.4 Interrupt of 8/16-bit Up/Down Counter/Timer The interrupt of the 8/16-bit up/down counter/timer occurs when the count direction is changed only once during count start, when an match of comparison result is detected, or when the overflow/underflow occurs. The DMA transfer and extended intelligent I/O service (EI OS) cannot be activated for the interrupt of the 8/16-bit up/down counter/timer.
Page 298 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Interrupt of 8/16-bit up/down counter/timer, DMA transfer, and EI Table 13.4-2 shows the relationship between the interrupt source, interrupt vector, and interrupt control register other than software interrupt. Table 13.4-2 Interrupt source, interrupt vector, and interrupt control register μDMAC Interrupt vector Interrupt control register...
Page 299: 8/16-Bit Up/Down Counter/Timer Operation
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.5 8/16-bit Up/Down Counter/Timer Operation This section explains different count modes in the 8/16-bit up/down counter/timer and the operation of the reload/compare function. ■ Selection of count mode The 8/16-bit up/down counter/timer has four types of count modes. These count modes are selected by CCRH: CMS1 or CMS0.
Page 300 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER In the mode at frequency multiplied by 2, at the timing of both the rising and falling edges of the BIN pin, counting is done as required by checking for the AIN pin value. Count operations in this case are as follows: •...
Page 301 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.5-2 Outline of phase difference count mode (at frequency multiplied by 4) operation AIN pin BIN pin +1 +1 -1 -1 -1 -1 Count value 0 In counting the encoder output, the input condition must be arranged by defining the relationship between the phases and pins shown below.
Page 302: Reload/Compare Function
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.5.1 Reload/compare function The 8/16-bit up/down counter/timer has reload and compare functions. These two functions may be mixed for processing. ■ Selection of reload and compare functions Table 13.5-3 shows an example of selecting reload and compare functions. Table 13.5-3 Selection example of reload/compare function RLDE, UCRE Reload and compare functions...
Page 303 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Compare function The compare function is available in any modes other than the timer mode. If RCR and UDCR values match at the start of the compare function, CMPF is specified and an interrupt request occurs.
Page 304 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ❍ If reload or clear events are generated in a count operation All updating operations of UDCR are in sync with the count clock. Figure 13.5-6 shows an example of reloading 080 Figure 13.5-6 Normal operation counting UDCR ↓...
Page 305: Writing Data To Up/Down Count Register (Udcr)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.5.2 Writing data to up/down count register (UDCR) Writing data directly to UDCR from a data bus is not permitted. This section includes procedures for writing any data to UDCR. ■ Writing data to UDCR Data can be written to UDCR with the following procedures: 1.
Page 306 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Count direction flag, count direction reversal flag The count direction flag (UDF1, UDF0) indicates whether the last count operation was either an up-count or down-count when an up- or down-count was performed. By evaluating the count clock generated by input of both the AIN and BIN pins, a flag is updated at every count operation.
Page 307: Program Example Of 8/16-Bit Up/Down Counter/Timer
Note: Note: Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt.
Page 308 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Setting method other than program example ● Method to select 8-bit or 16-bit operation Set by the 16-bit mode enable setting bit (CCR0.M16E). Bit length of up/down counter 16-bit mode enable setting bit (M16E) To set to 8-bit Set to "0"...
Page 309 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ● Method to set the value to up/down counter The value can be set to the up/down counter when "1" is written to the counter write bit (CCR0.CTUT, CCR1.CTUT) after the value is written to the reload/compare register (RCR). ●...
Page 310 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ● Method to clear up/down counter by ZIN pin Set by the counter clear gate bit (CCR0.CGSC, CCR1.CGSC) and counter clear gate edge selection bits (CCR0.CGE[1:0], CCR1.CGE[1:0]). (valid for all count modes). Counter clear gate bit Counter clear gate edge ZIN pin input (CGSC)
Page 311 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ● Method to know the previous count direction (method to know the current rotation direction) Set by the up/down flag (CSR0.UDF[1:0], CSR1.UDF[1:0]) . Setting Up/down flag (UDF[1:0]) "00 " No count after a reset "01 "...
Page 312 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ● Method to set reload value and compare value Set the value to the reload/compare registers (RCR0, RCR1) (same value is set for compare value and reload value). ● Interrupt related register The relationship between the up/down counter number, interrupt level, and interrupt vector is shown in the following table.
Page 313: Chapter 14 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER This chapter provides an overview of the 16-bit reload timer, explains the configuration and functions of its registers, interrupt and its operation. 14.1 Overview of 16-Bit Reload Timer 14.2 Configuration and Functions of 16-Bit Reload Timer Registers 14.3 Interrupt of 16-Bit Reload Timer 14.4 Operations of the 16-Bit Reload Timer 14.5 Program Example of 16-Bit Reload Timer...
Page 314: Overview Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of 16-Bit Reload Timer The 16-bit reload timer has the following functions: • Clock mode can be selected from the internal clock mode and event count mode. • When an underflow of 16-bit timer register (TMR) occurs, the count operation can be selected either the one-shot mode that stops the operation or the reload mode that continues its operation by reloading count setting value.
Page 315 CHAPTER 14 16-BIT RELOAD TIMER ■ Counter operation modes ❍ Reload mode " → "FFFF If countdown causes an underflow("0000 "), the specified count value is reloaded to continue with counting. An underflow can generate an interrupt request that can then be used as an interval timer.
Page 316 CHAPTER 14 16-BIT RELOAD TIMER ■ Block diagram of the 16-bit reload timer Figure 14.1-1 Block diagram of the 16-bit reload timer Internal data bus TMRLR 16-bit reload register Reload signal Reload control circuit 16-bit timer register (down-counter) UF Count clock generation circuit Gate Machine Wait signal...
Page 317 CHAPTER 14 16-BIT RELOAD TIMER ■ Block diagram of pin related to 16-bit reload timer Figure 14.1-2 Block diagram of pin related to 16-bit reload timer Peripheral function Peripheral function input (TIN0) output (TOT0) Peripheral function output enable Port data register (PDR) Open drain control signal (P73/74) PDR Read...
Page 318: Configuration And Functions Of 16-Bit Reload Timer Registers
CHAPTER 14 16-BIT RELOAD TIMER 14.2 Configuration and Functions of 16-Bit Reload Timer Registers This section describes the configuration and functions of the registers used in the 16- bit reload timer. ■ List of registers Figure 14.2-1 shows the list of the registers of the 16-bit reload timer. Figure 14.2-1 16-bit reload timer registers TMCSR 0000CB...
Page 319: Timer Control Status Register (Tmcsr)
CHAPTER 14 16-BIT RELOAD TIMER 14.2.1 Timer Control Status Register (TMCSR) This section describes the configuration and functions of the timer control status register (TMCSR). ■ Timer control status register (TMCSR) The timer control status register (TMCSR) is used to control the operation mode and interrupts of the16-bit reload timer.
Page 320 CHAPTER 14 16-BIT RELOAD TIMER Table 14.2-1 Internal clock mode (CLS1/0 = 00 , 01 , or 10 MOD2 MOD1 MOD0 Input pin function Active edge or level Trigger invalid Initial value Rising edge Trigger input Falling edge Both edges "L"...
Page 321 CHAPTER 14 16-BIT RELOAD TIMER [bit4] RELD (Reload operation enable) This bit enables reload operation. With RELD set to "1", the timer operates in reload mode. In this mode, the timer loads the reload register data into the counter and continues counting even if an underflow occurs.
Page 322 CHAPTER 14 16-BIT RELOAD TIMER [bit1] CNTE (Timer counter enable) This bit enables the timer counter. CNTE Function Counter operation stopped (initial value) Counter operation allowed (start trigger wait) [bit0] TRG (Software trigger) This bit operates as a software trigger bit. With TRG set to "1", a software trigger is applied, data from the timer reload register is loaded into the counter and counting starts.
Page 323: 16-Bit Timer Register (Tmr)/16-Bit Reload Register (Tmrlr)
CHAPTER 14 16-BIT RELOAD TIMER 14.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) This section describes the configuration and functions of the 16-bit timer register (TMR)/16-bit reload register (TMRLR). ■ 16-bit timer register (TMR)/16-bit reload register (TMRLR) The bit configuration of the 16-bit timer register (TMR)/16-bit reload register (TMRLR) is shown below.
Page 324 CHAPTER 14 16-BIT RELOAD TIMER ■ 16-bit reload register (TMRLR) The 16-bit reload register sets the initial counter value while count operation is disabled (TMCSR: CNTE=0). When the counter is started by enabling counter operation (TMCSR: CNTE=1), the count-down will start from the value that was written to this register. The value set in this register is reloaded to the counter in reload mode if an underflow occurs, and count-down continues.
Page 325: Interrupt Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.3 Interrupt of 16-Bit Reload Timer The interrupt of the 16-bit reload timer occurs when underflow of the counter is detected. The underflow interrupt of counter can activate the DMA transfer and extended intelligent I/O service (EI OS).
Page 326: Operations Of The 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.4 Operations of the 16-Bit Reload Timer This section describes the settings of the 16-bit reload timer. ■ Settings of the 16-bit reload timer ❍ Settings for internal clock mode For interval timer operation, the settings shown in Figure 14.4-1 are required. Figure 14.4-1 Settings of internal clock mode TMCSR CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE...
Page 327: State Transitions During Count Operation
CHAPTER 14 16-BIT RELOAD TIMER 14.4.1 State Transitions During Count Operation This section describes the state transitions during count operation. ■ State transitions during count operation Figure 14.4-3 State transition during counter operation STOP state CNTE=1, WAIT=1 Reset TIN pin: Input disabled TOT pin: General-purpose port Counter: Retains the value at stop.
Page 328: Operations Of Internal Clock Mode (Reload Mode)
CHAPTER 14 16-BIT RELOAD TIMER 14.4.2 Operations of Internal Clock Mode (Reload Mode) The counter operates in sync with the internal count clock to count down the 16-bit counter and generate an interrupt request to the CPU in case of counter underflow. The counter also outputs a toggle waveform from the timer output pin.
Page 329 CHAPTER 14 16-BIT RELOAD TIMER ❍ External trigger operation The counter is started if a valid edge (rising, falling, or both edges can be selected) is input to the TIN pin. Figure 14.4-5 shows the external trigger operation in reload mode. Figure 14.4-5 Count operation in reload mode (external trigger operation) Count clock Reload...
Page 330: Internal Clock Mode (One-Shot Mode)
CHAPTER 14 16-BIT RELOAD TIMER 14.4.3 Internal Clock Mode (One-Shot Mode) The counter is in synchronization with the internal count clock in this mode to count down the 16-bit counter and generate an interrupt request to the CPU at counter underflow.
Page 331 CHAPTER 14 16-BIT RELOAD TIMER ❍ External trigger operation When a valid edge (leading, trailing, or both can be selected) is input to the TIN pins, the counter is started. Figure 14.4-8 shows the external trigger operation in one-shot mode. Figure 14.4-8 Count operation in one-shot mode (external trigger operation) Count clock Reload...
Page 332: Event Count Mode
CHAPTER 14 16-BIT RELOAD TIMER 14.4.4 Event Count Mode The counter counts input edges from the TIN pin to count down the 16-bit counter and generate an interrupt request to the CPU when a counter underflow occurs. The TOT pin can output either a toggle waveform or a square wave. ■...
Page 333 CHAPTER 14 16-BIT RELOAD TIMER ❍ Operation in one-shot mode " → "FFFF If the counter value causes an underflow ("0000 "), the counter stops at "FFFF ". In this case, the timer interrupt request flag (UF) is set to "1". If the interrupt request enable bit (INTE) is set to "1", an interrupt request occurs.
Page 334: Program Example Of 16-Bit Reload Timer
Note: Note: Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt.
Page 335 CHAPTER 14 16-BIT RELOAD TIMER ■ Setting method other than program example ● Method to set (rewrite) reload value The reload value is set to the 16-bit reload register (TMRLR). The following shows the calculation formula of the set value. <Formula>...
Page 336 CHAPTER 14 16-BIT RELOAD TIMER ● Method to reverse output level The output level is shown in the following table. Set by the timer output level bit (TMCSR.OUTL). Output level Timer output level bit (OUTL) Reload mode, "L" level output of initial value Set to "0"...
Page 337 CHAPTER 14 16-BIT RELOAD TIMER ● Types of valid edge in event count mode and selection method Set by the trigger selection bits (TMCSR.MOD[1:0]). Three valid edges are provided. Valid edge Trigger selection bits (MOD1, MOD0) Rising edge Set to "01 "...
Page 338 CHAPTER 14 16-BIT RELOAD TIMER ● Interrupt related register The relationship among the reload timer number, interrupt level, and interrupt vector, and inter- rupt control register is shown below. For details of the interrupt level and interrupt vector, see CHAPTER 3 INTERRUPT. Interrupt vector Interrupt level setting register Reload timer...
Page 339: Chapter 15 8/16-Bit Ppg Timer
CHAPTER 15 8/16-BIT PPG TIMER This chapter provides an overview of the 8/16-bit PPG timer, explains the configuration and functions of its registers interrupt and its operation. 15.1 Overview of 8/16-Bit PPG Timer 15.2 Configuration of 8/16-Bit PPG Timer 15.3 Configuration and Functions of 8/16-Bit PPG Timer Registers 15.4 Interrupt of 8/16-Bit PPG Timer 15.5 Operations of 8/16-Bit PPG Timer 15.6 Program Example of 8/16-Bit PPG Timer...
Page 340: Overview Of 8/16-Bit Ppg Timer
CHAPTER 15 8/16-BIT PPG TIMER 15.1 Overview of 8/16-Bit PPG Timer The 8/16-bit PPG timer is a 6-channel reload timer module that can be used any interval and output pulse of duty ratio. On the hardware level, the timer consists of six 8-bit decrement counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins and six interrupt outputs.
Page 341: Configuration Of 8/16-Bit Ppg Timer
CHAPTER 15 8/16-BIT PPG TIMER 15.2 Configuration of 8/16-Bit PPG Timer This section shows the configuration of channels 0/2/4 and channels 1/3/5 of the 8/16- bit PPG timer. ■ Block diagram of the 8/16-bit PPG timer Figure 15.2-1 shows a block diagram of channels 0, 2, and 4. Figure 15.2-2 shows a block diagram of channels 1, 3, and 5.
Page 342 CHAPTER 15 8/16-BIT PPG TIMER Figure 15.2-2 Block diagram of the 8/16-bit PPG timer (channels 1/3/5) PPG1/3/5 output enable Peripheral clock: divide-by-16 Peripheral clock: divide-by-8 PPG1/3/5 Peripheral clock: divide-by-4 Peripheral clock: divide-by-2 UART0 Peripheral clock PPG1/3/5 output latch PEN1 PCNT (down-counter) "L"/"H"...
Page 343 CHAPTER 15 8/16-BIT PPG TIMER ■ Block diagram of pin related to 8/16-bit PPG timer Figure 15.2-3 Block diagram of pin related to 8/16-bit PPG timer Peripheral function output (PPG0 to 5) Peripheral function output enable Port data register (PDR) Read P-ch Output latch...
Page 344: Configuration And Functions Of 8/16-Bit Ppg Timer Registers
CHAPTER 15 8/16-BIT PPG TIMER 15.3 Configuration and Functions of 8/16-Bit PPG Timer Registers This section describes the configuration and functions of the registers used in the 8/16-bit PPG timer. ■ List of 8/16-bit PPG timer registers Figure 15.3-1 shows a list of the registers for the 8/16-bit PPG timer. Figure 15.3-1 List of 8/16-bit PPG timer registers PPGC0/PPGC2/PPGC4 ch.0 00003A...
Page 345: Ppg0/2/4 Operation Mode Control Register (Ppgc0/Ppgc2/Ppgc4)
CHAPTER 15 8/16-BIT PPG TIMER 15.3.1 PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) This section describes the configuration and functions of the PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4). ■ PPG0/2/4 operation mode control register (PPGC0/PPGC2/PPGC4) The PPG0/PPG2PPG/4 operation mode control register (PPGC0/PPGC2/PPGC4) is used to select the channel 0/2/4 operation mode, control the pin output, select the count clock, and control the trigger.
Page 346 CHAPTER 15 8/16-BIT PPG TIMER [bit4] PIE0:ppg Interrupt Enable (PPG interrupt enable) This bit is used to prohibit/allow PPG interrupts. PIE0 Operation state Interrupts prohibited Interrupts allowed • If PUF0 is changed to "1" while this bit is "1", an interrupt request occurs. If this bit is "0", no interrupt generates.
Page 347: Ppg1/3/5 Operation Mode Control Register (Ppgc1/Ppgc3/Ppgc5)
CHAPTER 15 8/16-BIT PPG TIMER 15.3.2 PPG1/3/5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) This section describes the configuration and functions of the PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5). ■ PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) The PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) is used to select the channel 1/3/5 operation mode, control pin output, and select the count clock.
Page 348 CHAPTER 15 8/16-BIT PPG TIMER [bit12] PIE1: ppg Interrupt Enable (PPG interrupt enable) This bit is used to prohibit/allow PPG interrupts. PIE1 Operation state Interrupts prohibited Interrupts allowed If PUF0 is set to "1" when this bit is"1", an interrupt request occurs. When this bit is "0", no interrupt generates.
Page 349 CHAPTER 15 8/16-BIT PPG TIMER Notes: • Do not set these bits to "10 ". • To set these bits to "01 ", do not set the PEN0 bit of PPGC0 and the PEN1 bit of PPGC1 to "01 ". It is recommended that the PEN0 bit and the corresponding PEN1 bit be set to "11 "...
Page 350: Ppg0 To Ppg5 Output Control Registers (Ppg01, Ppg23, Ppg45)
CHAPTER 15 8/16-BIT PPG TIMER 15.3.3 PPG0 to PPG5 Output Control Registers (PPG01, PPG23, PPG45) This section describes the configuration and functions of the PPG0 to PPG5 output control registers (PPG01, PPG23, PPG45). ■ PPG0 to PPG5 output control registers (PPG01, PPG23, PPG45) The bit configuration of the PPG0 to 5 output control registers (PPG01, PPG23, PPG45) is described below.
Page 351 CHAPTER 15 8/16-BIT PPG TIMER [bit4, bit3, bit2] PCM2 to 0: ppg Count Mode (count clock selection) These bits are used to select the operation clock for the down counter of channels 0, 2, and PCM2 PCM1 PCM0 Operation mode Peripheral clock (62.5 ns machine clock for 16 MHz) Peripheral clock/2 (125 ns machine clock for 16 MHz) Peripheral clock/4 (250 ns machine clock for 16 MHz)
Page 352: Reload Registers (Prll0 To Prll5, Prlh0 To Prlh5)
CHAPTER 15 8/16-BIT PPG TIMER 15.3.4 Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) This section describes the configuration and functions of the reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5). ■ Reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) The bit configuration of the reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) is shown below.
Page 353: Interrupt Of 8/16-Bit Ppg Timer
CHAPTER 15 8/16-BIT PPG TIMER 15.4 Interrupt of 8/16-Bit PPG Timer The interrupt of the 8/16-bit PPG timer occurs when the PPG counter underflow is detected. The interrupt of the PPG counter underflow cannot activate the DMA transfer and extended intelligent I/O service (EI OS).
Page 354 CHAPTER 15 8/16-BIT PPG TIMER ■ Interrupt of 8/16-bit PPG timer, DMA transfer, and EI Table 15.4-2 shows the relationship between the interrupt source, interrupt vector, and interrupt control register other than software interrupt. Table 15.4-2 Interrupt source, interrupt vector, and interrupt control register μDMAC Interrupt vector Interrupt control register...
Page 355: Operations Of 8/16-Bit Ppg Timer
CHAPTER 15 8/16-BIT PPG TIMER 15.5 Operations of 8/16-Bit PPG Timer The 8/16-bit PPG timer contains an 8-bit PPG unit for six channels (PPG0/PPG1, PPG2/ PPG3, PPG4/PPG5). In addition to independent operation mode, the channels can also be used in direct connection mode (PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5). In total, three types of operation modes are therefore supported: independent operation mode, 8-bit prescaler + 8-bit PPG mode and 16-bit PPG mode.
Page 356 CHAPTER 15 8/16-BIT PPG TIMER ■ PPG output operation For the 8/16-bit PPG timer, PPG operation of channel 0 (channel 2 or channel 4) is started by setting bit7 of the PPGC0 register (PEN0) to "1". Similarly, PPG operation of channel 1 (channel 3 or channel 5) is started by setting bit15 of the PPGC1 register (PEN1) to "1"...
Page 357 CHAPTER 15 8/16-BIT PPG TIMER ■ Selection of count clock The 8/16-bit PPG timer uses the input from the peripheral clock and timebase counter as a counter clock, allowing a selection from six types of count clock input. Bit4 to bit2 of the PPG01/PPG23/PPG45 registers (PCM2 to 0) are used to select the clock of channel 0 (channel 2 or channel 4), and bit7 to bit5 of the PPG01/PPG23/PPG45 registers (PCS2 to PCS0) are used to select the clock of channel 1 (channel 3, or channel5).
Page 358 CHAPTER 15 8/16-BIT PPG TIMER Figure 15.5-2 Waveform in 8-bit prescaler + 8-bit PPG mode output operation PPG0 PPG1 The pulse width shown in Figure 15.5-2 can be expressed with the following formulas. 0 = T ✕ (L0 + 1) 0 = T ✕...
Page 359 CHAPTER 15 8/16-BIT PPG TIMER ■ Initial value of hardware components The hardware components of the 8/16-bit PPG timer are initialized to the following values at reset. → 0X000001 < Registers > PPG0 → 00000001 PPG1 PPG01 → XXXXXX00 → "L" <...
Page 360: Program Example Of 8/16-Bit Ppg Timer
Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt. *1: io_PPG01 represents PPG1 register and PPG0 register.
Page 361 CHAPTER 15 8/16-BIT PPG TIMER ■ Setting method other than program example ● Method to enable/stop PPG operation Set by the PPG operation enable bit (PPG01/PPG23/PPG45.PEN0 or 1). Control PPG operation enable bit (PEN0 or PEN1) To stop PPG operation Set to "0"...
Page 362 CHAPTER 15 8/16-BIT PPG TIMER ● Method to enable/disable/clear interrupt Enabling/disabling interrupt is set by the interrupt request enable bit (PPG01/PPG23/PPG45. PIE0 or PIE1). Content of control Interrupt request enable bit (PIE0 or PIE1) To disable interrupt request Set to "0" To enable interrupt request Set to "1"...
Page 363: Chapter 16 Dtp/External Interrupts
CHAPTER 16 DTP/EXTERNAL INTERRUPTS This chapter provides an overview of the DTP/external interrupt unit, explains configuration and functions of its registers and its operation, shows the precautions on use. 16.1 Overview of DTP/External Interrupt Unit 16.2 Configuration and Functions of DTP/External Interrupt Unit Registers 16.3 DTP/External Interrupt 16.4 Operations of DTP/External Interrupt Unit 16.5 Precautions on Use of DTP/External Interrupt Unit...
Page 364: Overview Of Dtp/External Interrupt Unit
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.1 Overview of DTP/External Interrupt Unit The DTP (Data Transfer Peripheral) unit is a peripheral control section located between the peripheral units outside the device and the F MC-16LX CPU. It is used to receive DMA request or interrupt requests from the external peripheral device and report such MC-16LX CPU to start μDMAC, EI requests to the F OS, or interrupt handling.
Page 365 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ Block diagram of pin related to DTP/external interrupt Figure 16.1-2 Block diagram of pin related to DTP/external interrupt Peripheral function output (IRQ0/IRQ1/IRQ2/IRQ3/IRQ4/IRQ5/IRQ6/IRQ7) Port data register (PDR) PDR Read P-ch Output latch PDR Write Port direction register (DDR) Direction latch N-ch...
Page 366: Configuration And Functions Of Dtp/External Interrupt Unit Registers
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.2 Configuration and Functions of DTP/External Interrupt Unit Registers This section describes the configuration and functions of the registers used in the DTP/external interrupt unit. ■ List of registers for DTP/external interrupt unit Figure 16.2-1 shows a list of the registers for the DTP/external interrupt unit. Figure 16.2-1 List of DTP/external interrupt unit registers Address: 00000C EN5 EN4 EN3...
Page 367 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ Interrupt/DTP source register (EIRR: External interrupt request register) The bit configuration of the interrupt/DTP source register (EIRR) is shown below. Initial value EIRR Address: 00000D ER5 ER4 ER3 ER1 ER0 XXXXXXXX R/W R/W R/W R/W R/W The interrupt/DTP source register (EIRR) is set to "1"...
Page 368: Dtp/External Interrupt
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.3 DTP/External Interrupt The interrupt related to the DTP/external interrupt occurs when the edge or level input to input pin is detected. The DTP/external interrupt can activate the DMA transfer and extended intelligent I/O service (EI OS).
Page 369 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ❍ Selecting of DTP function or external interrupt function Whether the DTP function or the external interrupt function is executed depends on the setting of the EI OS enable bit in the corresponding interrupt control register (ICR:ISE) or that of the DMA enable register (DER:EN).
Page 370: Operations Of Dtp/External Interrupt Unit
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.4 Operations of DTP/External Interrupt Unit This section describes the operations of the DTP/external interrupt unit. ■ Operation of external interrupt unit If, after an external interrupt request has been set, the interrupt request specified in the ELVR register is input to the corresponding pin, this resource will generate an interrupt request signal for the interrupt controller.
Page 371 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ DTP operation To start μDMAC in a user program, the following initialization operations are performed: The I/O address pointer in the μDMAC descriptor is set to the register address allocated in 000000 0000FF , and the buffer address pointer is set to the start address of the memory buffer. The operational sequence for DTP is almost the same as that for external interrupts.
Page 372: Precautions On Use Of Dtp/External Interrupt Unit
CHAPTER 16 DTP/EXTERNAL INTERRUPTS 16.5 Precautions on Use of DTP/External Interrupt Unit This section shows precautions on use of the DTP/external interrupt unit. ■ Conditions for external connection of peripheral devices For support by the DTP unit, external peripheral devices must be able to automatically clear a request after successful data transfer.
Page 373 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ External interrupt request level • If edge request has been selected for the request level, at least a pulse width of three machine cycles is required for detecting edge. • If level setting has been selected for the request input level, note that an external request that has been input remains active with respect to the interrupt controller even if it is later withdrawn, since the interrupt controller contains an internal source retention circuit.
Page 374: Program Example Of Dtp/External Interrupt
Note: Note: Setting related to clock and setting of _set_il (numeric For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR value) are required in advance. See the chapter of MC-16LX FAMILY MB90480 SERIES". clock and interrupt.
Page 375 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ■ Setting method other than program example ● Type of detection level and setting method 4 types of the detection level are provided ("L" level, "H" level, rising, falling). Set by the detection level bit (ELVR. LBx,LAx) x=0 to 7. Operation mode Detection level bit (LBx,LAx) x=0 to 7 To detect "L"...
Page 376 CHAPTER 16 DTP/EXTERNAL INTERRUPTS ● Interrupt related register The relationship between the external interrupt pin, interrupt level, and interrupt vector is shown in the following table. For details of the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT". External interrupt pin Interrupt vector Interrupt level setting bit Interrupt control register 00 (ICR00)
Page 377: Chapter 17 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER This chapter provides an overview of the 8/10-bit A/D converter, explains configuration and functions of these registers, operation, conversion data protection function, and shows the precautions on use. 17.1 Overview of 8/10-Bit A/D Converter 17.2 Configuration of 8/10-Bit A/D Converter 17.3 Configuration and Functions of 8/10-Bit A/D Converter Registers 17.4 Interrupt of 8/10-Bit A/D Converter 17.5 Operations of 8/10-Bit A/D Converter...
Page 378: Overview Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.1 Overview of 8/10-Bit A/D Converter This section describes the features of the 8/10-bit A/D converter and provides its block diagram. ■ Features of the 8/10-bit A/D converter The 8/10-bit A/D converter features the following functions: Conversion time: Minimum of 3.68 μs per channel •...
Page 379: Configuration Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 Configuration of 8/10-Bit A/D Converter This section describes the block diagram and configuration of 8/10-bit A/D converter. ■ Block diagram of 8/10-bit A/D converter Figure 17.2-1 shows a block diagram of the 8/10-bit A/D converter. Figure 17.2-1 Block diagram of 8/10-bit A/D converter AVRH D/A converter...
Page 380 CHAPTER 17 8/10-BIT A/D CONVERTER ■ Pin related to 8/10-bit A/D converter The pin related to 8/10-bit A/D converter has analog input AN0/AN1/AN2/AN3/AN4/AN5/AN6/ AN7 pins and input trigger ADTG pin. The general-purpose I/O port (P60/AN0, P61/AN1, P62/ AN2, P63/AN3, P64/AN4, P65/AN5, P66/AN6, P67/AN7) functions as the analog input pin of A/D, and the general-purpose I/O port (P93/ADTG) functions as the trigger input of A/D.
Page 381: Configuration And Functions Of 8/10-Bit A/D Converter Registers
CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 Configuration and Functions of 8/10-Bit A/D Converter Registers This section describes the configuration and functions of the registers used in the 8/10-bit A/D converter. ■ List of registers for 8/10-bit A/D converter Figure 17.3-1 illustrates the list of registers for 8/10-bit A/D Converter. Figure 17.3-1 List of registers for 8/10-bit A/D converter ADCS2 ADCS1...
Page 382: Control Status Register 1 (Adcs1)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.3.1 Control Status Register 1 (ADCS1) The control status register 1 (ADCS1) controls the A/D converter and displays the status of operation. ■ Control status register 1 (ADCS1) The bit configuration of the control status register 1 (ADCS1) is illustrated below. ADCS1 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Address: 000046...
Page 383 CHAPTER 17 8/10-BIT A/D CONVERTER These bits are initialized to "00" at reset. Each operation mode operates as follows: • After start of A/D conversion in continuous or stop mode, conversion will continue until operation is stopped via the BUSY bit. •...
Page 384 CHAPTER 17 8/10-BIT A/D CONVERTER [bit2, bit1, bit0] ANE2, ANE1, ANE0: ANalog End channel set These bits specify the end channel for A/D conversion. ANE2 ANE1 ANE0 End channel • Specifying the same channels as for ANS2 to ANS0 will result in one-channel conversion (Single conversion).
Page 385: Control Status Register 2 (Adcs2)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.3.2 Control Status Register 2 (ADCS2) The control status register 2 (ADCS2) is used for A/D converter control and status display. ■ Control status register 2 (ADCS2) The bit configuration of the control status register 2 (ADCS2) is illustrated below. ADCS2 BUSY INT INTE PAUS STS1 STS0 STRT Reserved...
Page 386 CHAPTER 17 8/10-BIT A/D CONVERTER [bit13] INTE: interrupt enable This bit is used to enable or disable interrupts at conversion end. • 0: Interrupts prohibited • 1: Interrupts allowed Set this bit when using μDMAC. An interrupt request will then trigger μDMAC start. This bit is initialized to "0"...
Page 387 CHAPTER 17 8/10-BIT A/D CONVERTER Note: When starting the A/D converter by an external trigger or an internal timer, set the input value of the internal timer and the external trigger only in inactive state. For setting STS1 and STS0, set in the state of ADTG=1 input and internal timer (PPG1) = 0 output. [bit9] STRT: start 8/10-bit A/D converter is started by software.
Page 388: Data Registers (Adcr2 And Adcr1)
CHAPTER 17 8/10-BIT A/D CONVERTER 17.3.3 Data Registers (ADCR2 and ADCR1) The configurations and functions of the data registers (ADCR2 and ADCR1) are explained below. ■ Data registers (ADCR2 and ADCR1) The function of each bit for the data registers (ADCR2 and ADCR1) is described below. ADCR1 Address: 000048 Initial value...
Page 389: Interrupt Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.4 Interrupt of 8/10-Bit A/D Converter The 8/10-Bit A/D converter generates the interrupt request when the A/D conversion is terminated, and the conversion result is stored to the A/D data register (ADCR). Also, it can activate the DMA transfer and extended intelligent I/O service (EI OS).
Page 390: Operations Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 Operations of 8/10-Bit A/D Converter The 8/10-bit A/D converter operates based on a sequential comparison method and has a 10-bit resolution. The 8/10-bit A/D converter has only one register for storing results of conversion (10- bit).
Page 391 CHAPTER 17 8/10-BIT A/D CONVERTER Set the BUSY bit to "0" to forcibly stop operation. When operation is stopped forcibly, data before the completion of conversion will be stored in the conversion registers. Note: When operation is forcibly stopped in continuous mode, conversion data retains data before operation of forced stop.
Page 392: Example Of Μdmac Start In Single Mode
CHAPTER 17 8/10-BIT A/D CONVERTER 17.5.1 Example of μDMAC Start in Single Mode An example of μDMAC start in the single mode is described below. Example of μDMAC start in single mode ■ An example of start operation is based on the conditions described below: •...
Page 393 CHAPTER 17 8/10-BIT A/D CONVERTER Figure 17.5-2 shows an example of the operational flow for start of conversion. Figure 17.5-2 Sample operation flow for μDMAC start operation in single mode Interrupt → μDMAC transfer Start Interrupt → μDMAC transfer Interrupt → μDMAC transfer Interrupt sequence Performed in parallel...
Page 394: Example Of Μdmac Start In Continuous Mode
CHAPTER 17 8/10-BIT A/D CONVERTER 17.5.2 Example of μDMAC Start in Continuous Mode An example of μDMAC start in the continuous mode is described below. Example of μDMAC start in continuous mode ■ Examples of start operation are based on the following conditions: •...
Page 395 CHAPTER 17 8/10-BIT A/D CONVERTER Figure 17.5-3 shows a sample operation flow for start processing. Figure 17.5-3 Sample operation flow for μDMAC start operation in continuous mode Interrupt → μDMAC transfer Start After completing all 6 transfer sessions Interrupt → μDMAC transfer Interrupt sequence Interrupt →...
Page 396: Example Of Μdmac Start In Stop Mode
CHAPTER 17 8/10-BIT A/D CONVERTER 17.5.3 Example of μDMAC Start in Stop Mode An example of μDMAC start in stop mode is described below. Example of μDMAC start in stop mode ■ Examples of start operation are based on the following conditions: •...
Page 397 CHAPTER 17 8/10-BIT A/D CONVERTER Figure 17.5-4 shows a sample operation flow for the start operation. Figure 17.5-4 Sample operation flow of μDMAC start operation in stop mode Interrupt → μDMAC transfer Start After completing all 12 transfer sessions Stop Interrupt sequence Start by external edge...
Page 398: Conversion Data Protection Function Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.6 Conversion Data Protection Function of 8/10-Bit A/D Converter This 8/10-bit A/D converter has a conversion data protection function to enable continuous conversion and saving of multiple data items by μDMAC. ■ Conversion data protection function The 8/10-bit A/D converter has only a single conversion data register.
Page 399 CHAPTER 17 8/10-BIT A/D CONVERTER Operation flow of conversion data protection function (when μDMAC is used) ■ Figure 17.6-1 shows the operation flow of the conversion data protection function. Figure 17.6-1 Operation flow of conversion data protection function μ (when DMAC is used) μDMAC setting The operation flow for the case in which...
Page 400: Precautions On Use Of The 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.7 Precautions on use of the 8/10-Bit A/D Converter This section explains the precautions required when the 8/10-bit A/D converter is used. ■ Precautions when starting by external trigger/internal trigger To start the A/D converter by an external trigger or the internal timer, specify the input values of the external trigger and internal timer only in the inactive state.
Page 401: Program Example Of 8/10-Bit A/D Converter
CHAPTER 17 8/10-BIT A/D CONVERTER 17.8 Program Example of 8/10-Bit A/D Converter This section describes the program example of the 8/10-bit A/D converter. ■ Program example of 8/10-bit A/D converter Example of setting procedure Program example An example that A/D-converts the level input by AN0 (single void AD_sample() conversion, software trigger) is shown below.
Page 402 For the description form of the register, see "SAMPLE I/O REGISTER FILES are required in advance. See the chapter of clock and interrupt. FOR F MC-16LX FAMILY MB90480 SERIES". ■ Setting method other than program example ● Type of conversion mode and setting method The following three conversion modes are available.
Page 403 CHAPTER 17 8/10-BIT A/D CONVERTER ● Method to enable analog pin input Set by the analog input enable register (ADER) Operation Control bit Setting To input AN0 pin (ADER.ADE0) Set to "1" To input AN1 pin (ADER.ADE1) Set to "1" To input AN2 pin (ADER.ADE2) Set to "1"...
Page 404 CHAPTER 17 8/10-BIT A/D CONVERTER The start trigger occurs due to underflow of the reload timer when output signal of the reload timer is set to rising edge. • Method to start by external trigger The external trigger is set by the external trigger input pin (ADTG). The external trigger input pin is set by the data direction bit (DDR9.P93).
Page 405 CHAPTER 17 8/10-BIT A/D CONVERTER ● Interrupt related register The relationship between the interrupt level and interrupt vector is shown in the following table. For details of the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT". Interrupt vector Interrupt level setting bit Interrupt control register 14 (ICR14) Address: FFFF5C Address: 0000BE...
Page 406 CHAPTER 17 8/10-BIT A/D CONVERTER...
Page 407: Chapter 18 Expanded I/O Serial Interface
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE This chapter provides an overview, of the expanded I/O serial interface, explains the configuration, interrupt, and its operation, the configuration and functions of its registers. 18.1 Overview of Expanded I/O Serial Interface 18.2 Configuration of Expanded I/O Serial Interface 18.3 Configuration and Functions of Expanded I/O Serial Interface Registers 18.4 Interrupt of Expanded I/O Serial Interface 18.5 Operation of Expanded I/O Serial Interface...
Page 408: Overview Of Expanded I/O Serial Interface
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.1 Overview of Expanded I/O Serial Interface The expanded I/O serial interface is a serial I/O interface with an 8-bit/1-channel configuration that is used to transfer data by clock synchronization. For data transfer, LSB first or MSB first can be selected. ■...
Page 409: Configuration Of Expanded I/O Serial Interface
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.2 Configuration of Expanded I/O Serial Interface The expanded I/O serial interface consists of the serial mode control status register and serial data register. ■ Block diagram of expanded I/O serial interface Figure 18.2-1 shows a block diagram of the expanded I/O serial interface. Figure 18.2-1 Block diagram of expanded I/O serial interface Internal data bus Initial value...
Page 410 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE ● Setting when using as SIN1/SCK1/SIN2/SCK2 pins When the SIN1/SCK1/SIN2/SCK2 pins are used as input by the expanded I/O serial interface, P90/SIN1, P92/SCK1, P40/SIN2, P42/SCK2 pins should be set to the input port by the port direction register (DDR9 bit8, 10→"0"...
Page 411: Configuration And Functions Of Expanded I/O Serial Interface Registers
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.3 Configuration and Functions of Expanded I/O Serial Interface Registers This section describes the configuration and functions of the registers used by the expanded I/O serial interface. ■ List of registers for expanded I/O serial interface Figure 18.3-1 shows a list of the registers used by the expanded I/O serial interface.
Page 412: Serial Mode Control Status Register 0/1 (Smcs0/Smcs1)
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.3.1 Serial Mode Control Status Register 0/1 (SMCS0/SMCS1) This section describes the configuration and functions of the serial mode control status register0/1 (SMCS0/SMCS1). ■ Serial mode control status register0/1 (SMCS0/SMCS1) The serial mode control status register 0/1 (SMCS0/SMCS1) controls the data transfer mode of serial I/O operations.
Page 413 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE At reset, the settings will be initialized to "000 ". These bits cannot be rewritten while data transfer is in progress. The shift clock can be selected from among five internal clocks and one external clock. The combinations of SMD2, SMD1, SMD0 = 110 and 111 are reserved and must not be set.
Page 414 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE [bit9] STOP (Stop bit) This bit is used to forcibly interrupt serial transfer. Setting this bit to "1" will result in operation stop. STOP Operation Normal operation Stop of transfer because of STOP = 1 (initial value) •...
Page 415 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE [bit1] SOE: Serial Out Enable (enable serial output) This bit is controls the output of the external output pins (SOT1 and SMD2) for serial I/O. General-purpose port pin (initial value) Serial data output • This bit is initialized to "0"...
Page 416: Serial Data Register 0/1 (Sdr0/Sdr1)
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.3.2 Serial Data Register 0/1 (SDR0/SDR1) This section describes the configuration and functions of the serial data register 0/1 (SDR0/SDR1). ■ Serial data register 0/1 (SDR0/SD1) The bit configuration of the serial data register 0/1 (SDR0/SDR1) is illustrated below. Initial value SDR 0/1 XXXXXXXX...
Page 417: Communication Prescaler Control Register0/1 (Sdcr0/Sdcr1)
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.3.3 Communication Prescaler Control Register0/1 (SDCR0/SDCR1) This section describes the configuration and functions of the communication prescaler control register0/1 (SDCR0/SDCR1). ■ Communication prescaler control register0/1 (SDCR0/SDCR1) The bit configuration of the communication prescaler control register0/1 (SDCR0/SDCR1) is illustrated below.
Page 418: Interrupt Of Expanded I/O Serial Interface
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.4 Interrupt of Expanded I/O Serial Interface The interrupt of the expanded I/O serial interface occurs when the data transfer is terminated. The interrupt of the expanded I/O serial interface can activate the DMA transfer and extended intelligent I/O service (EI OS).
Page 419: Operation Of Expanded I/O Serial Interface
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.5 Operation of Expanded I/O Serial Interface The expanded I/O serial interface consists of the serial mode control status register (SMCS) and shift register (SDR). This interface is used for input and output of 8-bit serial data.
Page 420: Shift Clock Modes
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.5.1 Shift Clock Modes The shift clock has two modes, the internal shift clock mode and the external shift clock mode. These two modes are specified by the setting of the SMCS. Change the mode only when the serial I/O interface is not operating.
Page 421: Operational States Of Serial I/O Units
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.5.2 Operational States of Serial I/O Units Four serial I/O states are used, namely, STOP, Halt, SDR R/W Wait, and Transfer. ■ Operational states of serial I/O units ❍ STOP State The shift counter is initialized to SIR=0 at reset or by writing "1" to the STOP bit of SMCS. To return from the STOP state, set STOP = 0 and STRT= 1 (these bits can be set simultaneously).
Page 422 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE Figure 18.5-2 Concept of read and write for serial data registers Data bus Data bus Read Read Write Write Interrupt output Interrupt input Expanded I/O Interrupt controller serial interface Data bus (1) For MODE = 1, data transfer is ended by the shift clock counter. A read/write wait state will be entered after SIR is set to 1.
Page 423: Start/Stop Timing And Input/Output Timing Of Shift Operation
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.5.3 Start/Stop Timing and Input/Output Timing of Shift Operation Start/stop timing and input/output timing of the shift operation are described below. ■ Start/Stop timing and input/output timing of shift operation • Start Set the STOP bit and STRT bit of SMCS to "0" and "1", respectively. •...
Page 424 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE ❍ Instruction shift in external shift clock mode (LSB first) During instruction shift, "H" will be output if the bit corresponding to SCK in PDR is set to "1" and "L" will be output if the bit is set to "0". (If SCOE = 0 when external shift clock mode is selected.) Figure 18.5-5 Instruction shift in external shift clock mode PDR SCK bit "0"...
Page 425: Interrupt Function
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE 18.5.4 Interrupt Function The expanded I/O serial interface generates the interrupt requests for the CPU. ■ Interrupt function of expanded I/O serial interface An interrupt request is output to the CPU when the SIR bit, which acts as an interrupt flag, is set at the end of data transfer provided that the SIE bit of the SMCS, which enables interrupts, is "1".
Page 426: Program Example Of Expanded I/O Serial Interface
Note: Note: Setting related to clock and setting of __set_il For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR (numeric value) are required in advance. MC-16LX FAMILY MB90480 SERIES". See the chapter of clock and interrupt.
Page 427 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE ■ Setting method other than program example ● Type of operation clock and selection method There are two operation clocks: internal timer and external clock. Set by the shift clock select bits (SMCS0.SMD[2:0], SMCS1.SMD[2:0]). Shift clock select bits (SMD[2:0]) Content of control To select internal timer...
Page 428 CHAPTER 18 EXPANDED I/O SERIAL INTERFACE ● Interrupt related register The relationship between the SIO number, interrupt level, and interrupt vector is shown in the following table. For details of the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT". Interrupt vector Interrupt level setting register Interrupt level register (ICR13)
Page 429: Chapter 19 Uart
CHAPTER 19 UART This chapter provides an overview, of the UART, explains the configuration, interrupt, its operation, the configuration and functions of its registers shows the precautions on use, and program example of the UART. 19.1 Overview of the UART 19.2 Configuration of UART 19.3 Configuration and Functions of UART Registers 19.4 Interrupt of UART...
Page 430: Overview Of The Uart
CHAPTER 19 UART 19.1 Overview of the UART The UART is a serial I/O port for asynchronous (start-stop synchronization) communications or CLK synchronous communication. ■ UART features The UART has the following features: • Built-in full-duplex double buffer • Both asynchronous (start-stop synchronization) and CLK synchronous communication (no start bit and stop bit) are available •...
Page 431: Configuration Of Uart
CHAPTER 19 UART 19.2 Configuration of UART The UART consists of the serial mode register, serial control register, serial status register, communication prescaler control register and serial input/output register. ■ UART Block Diagram Figure 19.2-1 shows a block diagram of the UART. Figure 19.2-1 Block diagram of the UART Control signal Reception interrupt (to CPU)
Page 432 CHAPTER 19 UART ■ Pin related to UART The pin related to the UART has the SIN0/SOT0/SCK0 pins. The SIN0 pin functions as the serial input port, the SOT0 pin functions as the serial output port, and the SCK0 pin functions as the external clock input port.
Page 433: Configuration And Functions Of Uart Registers
CHAPTER 19 UART 19.3 Configuration and Functions of UART Registers This section describes the configuration and functions of the registers used by the UART. ■ List of UART registers Figure 19.3-1 lists the UART registers. Figure 19.3-1 List of UART registers (R/W) SIDR(R)/SODR(W) (R/W)
Page 434: Serial Mode Register (Smr)
CHAPTER 19 UART 19.3.1 Serial Mode Register (SMR) This section describes the configuration and functions of the serial mode register (SMR). ■ Serial mode register (SMR) The bit configuration of the serial mode register (SMR) is illustrated below. 000020 MD1 MD0 CS2 CS1 CS0 SCKE SOE Serial mode register (SMR) Reserved...
Page 435 CHAPTER 19 UART [bit5, bit4, bit3] CS2, CS1, CS0: Clock Select These bits select the baud rate clock sources. When a dedicated baud rate generator is selected, the baud rate will be determined at the same time. CS2 to CS0 Clock input to 101 Dedicated baud rate generator...
Page 436: Serial Control Register (Scr)
CHAPTER 19 UART 19.3.2 Serial Control Register (SCR) This section describes the configuration and functions of the serial control register (SCR). ■ Serial control register (SCR) The bit configuration of the serial control register (SCR) is illustrated below. 000021 REC RXE TXE Serial control register (SCR) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Read/write Initial value...
Page 437 CHAPTER 19 UART [bit12] CL: Character Length This bit specifies the data length of one frame to be sent or received. 7-bit data 8-bit data Note: Only the normal mode (Mode 0) in asynchronous (start-stop synchronization) communications can handle 7-bit data. Specify 8-bit data in multiprocessor mode (Mode 1) or CLK synchronous mode (Mode 2).
Page 438: Serial Input/Output Register (Sidr/Sodr)
CHAPTER 19 UART 19.3.3 Serial Input/Output Register (SIDR/SODR) This section describes the configuration and functions of the serial input/output register (SIDR/SODR). ■ Serial input/output register (SIDR/SODR) The bit configuration of the serial input/output register (SIDR/SODR) is illustrated below. Serial input register (SIDR)/ 000022 Serial output register (SODR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write...
Page 439: Serial Status Register (Ssr)
CHAPTER 19 UART 19.3.4 Serial Status Register (SSR) This section describes the configuration and functions of the serial status register (SSR). ■ Serial status register (SSR) The bit configuration of the serial status register (SSR) is illustrated below. 000023 ORE FRE RDRF TDRE BDS Serial status register (SSR) (R) (R/W) (R/W) (R/W) Read/write Initial value...
Page 440 CHAPTER 19 UART [bit11] TDRE: Transmitter Data Register Empty This bit is an interrupt request flag that indicates that transmission data can be written to the SODR register. This flag is cleared when transmission data is written to the SODR register. The flag will be set again to indicate that the next item of transmission data can be written when written data is loaded into the transmission shift register unit and data transfer starts.
Page 441: Communication Prescaler Control Register (Cdcr)
CHAPTER 19 UART 19.3.5 Communication Prescaler Control Register (CDCR) This section describes the configuration and functions of the communication prescaler control register (CDCR). ■ Communication prescaler control register (CDCR) The bit configuration of the communication prescaler control register (CDCR) is illustrated below.
Page 442 CHAPTER 19 UART [bit11, bit10, bit9, bit8] DIV3, DIV2, DIV1, DIV0 These bits are determines the division ratios of the machine clocks. DIV3 to DIV0 Division Ratio 0000 Division by 1 0001 Division by 2 0010 Division by 3 0011 Division by 4 0100 Division by 5...
Page 443: Interrupt Of Uart
CHAPTER 19 UART 19.4 Interrupt of UART The UART has the reception and transmission interrupts. The interrupt of the UART can activate the DMA transfer and extended intelligent I/O service (EI OS). ■ Interrupt of UART The following table shows the interrupt control bit and interrupt source of the UART. UART reception interrupt UART transmission interrupt Data reception completion SSR:...
Page 444 CHAPTER 19 UART ■ Interrupt of UART, DMA transfer, and EI Table 19.4-1 shows the relationship between the interrupt source, interrupt vector, and interrupt control register other than software interrupt. Table 19.4-1 Interrupt source, interrupt vector, and interrupt control register μDMAC Interrupt vector Interrupt control register...
Page 445: Uart Operations
CHAPTER 19 UART 19.5 UART Operations This section describes the operations of the UART. ■ Operation modes UART has the operation modes shown below. The modes can be changed by setting values in the SMR and SCR registers. Mode Parity Data length Operation mode Stop bit length...
Page 446 CHAPTER 19 UART ■ UART clock selection ❍ Dedicated Baud Rate Generator - Asynchronous baud rate = φ / (prescaler division ratio) / (asynchronous transfer clock division ratio) - Synchronous baud rate = φ / (prescaler division ratio) / (synchronous transfer clock division ratio) φ: Machine clock •...
Page 447 CHAPTER 19 UART • For the division ratios of the asynchronous transfer clock, see Table 19.5-3. Table 19.5-3 Division ratios of the asynchronous transfer clock Non-CLK Calculation formula SCK0 synchronous × × × 76923 (φ / DIV)/(8 (φ / DIV)/(13 ×...
Page 448 CHAPTER 19 UART ❍ Internal timer The applicable baud rate when CS2 to CS0 are set to "110" and the internal timer (PPG1) is selected can be calculated by the following expressions: Asynchronous (start-stop synchronization): (φ / N) /(16 x 2 x (n + 1)) CLK synchronous: (φ...
Page 449: Operation In Asynchronous Mode (Operation Modes 0 And 1)
CHAPTER 19 UART 19.5.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) Transfer operation becomes asynchronous when the UART is used in operation mode 0 (normal mode) or in operation mode 1 (multiprocessor mode). ■ Operation in asynchronous mode (operation modes 0 and 1) ❍...
Page 450 CHAPTER 19 UART ❍ Reception Operation Reception is always performed if reception operation is enabled (SCR: RXE = 1). When the start bit is detected, one frame of data is received in accordance with the data format determined by the serial control register (SCR). When the error flag is set at the time of error after one frame has been received, the reception data full flag bit (SSR: RDRF) is set to "1".
Page 451 CHAPTER 19 UART ❍ Stop bit One or two stop bits can be selected for sending. The receiving unit, however, will only identify the first stop bit. ❍ Error detection • Mode 0: Parity errors, overrun errors, and frame errors can be detected. •...
Page 452: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 19 UART 19.5.2 Operation in Synchronous Mode (Operation Mode 2) The transfer operation becomes clock-synchronous when the UART operates in operation mode 2 (CLK synchronous mode). ■ Operation in CLK synchronous mode (operation mode 2) ❍ Transfer Data Format In synchronous mode, 8-bit data is transferred with LSB first, and no start bit or no stop bit is added.
Page 453 CHAPTER 19 UART ❍ Initialization The appropriate setting values for the control registers when using synchronous mode are shown below. [Serial mode register (SMR)] • MD1 and MD0: "10" • CS2, CS1, CS0: Specify the clock source determined by the clock selector. •...
Page 454: Two-Way Communication Function (Normal Mode)
CHAPTER 19 UART 19.5.3 Two-Way Communication Function (Normal Mode) Normal serial two-way communication in a 1:1 connection can be performed in operation modes 0 and 2. The synchronization type is "asynchronous" for operation mode 0 and "synchronous" for operation mode 2. ■...
Page 455 CHAPTER 19 UART ■ Communication procedure for two-way communication function Communication is started from the sending side with an arbitrary timing when data for transmission is ready. When the receiving side receives the transmission data, returns ANS (in this example, separately for each byte) periodically.
Page 456: Master/Slave Communication Function (Multiprocessor Mode)
CHAPTER 19 UART 19.5.4 Master/Slave Communication Function (Multiprocessor Mode) The UART enables communication in a master/slave connection in which more than one CPU is connected. Operation mode 1 is used in this case. The UART itself can be used only as the master system. ■...
Page 457 CHAPTER 19 UART ■ Function selection Table 19.5-5 lists settings for selecting the communication method in master/slave communication. Table 19.5-5 Function selection in master/slave communication Operation mode Synchronous Data Parity Stop bit Master Slave operation Sending and receiving A/D = 1 + 8-bit address the addresses 1 or 2 Mode 1...
Page 458 CHAPTER 19 UART Figure 19.5-11 Procedure for communication using the master/ slave communication function Start (Master CPU) Set operation mode "1" The SIN pin is specified as serial data input Specify one-byte data (address data) for selecting the slave CPUs in D0 to D7, and send data (A/D = 1) Set A/D to "0"...
Page 459: Precautions On Use Of The Uart
CHAPTER 19 UART 19.6 Precautions on use of the UART Notes the following points when using the UART. ■ Precautions on use of the UART ❍ Enabling operation The serial control register (SCR) of the UART contains operation enable bits for enabling sending and receiving, namely, TXE (sending) and RXE (reception).
Page 460: Program Example Of Uart
Note: Note: Setting related to clock and setting of __set_il For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR (numeric value) are required in advance. See the MC-16LX FAMILY MB90480 SERIES". chapter of clock and interrupt.
Page 461 CHAPTER 19 UART ■ Setting method other than program example ● Combination that can be set The combination is shown below. Presence or absence of error flags Parity Selection of Operation mode Data length Data format Parity (PEN) selection STOP bit length (MD[1:0]) (CL) (A/D)
Page 462 CHAPTER 19 UART ● Method to control SCK, SIN and SOT pins Set as follows. UART register DDR7.P72 = 0 To input SCK pin SMR.SCKE = 0 To output SCK pin SMR.SCKE = 1 To input SIN pin DDR7.P70 = 0 To output SOT pin SMR.SOE = 1 ●...
Page 463 CHAPTER 19 UART ● Method to select stop bit length Set by the stop bit length select bit (SCR, SBL). Operation Stop bit length select bit (SBL) To set STOP bit to 1 bit Set to "0" To set STOP bit to 2 bit Set to "1"...
Page 464 CHAPTER 19 UART ● Method to clear the transmission buffer empty flag Perform in the following method. Content of control Serial output register (SODR) To clear transmission buffer empty flag Write to SODR register Writing to the SODR register for the first time starts the transmission. ●...
Page 465 CHAPTER 19 UART ● Method to check completion of operation Perform in the following method. • Mode 0/1, transmission : Check the SSR register empty flag after next transmission data is written. (completion can be checked when next transmission data is transferred from register to shifter and the empty flag in the serial output register is set to "1".) •...
Page 466 CHAPTER 19 UART The interrupt request is cleared in the following method UART reception UART transmission To clear interrupt The reception completion flag (RDRF) The transmission buffer empty flag request is set to "0" by reading the serial input (TDRE) is set to "0" when data is written register (SIDR).
Page 467: Chapter 20 Chip Selection Facility
CHAPTER 20 CHIP SELECTION FACILITY This chapter provides an overview, of the chip selection facility explains the configuration, and its operation, the configuration and functions of its registers. 20.1 Overview of Chip Selection Facility 20.2 Configuration of Chip Selection Facility 20.3 Configuration and Functions of Chip Selection Facility Registers 20.4 Operation of the Chip Selection Facility...
Page 468: Overview Of Chip Selection Facility
CHAPTER 20 CHIP SELECTION FACILITY 20.1 Overview of Chip Selection Facility The chip selection facility is a module used to generate a chip selection signal for simplified memory connection to the outside. It contains four chip selection output pins. The chip selection facility has four chip select output pins and enables an area within the hardware to be specified via an output setting register, and if the device detects an access to that external address, it outputs a selection signal via the corresponding pin.
Page 469: Configuration Of Chip Selection Facility
CHAPTER 20 CHIP SELECTION FACILITY 20.2 Configuration of Chip Selection Facility This section describes the block diagram and pin related to the chip selection facility. ■ Block diagram of the chip selection facility Figure 20.2-1 shows a block diagram of the chip selection facility. Figure 20.2-1 Block diagram of the chip selection facility CMRx CARx...
Page 470 CHAPTER 20 CHIP SELECTION FACILITY ■ Block diagram of pin related to chip select facility Figure 20.2-2 Block diagram of pin related to chip select facility Peripheral function output (CS0 to CS3) Peripheral function output enable Port data register (PDR) PDR Read P-ch Output latch...
Page 471: Configuration And Functions Of Chip Selection Facility Registers
CHAPTER 20 CHIP SELECTION FACILITY 20.3 Configuration and Functions of Chip Selection Facility Registers This section describes the configuration and functions of the registers used by the chip selection facility. ■ List of registers used for the chip selection facility Figure 20.3-1 lists the registers for the chip selection facility.
Page 472: Chip Select Area Mask Register (Cmrx)
CHAPTER 20 CHIP SELECTION FACILITY 20.3.1 Chip Select Area MASK Register (CMRx) This section describes the configuration and functions of the chip selection area MASK register (CMRx). ■ Chip selection area MASK register (CMRx) The diagram below shows the bit configuration of the chip selection area MASK register (CMRx).
Page 473: Chip Selection Area Register (Carx)
CHAPTER 20 CHIP SELECTION FACILITY 20.3.2 Chip Selection Area Register (CARx) This section describes the configuration and functions of the chip selection area register (CARx). ■ Chip selection area register (CARx) The diagram below shows the bit configuration of the chip selection area register (CARx). 0000C1 CARx 0000C3...
Page 474: Chip Selection Control Register (Cscr)
CHAPTER 20 CHIP SELECTION FACILITY 20.3.3 Chip Selection Control Register (CSCR) This section describes the configuration and functions of the chip selection control register (CSCR). ■ Chip selection control register (CSCR) The diagram below shows the bit configuration of the chip selection control register (CSCR). CSCR 0000C8 OPL3 OPL2 OPL1 OPL0...
Page 475: Chip Selection Active Level Register (Calr)
CHAPTER 20 CHIP SELECTION FACILITY 20.3.4 Chip Selection Active Level Register (CALR) This section describes the configuration and functions of the chip selection active level register (CALR). ■ Chip selection active level register (CALR) The diagram below shows the bit configuration of the chip selection active level register (CALR). CALR 0000C9 ACTL3 ACTL2 ACTL1 ACTL0...
Page 476: Operation Of The Chip Selection Facility
CHAPTER 20 CHIP SELECTION FACILITY 20.4 Operation of the Chip Selection Facility This section describes the operations of the chip selection facility. ■ Outline of operations When the CPU accesses program or data, the chip selection facility is activated if a match between the upper 8 bits of an address and CAR0/1/2/3 is detected.
Page 477 CHAPTER 20 CHIP SELECTION FACILITY ■ Notes on using the chip selection facility • The CS0 pin always becomes active to read the reset vector if used in external vector mode. In the address space F00000 to FFFFFF (1 MB: initial value), always use this pin only for the access to program ROM, since the corresponding decode signal will be output immediately after a reset.
Page 478 CHAPTER 20 CHIP SELECTION FACILITY...
Page 479: Chapter 21 Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION This chapter explains the functions and operations of the address match detection. 21.1 Overview of Address Match Detection Function 21.2 Block Diagram of Address Match Detection Function 21.3 Configuration of Registers for Address Match Detection Function 21.4 Explanation of Operation of Address Match Detection Function 21.5 Program Example of Address Match Detection Function...
Page 480: Overview Of Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the program address detection registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program.
Page 481: Block Diagram Of Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Program address detection control status register (PACSR) • Program address detection registers (RADR) ■...
Page 482: Configuration Of Registers For Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Configuration of Registers for Address Match Detection Function This section details the registers used by the address match detection function. ■ List of Registers and Initial Values of Address Match Detection Function Figure 21.3-1 List of Registers and Initial Values of Address Match Detection Function Program address detection control status register (PACSR): Address 009E...
Page 483: Program Address Detection Control Status Register (Pacsr)
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3.1 Program Address Detection Control Status Register (PACSR) The program address detection control status register (PACSR) enables or disables output of an interrupt at an address match. If an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is output.
Page 484 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION Table 21.3-1 Functions of Program Address Detection Control Status Register (PACSR) Bit Name Function bit7 to reserved: reserved Always set to "0". bit4 The address match detection operation with the program address detection register 1 (PADR1) is enabled or disabled. When set to "0": Disables the address match detection operation.
Page 485: Program Address Detection Registers (Padr0, Padr1)
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3.2 Program Address Detection Registers (PADR0, PADR1) The value of an address to be detected is set in the program address detection registers. When the address of the instruction processed by the program matches the address set in the program address detection registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
Page 486 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ Functions of Program Address Detection Registers (PADR0 and PADR1) There are two program address detection registers (PADR0 and PADR1) that consist of a high byte, middle byte, and low byte, totaling 24 bits. Table 21.3-2 Address Setting of Program Address Detection Registers Interrupt Output Register Name...
Page 487: Explanation Of Operation Of Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the program address detection registers (PADR0 and PADR1), the address match detection function will replace the first instruction code executed by CPU with the INT9 instruction (01 ) to branch to the interrupt processing program.
Page 488: Example Of Using Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E PROM Memory Map ❍ System configuration Figure 21.4-2 gives an example of the system configuration using the address match detection function.
Page 489 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ PROM Memory Map Figure 21.4-3 shows the allocation of the E PROM patch program data. Figure 21.4-3 Allocation of E PROM Patch Program and Data PROM Address 0000 Patch program byte count 0001 Detection address 0 (Low) For patch program 0 PADR0...
Page 490 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ Setting and Operating State ❍ Initialization • E PROM data are all cleared to "00 ". ❍ Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (MB90480/485 series) from the outside according to the allocation of the E PROM patch program and data.
Page 491 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ Operation of Address Match Detection Function at Storing Patch Program in E PROM Figure 21.4-4 shows the operation of the address match detection function at storing the patch program in E PROM. Figure 21.4-4 Operation of Address Match Detection Function at Storing Patch Program in E PROM 000000...
Page 492 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ Flow of Patch Processing Figure 21.4-5 shows the flow of patch processing. Figure 21.4-5 Flow of Patch Processing MB90480/485 series PROM 0000 Patch program byte count : 80 I/O area 000000 0001 Detect address (Low) : 00 000100 Register/RAM area 0002...
Page 493: Program Example Of Address Match Detection Function
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ❍ Processing specifications If the address of the instruction to be executed by the program matches the address set in the program address detection register (PADR0), the INT9 instruction is executed.
Page 494 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION...
Page 495: Chapter 22 Rom Mirror Function Selection Module
CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE This chapter provides an overview of the ROM mirror function selection module and explains its registers. 22.1 Overview of ROM Mirror Function Selection Module 22.2 ROM Mirror Function Selection Register (ROMM)
Page 496: Overview Of Rom Mirror Function Selection Module
CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE 22.1 Overview of ROM Mirror Function Selection Module The ROM mirror function selection module is set to read the ROM data arranged in FF bank with access to 00 bank. ■ Block diagram of the ROM mirror function selection module Figure 22.1-1 shows a block diagram of the ROM mirror function selection module.
Page 497: Rom Mirror Function Selection Register (Romm)
CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE 22.2 ROM Mirror Function Selection Register (ROMM) This section describes the configuration and functions of the ROM mirror function selection register (ROMM). ■ ROMM (ROM mirror function selection register) The diagram below shows the bit configuration of the ROM mirror function selection register (ROMM).
Page 498 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE...
Page 499: Chapter 23 2M/3M Bit Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY This chapter explains the functions and operations of the 2M/3M bit flash memory. The following three operations are available for writing data to or erasing data from flash memory. • Writing/erasing via the program •...
Page 500: Overview Of 2M/3M Bit Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.1 Overview of 2M/3M Bit Flash Memory In the CPU memory map, the 2M/3M bit flash memory is allocated in banks FC to FF, and the operations for using the flash memory interface circuit, read access and program access from the CPU are provided just as they are for mask ROM.
Page 501: Sector Configuration Of 2M/3M Bit Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.2 Sector Configuration of 2M/3M Bit Flash Memory This section describes the sector configuration of the 2M/3M bit flash memory. ■ Sector configuration Figure 23.2-1 shows the sector configuration of the 2M/3M bit flash memory. The addresses in the figure indicate the upper and lower addresses of each sector.
Page 502: Flash Memory Control Status Register (Fmcs)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.3 Flash memory Control Status Register (FMCS) The flash memory control status register (FMCS) is used for write/erase operations on flash memory via the registers in the flash memory interface circuit. ■ Flash memory control status register (FMCS) The diagram below shows the bit configuration of the flash memory control status register (FMCS).
Page 503 In order to prevent accidental writing of any data to the flash memory, Fujitsu recommends always setting this bit to "0" whenever no write/erase operations are to be executed.
Page 504 CHAPTER 23 2M/3M BIT FLASH MEMORY ■ End timing of the automatic algorithm Figure 23.3-1 shows the relationship among the end timing of the automatic algorithm, the RDYINT bit, and the RDY bit. The RDYINT bit and RDY bit do not change at the same time. Write programs so as to determine the end of automatic algorithm using either of one bit.
Page 505 CHAPTER 23 2M/3M BIT FLASH MEMORY ■ Setting subclock mode If the subclock mode is used, the following settings are required: ❍ If subclock mode is used at an internal clock frequency of 10 MHz or less To use the subclock mode, change the low-power consumption mode selection bits (LPM1, LPM0) of the flash memory control status register to other than 0, 0 at initialization.
Page 506 CHAPTER 23 2M/3M BIT FLASH MEMORY ❍ If subclock mode is used at an internal clock frequency of more than 10 MHz To use subclock mode, first set the internal clock frequency to 10 MHz or less and next change the low-power consumption mode selection bits (LPM1, LPM0) to other than 0, 0 before changing to subclock mode.
Page 507 CHAPTER 23 2M/3M BIT FLASH MEMORY For operation at an internal clock frequency of more than 10 MHz after subclock mode is canceled, change the mode to main clock mode or PLL clock mode (internal clock frequency becomes 10 MHz or less), change the low-power consumption mode selection bits (LPM1, LPM0) to 0, 0, and then set the internal clock frequency to more than 10 MHz.
Page 508: Method For Starting The Flash Memory's Automatic Algorithm
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.4 Method for Starting the Flash Memory's Automatic Algorithm There are four kinds of commands for starting the automatic algorithm for flash memory: read/reset, write, chip erase, and sector erase. For sector erase operations, control of suspension and resuming is provided.
Page 509: Verifying The Execution State Of The Automatic Algorithm
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.5 Verifying the Execution State of the Automatic Algorithm The flash memory contains dedicated hardware indicating the internal operation state of the flash memory and whether operations have been completed that can be used to control the operational flow of write/erase operations via the automatic algorithm.
Page 510 CHAPTER 23 2M/3M BIT FLASH MEMORY Table 23.5-2 lists the hardware sequence flag functions. Table 23.5-2 List of hardware sequence flag functions State → → → → Write operation → write completed Toggle (specifying the write address) DATA: 7 DATA: 6 DATA: 5 DATA: 3 →...
Page 511: Data Polling Flag (Dq7)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.5.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a flag that is used to indicate via the data polling function whether execution of the automatic algorithm is in progress or has ended. ■...
Page 512 CHAPTER 23 2M/3M BIT FLASH MEMORY ■ Sector erase suspend Read operations of the flash memory while sector erase is suspended will output "1" if an address for the sector being erased has been specified, or will output the read value of bit7 (DATA: 7) for the specified data item will be output in other cases.
Page 513: Toggle Bit Flag (Dq6)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.5.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) is a flag mainly used to indicate whether the automatic algorithm is being executed or has ended. In the case of the toggle bit flag, a toggle bit function is used for that purpose.
Page 514: Timing Limit Excess Flag (Dq5)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.5.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag (DQ5) is used to indicate when the execution of the automatic algorithm exceeds the time (internal pulse count) specified in the internal flash memory. ■...
Page 515: Sector Erase Timer Flag (Dq3)
If this flag is set to "0", the flash memory will accept writing of the additional sector erase code. Fujitsu recommends checking the state of the flag before subsequent sector erase codes are written to verify the operational state of the device. If a second state check returns the flag to "1", the erase code for an additional sector may not have been accepted.
Page 516: Flash Memory Write/Erase Operations
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6 Flash Memory Write/Erase Operations This section describes various operation procedures after issuing the automatic algorithm start command, including flash memory read/reset, write, chip erase, sector erase, sector erase suspend and sector erase resume. ■...
Page 517: Setting The Flash Memory To Read/Reset State
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.1 Setting the Flash Memory to Read/Reset State This section describes the procedures for issuing read/reset commands and setting the flash memory to read/reset state. ■ Setting the flash memory to the read/reset state To set the flash memory to the read/reset state, continuously send the read/reset command in the command sequence table (see Table 23.4-1) to the relevant sector in the flash memory.
Page 518: Writing Data To Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.2 Writing Data to Flash Memory This section describes the procedures for issuing a write command to write data to the flash memory. ■ Writing data to flash memory To start the automatic data write algorithm for the flash memory, repeatedly send the write command in the command sequence table (see Table 23.4-1) to the relevant sector in the flash memory.
Page 519 CHAPTER 23 2M/3M BIT FLASH MEMORY ■ Operation for writing to flash memory Figure 23.6-1 shows an example of the procedure for writing to flash memory. Using the hardware sequence flag (see Section "23.5 Verifying the Execution State of the Automatic Algorithm"), the operational state of the automatic algorithm operating on the flash memory can be determined.
Page 520: Erasing All Data In The Flash Memory (Chip Erase)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.3 Erasing All Data in the Flash Memory (Chip Erase) This section describes the procedure for issuing the chip erase command to erase all data in the flash memory. ■ Erasing all data in the flash memory (chip erase) To erase all data in the flash memory, repeatedly send the chip erase command in the command sequence table (see Table 23.4-1) to the relevant sector in the flash memory.
Page 521: Erasing Arbitrary Data In Flash Memory (Sector Erase)
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) This section describes the procedure for issuing a sector erase command to erase an arbitrary sector in flash memory. This procedure allows either erasure of individual sectors or erasure of multiple sectors at the same time to be specified.
Page 522 CHAPTER 23 2M/3M BIT FLASH MEMORY Figure 23.6-2 Example of sector erase procedure for flash memory Start of deletion FMCS:WE(bit5) Flash memory deletion enabled Delete command sequence (1) FxAAAA XXAA (2) Fx5554 XX55 (3) FxAAAA XX80 (4) FxAAAA XXAA (5) Fx5554 XX55 (6) Enter code to the delete sector (30...
Page 523: Suspending Sector Erasure For The Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.5 Suspending Sector Erasure for the Flash Memory This section describes the procedure for issuing the sector erase suspend command to suspend a sector erase operation for the flash memory. During erase suspension, data can be read from any sector that is not subject to erasure. ■...
Page 524: Resuming The Sector Erasure Of Flash Memory
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.6.6 Resuming the Sector Erasure of Flash Memory This section describes the procedure for issuing the sector erase resume command and resuming a suspended flash memory sector erase operation. ■ Resuming the sector erasure of flash memory To resume a suspended sector erase operation, send the sector erase resume command in the command sequence table (see Table 23.4-1) to the internal flash memory.
Page 525: Flash Security Function
CHAPTER 23 2M/3M BIT FLASH MEMORY 23.7 Flash Security Function The flash security function can preserve the contents of flash memory. ■ Overview Writing the protection code, 01 , to the security bit of flash memory can limit access to flash memory.
Page 526 CHAPTER 23 2M/3M BIT FLASH MEMORY...
Page 527: Chapter 24 Examples Of Mb90F481B/Mb90F482B/Mb90F488B/Mb90F489B Serial Programming Connection
CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/ MB90F488B/MB90F489B SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/ AF210/AF120/AF110 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. 24.1 Basic Configuration of Serial Programming Connection with MB90F481B/ MB90F482B/MB90F488B/MB90F489B 24.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply)
Page 528: Basic Configuration Of Serial Programming Connection With Mb90F481B/Mb90F482B/Mb90F488B/Mb90F489B
CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING 24.1 Basic Configuration of Serial Programming Connection with MB90F481B/MB90F482B/MB90F488B/MB90F489B The MB90F481B/MB90F482B/MB90F488B/MB90F489B supports serial on-board writing (Fujitsu standard) of the flash ROM. This section provides the related specifications. ■ Basic Configuration of Serial Programming Connection with MB90F481B/ MB90F482B/MB90F488B/MB90F489B Fujitsu standard serial on-board writing uses the Yokogawa Digital Computer Corporation flash microcontroller programmer.
Page 529 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING ■ Pins used for Fujitsu standard serial on-board writing Table 24.1-1 shows the functions of the related pins used for Fujitsu Standard serial on-board writing. Table 24.1-1 Function of pins Function Description MD2, MD1,...
Page 530 AZ221 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu F MC-16LX flash microcontroller control module AZ290 Remote controller 2M bytes PC Card (Option) FLASH memory capacity of up to 128 K bytes...
Page 531 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING ■ Examples of Serial Programming Connections Examples for the following two types of connections are shown below. • Example of connection in single-chip mode (When Using the User Power Supply) • Example of minimum connection with flash microcontroller programmer (When Using the User Power Supply)
Page 532: Example Of Connection In Single-Chip Mode (When Using The User Power Supply)
CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING 24.2 Example of Connection in Single-Chip Mode (When Using the User Power Supply) In the user system, mode pins MD2 and MD0, which are set to single-chip mode, are supplied with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of AF220/AF210/ AF120/AF110, and the system is set to serial programming mode (serial programming mode: MD2, MD1, MD0=110).
Page 533 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING Similarly to P80, using the SIN0, SOT0, and SCK0 pins in the user system requires a control circuit as shown in Figure 24.2-2. The user circuit is disconnected in serial programming mode by the flash microcontroller programmer’s "/TICS" signal. Figure 24.2-2 Pin control circuit AF220/AF210/AF120/AF110 MB90F481B, MB90F482B,...
Page 534: Example Of Minimum Connection With Flash Microcontroller Programmer (When Using The User Power Supply)
CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING 24.3 Example of Minimum Connection with Flash Microcontroller Programmer (When Using the User Power Supply) If, in serial programming mode, pins (MD2, MD0, and P80) are set as shown below, MD2, MD0, and P80 do not need to be connected with the flash microcontroller programmer.
Page 535 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING Using the pins SIN0, SOT0, and SCK0 in the user system requires a control circuit as shown in Figure 24.3-2. The user circuit is disconnected in serial programming mode by the flash microcontroller programmer’s "/TICS" signal for outputting "L". Figure 24.3-2 Pin control circuit MB90F481B, AF220/AF210/AF120/AF110...
Page 536 CHAPTER 24 EXAMPLES OF MB90F481B/MB90F482B/MB90F488B/MB90F489B SERIAL PROGRAMMING...
Page 537: Chapter 25 Pwc Timer (Only Mb90485 Series)
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) This chapter provides an overview of the PWC timer, explains the configuration, the configuration and functions of its registers interrupt, shows the precautions on use. 25.1 Overview of PWC Timer 25.2 Configuration of PWC Timer 25.3 Configuration and Functions of PWC Timer Registers 25.4 Interrupt of PWC Timer 25.5 Operations of PWC Timer...
Page 538: Overview Of Pwc Timer
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.1 Overview of PWC Timer The PWC timer is a 16-bit multifunctional up-count timer used to measure the pulse width of input signals. PWC: Pulse Width Count (for pulse width measurement) ■ PWC timer functions On the hardware level, the PWC timer consists of one 16-bit up-count timer, one input pulse divider and divide ratio control register, one measurement input pin, and one 16-bit control register.
Page 539: Configuration Of Pwc Timer
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.2 Configuration of PWC Timer The PWC timer consists of the PWC control/statue register, PWC data buffer, and divide ratio control register. ■ Block diagram of PWC timer Figure 25.2-1 shows a block diagram of the PWC timer. Figure 25.2-1 Block diagram of the PWC timer PWCR read Error...
Page 540 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Pin related to PWC timer The pin related to the PWC timer has 3ch of PWC0/PWC1/PWC2 and functions as the input port when the PWC is used. The PWC0/PWC1/PWC2 pins function as the general-purpose I/O port (P36/PWC0, P37/PWC1,P75/PWC2) and input pin.
Page 541: Configuration And Functions Of Pwc Timer Registers
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.3 Configuration and Functions of PWC Timer Registers This section describes the configuration and functions of the registers used in the PWC timer. ■ List of PWC timer registers Figure 25.3-1 shows a list of the PWC timer registers. Figure 25.3-1 List of PWC timer registers (R/W) PWCSR0 to 2...
Page 542: Pwc Control/Status Register (Pwcsr0 To Pwcsr2)
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.3.1 PWC Control/Status Register (PWCSR0 to PWCSR2) This section describes the configuration and functions of the PWC control/status register (PWCSR0 to PWCSR2). ■ PWC control/status register (PWCSR0 to PWCSR2) Figure 25.3-2 shows the bit configuration of the PWC control/status register (PWCSR0 to PWCSR2).
Page 543 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) Table 25.3-2 Functions related to Read operations (indicating the operation state of the 16-bit up-count timer) STRT STOP Operation control function Timer stop mode (not started or end of measurement) (initial value) Timer count operation mode (measurement in progress) •...
Page 544 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) [bit11] OVIR (timer overflow interrupt request flag) This bit is a flag used to indicate an overflow of the 16-bit up-count timer to the area from FFFF to 0000 . If this bit is set when timer overflow interrupt requests are enabled (bit10:OVIE = "1"), a timer overflow interrupt request is generated.
Page 545 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) [bit7, bit6] CKS1, CKS0 (clock selection) These bits are used to select one internal count clock out of the three types listed in Table 25.3-3. Table 25.3-3 Count clocks of the 16-bit up-count timer CKS1 CKS0 Count clock selection...
Page 546 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) [bit3] S/C (Selection of Measurement Mode (one-shot/repeated)) This bit is used to select the measurement mode. Table 25.3-5 Selection of the measurement mode for the 16-bit up-count timer Measurement mode selection Timer mode Pulse width One-shot measurement mode Stopped after one-time...
Page 547: Pwc Data Buffer Register (Pwcr0 To Pwcr2)
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.3.2 PWC Data Buffer Register (PWCR0 to PWCR2) This section describes the configuration and functions of the PWC data buffer register (PWCR0 to PWCR2). ■ PWC data buffer register (PWCR0 to PWCR 2) Figure 25.3-3 shows the bit configuration of the PWC data buffer register (PWCR0 to PWCR2).
Page 548: Divide Ratio Control Register (Divr0 To Divr2)
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.3.3 Divide Ratio Control Register (DIVR0 to DIVR2) This section describes the configuration and functions of the divide ratio control register (DIVR0 to 2). ■ Divide ratio control register (DIVR0 to DIVR2) Figure 25.3-4 shows the bit configuration of the divide ratio control register (DIVR0 to DIVR2). Figure 25.3-4 Bit configuration of the divide ratio control register (DIVR0 to DIVR2) DIVR ch.0 000082...
Page 549: Interrupt Of Pwc Timer
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.4 Interrupt of PWC Timer The interrupt of the PWC timer occurs when an overflow of the up counter in timer function and the pulse width measurement are terminated. The PWC0 is used for PWC interrupt that can activate the DMA transfer and extended intelligent I/O service OS).
Page 550 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Interrupt of PWC timer, DMA transfer, and EI Table 25.4-1 shows the relationship between the interrupt source, interrupt vector, and interrupt control register other than software interrupt. Table 25.4-1 Interrupt source, interrupt vector, and interrupt control register μDMAC Interrupt vector Interrupt control register...
Page 551: Operations Of Pwc Timer
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5 Operations of PWC Timer This section describes the operations of the PWC timer. ■ Outline of PWC timer operations The PWC timer is a multifunction timer based on an 16-bit up-count timer, which integrates measurement input pins with the 8-bit input divide circuit.
Page 552: Operations Of The Timer Function
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.1 Operations of the Timer Function This timer is an up-count (incrementing) timer providing both reload and one-shot operations. ■ Operation of timer functions After the timer starts, its value is incremented at each pulse of the count clock. If an overflow occurs in the range "FFFF "...
Page 553: Operations Of The Pulse Width Measurement Function
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.2 Operations of the Pulse Width Measurement Function With this function, the timer can be used to measure the time interval between any input pulse events. ■ Operations of the pulse width measurement function After the start of the pulse width measurement function, counting does not start before the specified measurement start edge is input.
Page 554 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) Figure 25.5-3 Pulse width measurement operation (repeated measurement mode/"H" level pulse width measurement) PWC input pulses to be measured (Solid line indicates timer count value) Timer count value Overflow FFFF Data transfer to PWCR Timer clear Timer clear 0000...
Page 555: Selection Of Count Clock And Operation Mode
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.3 Selection of Count Clock and Operation Mode This section describes the selection of the count clock and the operation mode. ■ Count clock selection A timer count clock can be selected from among three types of internal clocks by setting PWCSR: bit7 (CKS1) and bit6 (CKS0).
Page 556 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) Table 25.5-2 shows the settings for selection of the operation mode/measurement mode. Table 25.5-2 Settings of operation mode/measurement mode Operation mode MOD2 MOD1 MOD0 Timer One-shot timer Reload timer Pulse width Rising edge or falling edge to rising One-shot measurement: measurement edge or falling edge...
Page 557: Start And Stop Of Timer/Pulse Width Measurement
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.4 Start and Stop of Timer/Pulse Width Measurement Start/restart/stop/forcible stop of each operation are controlled by setting the PWCSR: bit15, bit14 (STRT, STOP bits). ■ Start and Stop of timer/pulse width measurement Start/restart of the timer/pulse width measurement is initiated by setting the STRT bit to "0", while a forcible stop is initiated by setting the STOP bit to "0".
Page 558 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Restart Restart is defined as a start operation (setting the STRT bit to "0") performed after entering timer/pulse width measurement mode. Restart operates as follows depending on the mode: ❍ One-shot timer mode Restart has no effect.
Page 559: Timer Mode Operation
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.5 Timer Mode Operation This section describes the device operation in timer mode. ■ Clearing the timer In the following cases, the 16-bit up-count timer is cleared to "0000 ": • At reset •...
Page 560 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Interrupt generation request In timer mode, an interrupt request may be generated due to a timer overflow. If an overflow occurs due to incrementing the counter, the overflow flag is set and an overflow interrupt request is generated, if such requests are allowed.
Page 561 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Timer Operation Flow Figure 25.5-4 shows the operation flow of the timer. Figure 25.5-4 Operational flow of the timer Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Set value to PWCR Restart Start via the STRT bit Reload operation...
Page 562: Operation In Pulse Width Measurement Mode
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.5.6 Operation in Pulse Width Measurement Mode This section describes operation in pulse width measurement mode. ■ One-Shot measurement and repeated measurement There are two modes for pulse width measurement: a mode for one-time measurement and a mode for repeated measurement.
Page 563 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Selection of input pin The PWC timer provides three channels, PWC0, PWC1, and PWC2, that are used as input signal pins for the pulse width counting. Each of these channels can therefore be used independently.
Page 564 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) Table 25.5-6 List of measurement modes (2/3) Measurement MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) mode "L" pulse width measurement Start of Stop of Start Stop counting counting Measures the width of the "L" pulse. Start of counting (measurement): When rising edge is detected End of counting (measurement): When falling edge is detected Interval...
Page 565 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) Table 25.5-6 List of measurement modes (3/3) Measurement MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) mode Divide interval Stop of counting Start of counting measurement Stop Start (Example of divide-by-4) Measures an interval by dividing the input pulse with a divide ratio selected in the divide ratio control register DIVR.
Page 566 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) : divide ratio selected via the divide ratio control register DIVR (use 1, except in divide frequency measurement mode) ■ Range for counting the pulse width/interval Depending on the selected combination of count clock and divide ratio of the input divider, the allowed pulse width/interval range for measurement will vary.
Page 567 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ■ Operational flow of pulse width measurement Figure 25.5-6 shows the operational flow of pulse width measurement. Figure 25.5-6 Operational flow of pulse width measurement Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Restart Start with STRT bit...
Page 568: Notes On Pwc Timer Usage
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) 25.6 Notes on PWC Timer Usage This section provides notes on using the PWC timer. ■ Notes on PWC timer usage ❍ Notes on rewriting the register Rewriting the bits in the PWCSR is prohibited. Rewrite the register either before the timer is started or after the timer stops.
Page 569 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES) ❍ Minimum pulse width The following restrictions apply to pulses that can be input to the pulse width measurement input pin. Minimum pulse width: machine clock divided-by-2 (0.25 μs or more for 16 MHz machine •...
Page 570 CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES)
Page 571: Chapter 26 Μpg Timer (Only Mb90485 Series)
CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) This chapter provides an overview, explains the configuration of the μPG timer and its timing chart, the configuration and functions of its registers. 26.1 Overview and Configuration of μPG Timer 26.2 Configuration and Functions of μPG Timer Registers 26.3 Timing Chart of μPG Timer...
Page 572: Overview And Configuration Of Μpg Timer
CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) 26.1 Overview and Configuration of μPG Timer The μPG timer is used to output pulses based on external input. Block diagram of μPG timer ■ Figure 26.1-1 shows a block diagram of the μPG timer. Figure 26.1-1 Block diagram of μPG timer MT00 MT01...
Page 573 CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) Block diagram of pin related to μPG timer ■ Figure 26.1-2 Block diagram of pin related to μPG timer Peripheral function output Peripheral (MT00, MT01) function input (EXTC) Peripheral function output enable Port data register (PDR) Open drain control signal (P43/P44/P45 only) PDR Read...
Page 574: Configuration And Functions Of Μpg Timer Registers
CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) 26.2 Configuration and Functions of μPG Timer Registers This section describes the configuration of the registers used in the μPG timer and their functions. μPG control/status register (PGCSR) ■ The bit configuration of the μPG control/status register (PGCSR) is shown below. PGCSR μPG control status register 00008E...
Page 575 CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) [bit4, bit3] PMT1,PMT0 (invert output) These bits are used to invert the output of each pulse. PMT1 PMT0 Operation control function Waveform at the start (initial value) Only MT00 inverted Only MT01 inverted MT00 and MT01 inverted These bits are initialized to "00 "...
Page 576: Timing Chart Of Μpg Timer
CHAPTER 26 μPG TIMER (ONLY MB90485 SERIES) 26.3 Timing Chart of μPG Timer This section shows a timing chart and timing for the μPG timer. Timing chart of μPG timer ■ Figure 26.3-1 shows the timing chart of input and output signals for the μPG timer. Figure 26.3-1 Timing chart of input/output signals for the μPG timer Input waveform Output MT00...
Page 577: Chapter 27 I 2 C Interface (Only Mb90485 Series)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) This chapter provides an overview, explains configuration, interrupt, and operation of the I C interface, the configuration and functions of its registers. 27.1 Overview of I C Interface 27.2 Configuration of I C Interface 27.3 Configuration and Functions of I C Interface Registers...
Page 578: Overview Of I
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.1 Overview of I C Interface The I C interface is a serial I/O port supporting the Inter IC BUS, allowing master/slave devices to operate over the I C bus. ■ C interface function The I C interface has the following functions.
Page 579: Configuration Of I
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.2 Configuration of I C Interface ■ Block diagram of the I C interface Figure 27.2-1 shows a block diagram of the I C interface. Figure 27.2-1 Block Diagram of I C Interface ICCR C enable Clock divider 1...
Page 580 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) ■ Pin related to I C interface The pin related to the I C interface has the SDA data input/output pin and SCL clock input/ output pin. The SCL/SDA pins function as the general-purpose I/O port (P76/SCL, P77/SDA) and I C interface.
Page 581: Configuration And Functions Of I C Interface Registers
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3 Configuration and Functions of I C Interface Registers This section describes the configuration and functions of the I C interface registers. ■ List of I C interface registers ❍ Bus status register (IBSR) Bus status register Bit number Address: 000088...
Page 582: Bus Status Register (Ibsr)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3.1 Bus Status Register (IBSR) This section describes the configuration and functions of the bus status register (IBSR). ■ Bus status register (IBSR) The diagram below shows the bit configuration of the bus status register (IBSR). Bus status register Bit number Address: 000088...
Page 583 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) This bit is cleared if a start or stop condition is detected. [bit3] TRX: Transfer/Receive This bit is used to indicate transmission or reception for data transfer. Reception Transmission [bit2] AAS: Addressed As Slave This bit is used to detect the addressing mode.
Page 584: Bus Control Register (Ibcr)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3.2 Bus Control Register (IBCR) This section describes the configuration and functions of the bus control register (IBCR). ■ Bus control register (IBCR) The diagram below shows the bit configuration of the bus control register (IBCR). Bus control register Bit number Address: 000089...
Page 585 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) [bit12] MSS: Master Slave Select This bit is used to select between master mode and slave mode. After the stop condition is generated and transferred, the device enters slave mode. The device enters master mode, the start condition is generated, and transfer starts. This bit is cleared if arbitration lost is detected in master transfer mode.
Page 586 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) (During reading) Transfer has not ended. This bit is set if the following conditions are met when one byte including an acknowledge bit is transferred: • Byte transferred in bus master transfer •...
Page 587 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) • Condition 2 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs When an instruction which generates a start condition by enabling I C operation (EN bit = 1) is executed (setting the MSS bit in the IBCR register to "1") with the I C bus occupied...
Page 588 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait * for the time of three - bit data transmission at the I transfer frequency set in the clock control register (ICCR).
Page 589 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) ■ Notes on using the bus control register (IBCR) Setting the SCC bit to "1" and the MSS bit to "0" at the same time is prohibited. Writing to the SCC, MSS, and INT bits at the same time will cause a conflict between transfer of the next byte and generation of start or stop conditions.
Page 590: Clock Control Register (Iccr)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3.3 Clock Control Register (ICCR) This section describes the configuration and functions of the clock control register (ICCR). ■ Clock control register (ICCR) The diagram below shows the bit configuration of the clock control register (ICCR). Bit number Address: 00008A Clock control register...
Page 591 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) Table 27.3-1 Serial clock frequency settings Note: The "+ 4" cycle in the formula reflects the minimum overhead for checking whether the output level of the SCL pin has changed. If the rising edge of the SCL pin is delayed or a slave device delays the clock, the overhead increases.
Page 592: Address Register (Iadr)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3.4 Address Register (IADR) This section describes the configuration and functions of the address register (IADR). ■ Address register (IADR) The diagram below shows the bit configuration of the address register (IADR). Address register Bit number Address: 00008B...
Page 593: Data Register (Idar)
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.3.5 Data Register (IDAR) This section describes the configuration and functions of the data register (IDAR). ■ Data register (IDAR) The diagram below shows the bit configuration of the data register (IDAR). Data register Bit number Address: 00008C...
Page 594: Interrupt Of I 2 C Interface
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.4 Interrupt of I C Interface The interrupt of I C interface occurs when the transfer of data is terminated. ■ Interrupt control bit and interrupt source of I C interface The interrupt control bit and interrupt source of I C interface is shown in the following table.
Page 595 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) ■ Interrupt of I C interface, DMA transfer, and EI Table 27.4-1 shows the relationship between the interrupt source, interrupt vector, and interrupt control register other than software interrupt. Table 27.4-1 Interrupt source, interrupt vector, and interrupt control register μDMAC Interrupt vector Interrupt control register...
Page 596: I 2 C Interface Operation
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) 27.5 I C Interface Operation The I C bus performs communication using two bidirectional bus lines that consist of one serial data line (SDA) and one serial clock line (SCL). The I C interface has instead two open drain input/output pins (SDA, SCL) that allow hard-wired logic to be used.
Page 597 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) ■ Acknowledge Acknowledge is transmitted from the receiving side to the transmitting side. The ACK bit is used to represent an acknowledge upon data reception. If data is transmitted, an acknowledge from the receive side is stored in the LRB bit.
Page 598 CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES) ❍ Interrupt conditions There is only one interrupt that can be generated related to the I C bus. The interrupt source is generated either after the end of the transfer for one byte, or because another predefined interrupt condition was met.
Page 599: Appendix
APPENDIX The appendix provides the memory map and lists the instructions used in the F 16LX. APPENDIX A Memory Map APPENDIX B I/O Map APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register APPENDIX D Instructions...
Page 600: Appendix A Memory Map
APPENDIX APPENDIX A Memory Map Memory space is divided according to three usage modes. ■ Memory space The memory space is divided according to three usage modes shown in Figure A-1. Figure A-1 Memory Map Single chip Internal ROM/external bus External ROM/external bus FFFFFF ROM area ROM area...
Page 601 APPENDIX A Memory Map Table A-1 shows the relationship among address #1, address #2, and address #3 for each product type. Table A-1 Relationship among address #1, address #2, and address #3 by product type Type Address #1 Address #2 Address #3 MB90F481B FC0000...
Page 602 APPENDIX Figure A-2 shows the MB90F489B memory map. Figure A-2 MB90F489B memory map External ROM/external bus Single chip Internal ROM/external bus MB90F489B MB90F489B MB90F489B FFFFFF ROM area ROM area FD0000 FCFFFF FC0000 FBFFFF ROM area ROM area F90000 F8FFFF F80000 F7FFFF 010000 00FFFF...
Page 603: Appendix B I/O Map
APPENDIX B I/O Map APPENDIX B I/O Map Table B-1 shows the addresses assigned to the registers for each peripheral function. ■ I/O maps Table B-1 shows the addresses assigned to the registers for each peripheral function. Table B-1 I/O Map (1/8) Address Register Abbreviation...
Page 604 APPENDIX Table B-1 I/O Map (2/8) Address Register Abbreviation Access Resource Initial value 00000000 (MB90480 series) Port 7 direction register DDR7 Port 7 XX000000 (MB90485 series) Port 8 direction register DDR8 Port 8 00000000 Port 9 direction register DDR9 Port 9 00000000 Port A direction register DDRA...
Page 605 APPENDIX B I/O Map Table B-1 I/O Map (3/8) Address Register Abbreviation Access Resource Initial value Communication Clock division control register SDCR1 0---0000 prescaler (SCI1) PPG reload register L (ch.0) PRLL0 XXXXXXXX PPG reload register H (ch.0) PRLH0 XXXXXXXX PPG reload register L (ch.1) PRLL1 XXXXXXXX PPG reload register H (ch.1)
Page 606 APPENDIX Table B-1 I/O Map (4/8) Address Register Abbreviation Access Resource Initial value Output compare register (ch.0) 00000000 lower OCCP0 Output compare register (ch.0) 00000000 upper Output compare register (ch.1) 00000000 lower OCCP1 Output compare register (ch.1) 00000000 upper Output compare register (ch.2) 00000000 lower OCCP2...
Page 607 APPENDIX B I/O Map Table B-1 I/O Map (5/8) Address Register Abbreviation Access Resource Initial value Timer data register lower TCDT 00000000 Timer data register upper TCDT 00000000 16-bit output Timer control status register TCCS 00000000 timer Timer control status register TCCS 0--00000 free-run timer...
Page 608 APPENDIX Table B-1 I/O Map (6/8) Address Register Abbreviation Access Resource Initial value Reserved area divide ratio control register DIVR1 PWC (ch.1) ------00 Reserved area divide ratio control register DIVR2 PWC (ch.2) ------00 Reserved area bus status register IBSR 00000000 bus control register IBCR 00000000...
Page 609 APPENDIX B I/O Map Table B-1 I/O Map (7/8) Address Register Abbreviation Access Resource Initial value Flash memory control status FMCR W,R/W Flash memory I/F 000X0000 register Use prohibited Interrupt control register 00 ICR00 W,R/W 00000111 Interrupt control register 01 ICR01 W,R/W 00000111...
Page 610 Program address detection 1FF5 XXXXXXXX register 1 (upper) * : These registers are only for MB90485 series. They are used as the reserved area on MB90480 series. Note: Descriptions for read/write R/W: Readable/Writable Read only Write only Descriptions for initial value The initial value of this bit is “0”.
Page 611: Appendix C Interrupt Source, Interrupt Vector, And Interrupt Control Register
APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register Table C-1 shows the relationship between interrupt sources and the interrupt vector/ interrupt control registers. ■ Interrupt sources, interrupt vectors, and interrupt control registers Table C-1 Relationship between interrupt sources and interrupt vector/interrupt control registers (1/2) Interrupt control μDMAC...
Page 612 APPENDIX Table C-1 Relationship between interrupt sources and interrupt vector/interrupt control registers (2/2) Interrupt control μDMAC Interrupt vector register Interrupt source channel clear number Number Address Number Address ❍ Input capture (ch.1) load FFFF90 ICR08 0000B8 ❍ Output compare (ch.0) match FFFF8C ❍...
Page 613: Appendix D Instructions
APPENDIX D Instructions APPENDIX D Instructions APPENDIX D describes the instructions used by the F MC-16LX. D.1 Instruction Types D.2 Addressing D.3 Direct Addressing D.4 Indirect Addressing D.5 Execution Cycle Count D.6 Effective address field D.7 How to Read the Instruction List D.8 F MC-16LX Instruction List D.9 Instruction Map...
Page 614: Instruction Types
APPENDIX Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 615: Addressing
APPENDIX D Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 616 APPENDIX ■ Effective Address Field Table D.2-1 lists the address formats specified by the effective address field. Table D.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the (RL1) byte, word, and long word types in order from the None left.
Page 617: Direct Addressing
APPENDIX D Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure D.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212 (This instruction stores the operand value in A.) Before execution...
Page 618 APPENDIX Figure D.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6 2 5 3 4 Memory space After execution A 0 7 1 6 2 5 6 4 Memory space...
Page 619 APPENDIX D Instructions ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000 to 0000FF is accessed regardless of the data bank register (DTB) and direct page register (DPR).
Page 620 APPENDIX ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure D.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB i : 0C1 : 0 (This instruction sets bits by I/O direct bit addressing.)
Page 621 APPENDIX D Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure D.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)
Page 622: Indirect Addressing
APPENDIX Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 623 APPENDIX D Instructions Figure D.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0 7 1 6 2 5 3 4 Memory space...
Page 624 APPENDIX ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): •...
Page 625 APPENDIX D Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 626 APPENDIX Figure D.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E × × × × 0 2 0 1 ×...
Page 627 APPENDIX D Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB).
Page 628: Execution Cycle Count
APPENDIX Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■...
Page 629 APPENDIX D Instructions ■ Calculating the Execution Cycle Count Table D.5-1 lists execution cycle counts and Table D.5-2 and Table D.5-3 summarize correction value data. Table D.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in Code Operand each addressing mode Execution cycle count in each addressing mode...
Page 630 APPENDIX Table D.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address External data bus...
Page 631: Effective Address Field
APPENDIX D Instructions Effective address field Table D.6-1 shows the effective address field. ■ Effective Address Field Table D.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order from the left.
Page 632: How To Read The Instruction List
APPENDIX How to Read the Instruction List Table D.7-1 describes the items used in the F MC-16LX Instruction List, and Table D.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table D.7-1 Description of Items in the Instruction List (1/2) Item Description Uppercase, symbol: Represented as is in the assembler.
Page 633 APPENDIX D Instructions Table D.7-1 Description of Items in the Instruction List (2/2) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution.
Page 634 APPENDIX Table D.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing addr16 Direct addressing addr24...
Page 635: Mc-16Lx Instruction List
APPENDIX D Instructions MC-16LX Instruction List Table D.8-1 to Table D.8-18 list the instructions used by the F MC-16LX. ■ MC-16LX Instruction List Table D.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) A,dir byte (A) ← (addr16) A,addr16 byte (A) ←...
Page 636 APPENDIX Table D.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation word (A) ← (dir) MOVW A,dir word (A) ← (addr16) MOVW A,addr16 word (A) ← (SP) MOVW A,SP word (A) ← (RWi) MOVW A,RWi word (A) ← (ear) MOVW A,ear word (A) ←...
Page 637 APPENDIX D Instructions Table D.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 byte (A) ← (A) + (dir) A,dir byte (A) ← (A) + (ear) A,ear byte (A) ← (A) + (eam) A,eam 4 + (a) byte (ear) ←...
Page 638 APPENDIX Table D.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 byte (eam) ← (eam) + 1 5+(a) 2 x (b) byte (ear) ← (ear) - 1 byte (eam) ← (eam) - 1 5+(a) 2 x (b) word (ear) ←...
Page 639 APPENDIX D Instructions Table D.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) DIVU A,eam word (A) / byte (eam)
Page 640 APPENDIX Table D.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) A,eam word (A) / byte (eam) quotient →...
Page 641 APPENDIX D Instructions Table D.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation byte (A) ← (A) and imm8 A,#imm8 byte (A) ← (A) and (ear) A,ear byte (A) ← (A) and (eam) A,eam 4+(a) byte (ear) ← (ear) and (A) ear,A byte (eam) ←...
Page 642 APPENDIX Table D.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear long (A) ← (A) or (eam) A,eam 7+(a) long (A) ←...
Page 643 APPENDIX D Instructions Table D.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← With right rotation carry RORC byte (A) ← With left rotation carry ROLC byte (ear) ← With right rotation carry RORC byte (eam) ← With right rotation carry RORC 5+(a) 2 x (b)
Page 644 APPENDIX Table D.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 BC/BLO rel Branch on (C) = 1 BNC/ Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0 Branch on (T) = 1...
Page 645 APPENDIX D Instructions Table D.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9 Branch on byte (eam) not equal to imm8...
Page 646 APPENDIX Table D.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (PS) PUSHW (SP) ←...
Page 647 APPENDIX D Instructions Table D.8-16 21 Bit Operand Instructions Mnemonic Operation byte (A) ← (dir:bp)b MOVB A,dir:bp byte (A) ← (addr16:bp)b MOVB A,addr16:bp byte (A) ← (io:bp)b MOVB A,io:bp bit (dir:bp)b ← (A) MOVB dir:bp,A 2 x (b) bit (addr16:bp)b ← (A) MOVB addr16:bp,A 2 x (b)
Page 648 APPENDIX Table D.8-18 10 String Instructions Mnemonic Operation byte transfer @AH+ ← @AL+, counter = RW0 MOVS / MOVSI byte transfer @AH- ← @AL-, counter = RW0 MOVSD byte search @AH+ ← AL, counter RW0 SCEQ / SCEQI byte search @AH- ← AL, counter RW0 SCEQD byte fill @AH+ ←...
Page 649: Instruction Map
APPENDIX D Instructions Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table D.9-2 to Table D.9-21 summarize the F MC-16LX instruction map. ■ Structure of Instruction Map Figure D.9-1 Structure of Instruction Map Basic page map : Byte 1...
Page 650 APPENDIX Figure D.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand Operand code [Basic page map] [Extended page map]* *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 651 APPENDIX D Instructions Table D.9-2 Basic Page Map...
Page 652 APPENDIX Table D.9-3 Bit Operation Instruction Map (First Byte = 6C...
Page 653 APPENDIX D Instructions Table D.9-4 Character String Operation Instruction Map (First Byte = 6E...
Page 654 APPENDIX Table D.9-5 2-byte Instruction Map (First Byte = 6F...
Page 655 APPENDIX D Instructions Table D.9-6 ea Instruction 1 (First Byte = 70...
Page 656 APPENDIX Table D.9-7 ea Instruction 2 (First Byte = 71...
Page 657 APPENDIX D Instructions Table D.9-8 ea Instruction 3 (First Byte = 72...
Page 658 APPENDIX Table D.9-9 ea Instruction 4 (First Byte = 73...
Page 659 APPENDIX D Instructions Table D.9-10 ea Instruction 5 (First Byte = 74...
Page 660 APPENDIX Table D.9-11 ea Instruction 6 (First Byte = 75...
Page 661 APPENDIX D Instructions Table D.9-12 ea Instruction 7 (First Byte = 76...
Page 662 APPENDIX Table D.9-13 ea Instruction 8 (First Byte = 77...
Page 663 APPENDIX D Instructions Table D.9-14 ea Instruction 9 (First Byte = 78...
Page 664 APPENDIX Table D.9-15 MOVEA RWi, ea Instruction (First Byte = 79...
Page 665 APPENDIX D Instructions Table D.9-16 MOV Ri, ea Instruction (First Byte = 7A...
Page 666 APPENDIX Table D.9-17 MOVW RWi, ea Instruction (First Byte = 7B...
Page 667 APPENDIX D Instructions Table D.9-18 MOV ea, Ri Instruction (First Byte = 7C...
Page 668 APPENDIX Table D.9-19 MOVW ea, Rwi Instruction (First Byte = 7D...
Page 669 APPENDIX D Instructions Table D.9-20 XCH Ri, ea Instruction (First Byte = 7E...
Page 670 APPENDIX Table D.9-21 XCHW RWi, ea Instruction (First Byte = 7F...
Page 671: Index
Index ......322 Numerics List of 8/16-bit PPG timer registers ..264 List of 8/16-bit up/down counter/timer registers 16-bit Major functions of 8/16-bit up/down ......302 16-bit reload register (TMRLR) .........260 counter/timer ........301 16-bit timer register (TMR) ....333 Outline of 8/16-bit PPG timer operation 16-bit timer register ......320 Pin related to 8/16-bit PPG timer...
Page 672 ........ 378 Handling of analog input pins Arbitration ............574 Arbitration ........... 31 Accumulator (A) ARSR A/D converter Automatic ready function selection register ....357 Block diagram of 8/10-bit A/D converter ..........162 (ARSR) Block diagram of pin related to 8/10-bit Asynchronous mode ........
Page 673 ..... 558 ......451 Block diagram of pin related to I C interface Chip selection area register (CARx) Block diagram of pin related to μPG timer ....551 .....452 Chip selection control register (CSCR) ....518 ....454 Block diagram of pin related to PWC timer Example of using the chip selection facility ....
Page 674 .... 274 Reload/compare register (ch0/ch1) (RCR0/1) Connection between CPUs in two-way ....280 ........432 Selection of reload and compare functions communication ....125, 131 Up/down count at any width in reload/compare CPU intermittent operation mode ..........281 ..124 function CPU operation mode and current consumption ......
Page 675 ....78 Interrupt of 16-bit reload timer,DMA transfer,and Extended intelligent I/O service (EI ..........303 ......85 Flowchart of Operation of EI Interrupt of 8/10-bit A/D converter,DMA transfer,and Interrupt of 16-bit input/output timer,DMA transfer, ..........367 ..........236 and EI Interrupt of 8/16-bit PPG timer,DMA transfer, Interrupt of 16-bit reload timer,DMA transfer, and ..........
Page 676 ..495 Pin states in external bus 8-bit data bus mode and Setting the flash memory to the read/reset state ....145 ..501 multiplex 8-bit external bus mode Suspending sector erasure for the flash memory ........ 496 Pin states in external bus 8-bit data bus mode and Writing data to flash memory ..
Page 677 IDAR ..........571 Data register (IDAR) Block diagram of expanded I/O serial ......34 Interrupt level mask register (ILM) ..........387 interface Initial value Block diagram of pin related to expanded I/O .......337 ........388 Initial value of hardware components serial interface .............
Page 678 ....148 ....214 Change to standby mode and interrupts Interval interrupt function of watch timer ......54 ......49 Configuration of hardware interrupt List of interrupt control registers Configuration of interrupt control register List of registers in delay interrupt generation ........
Page 679 Example of μDMAC start in stop mode ....374 Notes on Accessing the Low-Power Consumption Mode List of μDMAC registers ........67 Control Register (LPMCR) to Enter the Standby μDMAC functions ..........150 ..........67 Mode μDMAC operations ..........69 Operational state in low-power consumption μDMAC processing procedure ..........
Page 680 (PADR0 and PADR1) ....183 Port output pin registers (ODR7,ODR4) Program Address Detection Registers On-board ........463 (PADR0,PADR1) Pins used for Fujitsu standard serial on-board Patch ..........507 writing ........470 Flow of Patch Processing One-Shot Operation of Address Match Detection Function at Storing One-Shot measurement and repeated ......
Page 681 Product Pin states in external bus 8-bit data bus mode and multiplex ......145 8-bit external bus mode ..........4 Product configuration Program Configuration of PLL output selection register Operation of Address Match Detection Function at Storing ..........115 (PLLOS) ......469 Patch Program in E PROM ..........465...
Page 682 ..267 PWCR Counter control register (ch1) upper (CCRH1) ....... 271 ..525 Counter status register 0/1 (CSR0/1) PWC data buffer register (PWCR0 to PWCR 2) ........... 571 Data register (IDAR) PWCSR ...... 366 Data registers (ADCR2 and ADCR1) PWC control/status register ..........
Page 683 Reload timer PPG1/3/5 operation mode control register ......... 325 (PPGC1/3/5) Block diagram of pin related to 16-bit reload Program Address Detection Control Status Register ...........295 timer ..........461 (PACSR) ....294 Block diagram of the 16-bit reload timer Program Address Detection Registers .......303 Interrupt of 16-bit reload timer ........
Page 684 SDCR Single-Chip Communication prescaler control register0/1 Example of Connection in Single-Chip Mode (When Using ........395 ......510 (SDCR0/SDCR1) the User Power Supply) Slave ...... 394 Serial data register 0/1 (SDR0/SDR1) Communication procedure of master/slave communication ..........435 function Sector Connection between CPUs in master/slave ..........
Page 685 ....319 Stop mode Block diagram of the 8/16-bit PPG timer ..........537 ........139 Clearing the timer Canceling the stop mode ......218 ........... 139 Functions of 16-bit input/output timer Change to stop mode Example of μDMAC start in stop mode ......318 ....
Page 686 Microcontroller Programmer (When Using the Writing ........ 512 User Power Supply) ....478 Methods for writing/erasing flash memory User stack pointer Pins used for Fujitsu standard serial on-board User stack pointer (USP) and system stack pointer ..........507 writing ............ 32 (SSP) ......... 283...
Page 687 CM44-10121-5E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90480/485 Series HARDWARE MANUAL November 2006 the fifth edition FUJITSU LIMITED Electronic Devices Published Business Promotion Dept. Edited...

This manual is also suitable for:

Mb90485 series Mb90v485b Mb90487b Mb90f488b Mb90f481b Mb90v480b ... Show all

Fujitsu MB90480 Series Hardware Manual

Chapter 1 Overview of Mb90480/485 Series

Chapter 2 Cpu

Chapter 3 Interrupt

Chapter 4 Reset

Chapter 5 Clocks

Chapter 6 Low-Power Consumption Mode

Chapter 7 Mode Setting

Chapter 8 I/O Port

Chapter 9 Timebase Timer

Chapter 10 Watchdog Timer

Chapter 11 Watch Timer

Chapter 12 16-Bit Input/Output Timer

Chapter 13 8/16-Bit Up/Down Counter/Timer

Chapter 14 16-Bit Reload Timer

Chapter 15 8/16-Bit Ppg Timer

Chapter 16 Dtp/External Interrupts

Chapter 17 8/10-Bit A/D Converter

Chapter 18 Expanded I/O Serial Interface

Chapter 19 Uart

Chapter 20 Chip Selection Facility

Chapter 21 Address Match Detection Function

Chapter 22 Rom Mirror Function Selection Module

Chapter 23 2M/3M Bit Flash Memory

Chapter 24 Examples of Mb90F481B/Mb90F482B/Mb90F488B/Mb90F489B Serial Programming Connection

Chapter 25 Pwc Timer (Only Mb90485 Series)

CHAPTER 26 Μpg TIMER (ONLY MB90485 SERIES)

Chapter 27 I 2 C Interface (Only Mb90485 Series)

Appendix

APPENDIX A Memory Map

APPENDIX B I/O Map

APPENDIX C Interrupt Source, Interrupt Vector, and Interrupt Control Register

APPENDIX D Instructions

Quick Links

Related Manuals for Fujitsu MB90480 Series

Summary of Contents for Fujitsu MB90480 Series